KR20020051303A - Polarity detection circuit and method for high-order QAM - Google Patents

Abstract

PURPOSE: A polarity decision phase detector circuit for a high order quadrature modulation(QAM) and a method thereof are provided, which detects frequencies in a wider band without a subsidiary circuit. CONSTITUTION: A multiplier(20) outputs a compensation signal(q(n)) by multiplying a received QAM signal by an output signal(v(n)) from a voltage controlled oscillator(VCO)(70). A power detector(30) detects a signal having a high SNR characteristics among the compensation signal applied from the multiplier. Polarity decision units(30,40) decide polarities of I and Q channel respectively by inputting an output signal from the polarity decision units. A phase detector(50) detects a phase error by inputting an output signal(p(n)) of the polarity decision units and the output signal(q(n)) of the multiplier. A loop filter(60) filters the phase error detected through the phase detector and provides it to the VCO. And a symbol determination unit(80) generates decision data by determining a symbol by inputting the compensation signal being output from the multiplier.

Description

Polarity detection circuit and method for high-order QAM}

The present invention relates to a polarity determination phase detection circuit for high-order quadrature modulation (QAM), and more particularly, to a phase decision carrier synchronization phase having a wide range of frequency capturing performance. The present invention relates to a phase detector (PD).

In the conventional decision-directed (DD) scheme, the frequency offset capture performance of 256QAM is less than ± 10 kHz, requiring an auxiliary phase detection circuit for AFC (automatic frequency control) or carrier recovery.

One of the difficult problems faced when designing a modem using higher-order QAM modulation is carrier synchronization. QAM signals are multi-level signals and most systems employing QAM not only have broadcast signal characteristics but also perform carrier synchronization in the form of blinds without preamble in order to increase data efficiency. Becomes difficult.

The carrier of QAM has two channels of I and Q independently, such as quadrature phase shift keying (QPSK), and because of similarity in amplitude modulation, carrier for QPSK such as 4th order power and decision directed (DD) algorithm Synchronous algorithms have been used.

However, when the algorithm is applied to the QAM, the capture performance deteriorates as the higher order QAM is detected. In the higher order QAM, symbols that are not at the diagonal point as in QPSK detect an incorrect phase error.

In an effort to solve these problems, Sari & Moridi has published the article "New Phase and Frequency Detectors for Carrier Recovery in PSK and QAM Systems", IEEE Trans. Commum., Vol. 36, pp.1035-1043, Sept. 1988 applied a phase detector algorithm only to symbols within the crystal boundary by taking a square-shaped window on a symbol located diagonally. However, this algorithm was only applicable to low-order QAM where the number of input symbols and window coverage could be relatively large.

In addition, N.K. Jablon describes "Joint Blind Equalization, Carrier Recovery, and Timing Recovery for High-Order QAM Constellations" IEEE Trans. In Signal Processing, Vol.40, pp.1383-1398, June 1992, four points in the four ears of square QAM with good signal / noise ratio (SNR) were used to induce robust capture performance by the DD method. In addition, as the higher order QAMs, the number of symbols is stochastically decreased, and due to the application of the DD method for data determination, satisfactory capture performance was not obtained.

Phase detectors (PDs) can evaluate performance by observing the average power and dispersion characteristics of a PD called an S-curve. The wider the S-curve linear section of the PD, the wider the frequency and phase acquisition range.

S-curve characteristics for 64, 256 and 1024QAM by the traditional DD algorithm are shown in FIG. Referring to FIG. 1A, the intervals of [10 °, 10 °] are shown at 1 ° intervals, and the other sections are shown at 5 ° intervals for the sake of simplicity of FIG. The linear region was about [-7.2 °, 7.2 °] for 64QAM, [-3.5 °, 3.5 °] for 256QAM, and about [-1.8 °, 1.8 °] for 1024QAM. The linear region decreases as the higher-order QAM is obtained because the constellation is denser as the higher-order QAM becomes smaller, and the angle between symbol decision boundaries becomes narrower. Also, as the level of QAM increases, the capture performance deteriorates.

1B shows the dispersion characteristic of the S-curve for the PD output. In each QAM, since the dispersion amount is small at the linear section point, stable capture performance can be expected.

The reason why the S-curve characteristics become more complicated and difficult to analyze toward higher order QAM will be described with reference to FIG. 2. For the constellation points located at relatively small signal level (3,3) and relatively large level (9,9), the decision symbol can be frequently changed by DD hard decision according to phase rotation by frequency offset. . In FIG. 2, an asterisk denotes a point where the trace meets the trajectory caused by the phase rotation of the signal and a boundary value of Re or Im that distinguishes the determination region of each symbol. In other words, the crystal region changes at the point where an asterisk appears as the phase rotates. In (3,3), the point where the signal decision point is changed can be represented relatively visually through an asterisk, but in (9,9), it is shown that the asterisks are closely located so that it is difficult to distinguish the boundary. As the constellation points are denser and higher, the S-curve becomes more complicated because different phases frequently output different decision errors according to their phase rotations. In addition, the S-curve characteristic of the DD scheme is mathematically complicated because it must be represented in a linear combination considering each case for each signal determination range.

3A and 3B illustrate S-curve characteristics and dispersion characteristics when a conventional DD PD is applied using a signal having a high SNR characteristic passed through a conventional power detector. The S-characteristic is zigzag-shaped, because the crystal point changes with phase rotation. For example, FIG. 2 shows a situation when a constellation point such as (15, 15) is hardly determined according to the phase rotation. Since the symbol region is determined at the point where each decision level of Re or Im that determines each symbol region is determined, the DD-system outputs a nonlinear error whenever the determination region is changed. This makes the PLL difficult to capture and may cause hang-ups.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art as described above, and an object thereof is to provide a polarity determination phase detection circuit for a higher order QAM capable of capturing a wide range of frequencies without an auxiliary circuit.

1 is a diagram showing phase detection characteristics of a higher-order QAM by a conventional DD method.

1A is an S-curve characteristic diagram,

1b is an S-curve dispersion characteristic diagram,

2 is a 256QAM constellation diagram at an upper limit;

3A and 3B are S-curve characteristics and dispersion characteristics.

4 is a block diagram of a polarity determination phase detection circuit for higher order QAM according to an embodiment of the present invention.

5 is a view showing the polarity determination PD characteristics when the power detector of the present invention is applied,

5A is an S-curve characteristic diagram,

5b is an S-curve dispersion characteristic diagram,

6 is a constellation diagram for a polarity determination algorithm;

* Description of the symbols for the main parts of the drawings *

10: multiplier 20; Power detector

30, 40: polarity determiner 50: phase detector

60: loop filter 70: VCO

80: symbol determination means

The present invention for achieving the above object is a multiplier for outputting a compensation signal by multiplying the received QAM signal with the output signal from the voltage controlled oscillator; A power detector for detecting a symbol having a high SNR characteristic among compensation signals applied from the multiplier; A polarity judging unit for determining the polarity by inputting the output signal detected from the power detector; A phase detector for detecting a phase error by inputting an output signal of the polarity determiner and an output signal of the multiplier; A loop filter for filtering the phase error detected through the phase detector to provide the voltage controlled oscillator; It is characterized in that it provides a polarity determination phase detection circuit for a higher order QAM having a symbol determination means for determining a symbol according to a compensation signal output from the multiplier to generate decision data.

The polarity determiner inputs the output signal detected from the power detector to independently determine the polarity of the I and Q channels, respectively, and the symbol determination means selects the symbol determination threshold level as the intermediate point between the symbols to determine the symbol. Characterized in that.

In addition, the present invention includes the steps of outputting a compensation signal from the received QAM signal and phase error; Detecting a symbol having a high SNR characteristic among the compensation signals; Determining the polarity by inputting the detection signal; Detecting a phase error from the result of the polarity determination and the compensation signal; Providing the detected phase error to the QAM signal to generate a compensation signal and determining a symbol from the compensation signal at the same time to provide a polarity determination phase detection method for high frequency QAM. It features.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings in order to describe the present invention in more detail.

4 is a block diagram of a polarity determination phase detection circuit for higher order QAM according to an embodiment of the present invention.

Referring to FIG. 4, the polarity determination phase detection circuit for the higher order QAM of the present invention multiplies the received QAM signal with the output signal v (n) from the voltage controlled oscillator 70 to compensate the signal q (n). ) And a power detector 30 for detecting a signal having a high SNR characteristic among the compensation signal q (n) applied from the multiplier 20, and the power detector 30. A polarity determiner 30, 40 for determining the polarity of the I and Q channels by inputting the detected output signal, an output signal (( p (n) )) and the multiplier of the polarity determiner 30, 40, respectively. A phase detector 50 for detecting a phase error by inputting an output signal ( q (n) ), and filtering the phase error detected through the phase detector 50 to the VCO 70. A loop filter 60 for inputting a compensation signal output from the multiplier 10 to determine a symbol to generate decision data; And a determining means (80).

The operation of the polarity determination phase detection circuit for the higher order QAM having the above configuration will be described with reference to the characteristic diagrams of FIGS. 5 and 6 as follows.

First, in order to analyze the PD characteristics, the received QAM signal modeling is represented as in Equation (1). Equation (1) assumes that the system is fully equalized first, and that symbol timing recovery and gain control are fully accomplished.

Here, y (n) means the output of the equalizer and means the nth transmitted symbol as a (n) = a _I (n) + ja _Q (n) . wc is the carrier frequency, T is the symbol period, φ (n) is an uncompensated phase term that includes frequency offset, phase offset, and phase jitter, and v (n) is AWGN.

Traditional decision directed (DD) phase detection algorithms detect a phase by determining the transmitted symbol as the nearest constellation of the received symbol. This algorithm selects the symbol decision threshold level as the distance between symbols and performs symbol decision. When the compensated signal q (n) of Fig. 1 is expressed in polar coordinate form as shown in equation (2) and entered into a symbol region (representative symbol in the region = ?? (n) ), the compensated signal and its point The phase detection error between symbols is calculated as shown in equation (3).

Where r is the signal radius and θ (n) is the angle between the Re axis and the received signal.

Where Im denotes an imaginary part of {·} and the error signal Ψ (n) depends on the position of the compensated signal q (n) .

The polarity determination phase detection circuit of FIG. 5 detects a signal having a high SNR characteristic by the power detector 20, and the polarity determination devices 30 and 40 determine the polarity by using a symbol selected by the power detection. The carrier synchronization algorithm calculates a phase error through the phase detector 50 after the operation.

Therefore, the received QAM signal y (n) is multiplied by the output signal of the VCO 80 to output the compensated signal q (n) , and the PD is determined by the power detector according to the condition as shown in Equation (4). Is determined.

Here, τ is a critical radius value that can be changed according to the expected input frequency offset. Signals having a power greater than τ ² are independently polarized through the polarity determiner 30 and 40 in the I and Q channels, respectively, and the phase error is calculated through the phase detector 50.

In order to explain the phase detection operation of the present invention in more detail, the signal constellation diagram for the upper limit of 256QAM is shown in FIG. 6. If the output p (n) of the polarity determiner is the upper limit, it can be expressed as Equation (5).

In order to calculate the phase error signal, (n) in the formula (5) Dividing by (n) gives the same expression (6).

Where r and θ (n) are respectively means the magnitude and angle of (n) , and θ (n) is a component such as arg [( a (n) ))] + phase error ( φ (n)-?? φ (n) = Θ (n) ) It consists of. Since A is a case of one upper limit, a constant greater than zero can be obtained as follows.

If the transmission signal a (n) is a signal located diagonally, it can be expressed as θ (n) = π / 4 + Θ (n) , and if r = 2A , the PD output is output as sin Θ (n) Here , the interval of Θ (n) is [-π / 4, π / 4].

In the phase detection of the present invention, the analysis of the S-curve characteristic is shown in (Table 1). Table 1 shows the number of selection symbols, symbol input probability, and lock error range for the critical radius τ at 256QAM in a noise-free environment. In the case of 256QAM, there are 32 radiuses having different sizes, and 31 critical radius values τ exist between them. The τ value shown in Table 1 represents the median radius value between two adjacent radii for a signal having a high SNR. As the value of τ decreases, the number of symbols satisfying the condition increases, and thus the probability of occurrence increases. The meaning of the lock error range means the maximum error phase error that occurs when a signal that is not on the diagonal is determined to be a signal on the diagonal.

Based on Table 1, the average PD output characteristic of the present invention can be derived as shown in Equation (8). This is the average value of the PD output by each of the selected symbols and the exact expression for the S-curve assuming that the symbols input to the PD are equal probabilities.

Here, k means the k-th symbol in the total number N of the selected symbol represented by keureoseuteo in Figure 6, and P1 (k) and P _Q (k) refers to the polarity determination signal from the I and Q channels. The remaining parameters have the same meanings as in equation (7). If we consider the S-curve for the whole constellation point, the average output characteristic of the PD is expressed as the product of PDave and Pi .

The polarity determination algorithm of the present invention may be concerned about the DC offset in the S-curve but can lead to robust and fast acquisition without the DC offset since the selected symbols have a symmetrical distribution from the diagonal axis.

In addition, in the polarity determination algorithm of the present invention, the dispersion characteristic for the PD output can be obtained as shown in Equation (9).

As described above, according to the present invention, the linear symbols of the S-curve are widened by filtering the outer symbols having a high SNR by using the power detector 20 and determining the polarity by using the output of the power detector 20. . 5A and 5B show the polarity determination PD characteristics of the present invention, respectively. The polarity determination PD characteristic of the present invention has the S-curve as shown in FIG. It can be seen that.

In addition, the characteristic according to the critical radius value τ can be seen that the larger the τ value, the wider the linear section. If the value of τ is 20.5, the corresponding symbol is 4 vertices and represents the S-curve characteristic corresponding to QPSK. If the value of τ is 19.2, it is linear only in the [41.9 °, 41.9 °] section. .

The reason why the linear section decreases as the value of τ decreases is because in addition to the signal located at the diagonal, there are two signals left and right out of the diagonal by 4.1 °. It can be seen that as the phase rotation occurs due to the polarity determination early from 4.1 to the upper limit from the upper limit. Similarly, when the value of tau is 17.9, signals that are 4.1 ° and 8.7 ° away from the diagonal exist left and right. These signals also cause regions of "A" and "B" in FIG. 2 to make nonlinear sections, thereby reducing the linear region to [-36 °, 36 °].

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

According to the present invention as described above, the conventional phase detection circuit can only compensate the frequency offset of about ± 10KHz for 256QAM, and at the lowest frequency offset in the general analog front-edge stage to compensate up to ± 100KHz In addition, the introduction of AFC and the application of a wideband carrier recovery algorithm are inevitable. However, the phase detection circuit that detects the phase error by using the power detection of the present invention has an advantage of compensating an offset of ± 300 KHz at SNR = 30 dB without a conventional auxiliary circuit.

In addition, by applying a gear-shift PLL that converts the loop gain in stages, stable tracking performance in a steady state was obtained. In other words, the system is designed with a small value of τ at the beginning of the PLL to reduce the probability of PD idling and to increase the loop gain to widen the capture range. There was an advantage that can be corrected by increasing the residual frequency offset. In addition, when the system is finally stabilized, it is possible to perform perfect carrier synchronization by performing fine phase tracking by switching to the DD mode to reduce phase jitter due to the rest of the PD.

Claims (6)

A multiplier for multiplying the received QAM signal with an output signal from a voltage controlled oscillator to output a compensation signal; A power detector for detecting a symbol having a high SNR characteristic among compensation signals applied from the multiplier; A polarity judging unit for determining the polarity by inputting the output signal detected from the power detector; A phase detector for detecting a phase error by inputting an output signal of the polarity determiner and an output signal of the multiplier; A loop filter for filtering the phase error detected through the phase detector to provide the voltage controlled oscillator; And a symbol determination means for determining a symbol according to a compensation signal output from the multiplier to generate decision data. 2. The polarity determination phase detection circuit of claim 1, wherein the polarity determiner inputs an output signal detected from the power detector to independently determine polarities of I and Q channels, respectively. 2. The polarity determination phase detection circuit of claim 1, wherein the symbol determination means determines a symbol by selecting a symbol determination threshold level as a distance midpoint between symbols. Outputting a compensation signal from the received QAM signal and the phase error; Detecting a symbol having a high SNR characteristic among the compensation signals; Determining the polarity by inputting the detection signal; Detecting a phase error from the result of the polarity determination and the compensation signal; And generating a compensation signal by feeding back the detected phase error to the QAM signal, and determining a symbol from the compensation signal at the same time. 5. The method of claim 4, wherein the polarity determination independently determines the polarity of the I and Q channels, respectively, from the detection signal. 5. The method of claim 4, wherein the symbol determination determines a symbol by selecting a symbol determination threshold level as a distance midpoint between symbols.