KR20020050270A - Dynamically adjusting a processor's operational parameters according to its environment - Google Patents

Abstract

When the computer system detects a change in one of a number of operating characteristics, the system stops core clocks running on the processor. The updated frequency control information is supplied to the clock control logic in response to the detected change, and the updated voltage control information is supplied to the voltage control circuit in response to the change. Once the updated information is supplied, the system is configured to operate the clocks to operate the processor at a second clock frequency corresponding to the updated frequency control information and at a second voltage corresponding to the updated voltage control information. Resume.

Description

DYNAMICALLY ADJUSTING A PROCESSOR'S OPERATIONAL PARAMETERS ACCORDING TO ITS ENVIRONMENT}

Conventional notebook computers have power and thermal limitations that allow them to operate at performance levels below the same desktop computer. When using a battery as a power source, conventional notebook computers can reduce performance levels using techniques to protect battery life. In addition, conventional notebook computers have a small, dense system configuration that limits the ability to safely dissipate heat generated by computer operation. Therefore, conventional notebook computers generally use power of less than the desktop counterparts, which adversely affects performance.

Most power saving techniques have been introduced to overcome and weaken the limitations caused by heat and battery power limitations. The operating frequency (clock frequency) of the processor and its operating voltage determine the power consumption of the processor. Since power consumption and thus heat generation are very proportional to the operating frequency of the processor, reducing the frequency of the processor below the desktop performance level has been a common way to keep within notebook computer power limitations.

A general power regulation technique called "throttling" prevents the processor from overheating by stopping temporary processor operations due to stopping the processor clocks. Throttling is an industry standard method of reducing processor power consumption by reducing the effective frequency of processor operation to adjust the power of processor operation and correspondingly using a clock control signal (e.g., the STPCLK # input of the processor). . When a temperature sensor placed on or near the processor is needed, a throttling step is initiated. Throttling continuously stops and starts processor operation according to a predetermined power, which is a period of several milliseconds. The reduction in the effective speed of the processor reduces power dissipation and reduces the temperature of the processor.

Applications such as word processors leave the processor idle for a long time. As a result, typical processor power consumption when operating word processing applications may be 30-50% below the maximum value. This idle state time can be used by the computer system to achieve additional power savings by causing the processor to sleep temporarily.

For example, in a word processing application, the processor performs a fast task after each character is hit, with the operation stopped until the next key strike. In addition, peripheral devices are turned off to achieve mobile power savings. For example, the notebook's hard drive is suspended after a period of inactivity until it is needed again. If the system detects another period of inactivity, for example a few minutes, the display is off. This technique is useful for conserving battery power and reducing the amount of heat that needs to be dissipated in the processor. It is also common to use cooling fans to increase the amount of heat removed from the system, to lower the processor temperature and to prevent damage to the system.

A typical notebook computer with power regulation activity and operation from a battery consumes about 15 to 20 watts. The processor portion in the power consumption is generally 8 to 12 watts. The remaining power consumption relates to the display, hard drive, memory subsystem, graphics controller and other peripherals. With a 40-50 watt-hour battery pack, the notebook will run for 2.5-3.5 hours. In contrast, without the power and thermal limitations of the notebook processor, a typical desktop processor consumes 20-30 watts.

However, when the notebook computer is connected to AC-line power, a large amount of system power can be used and additional cooling capacity can be used to remove more heat from the processor. This allows the processor to operate at a performance level approaching the performance level of a desktop processor. In this case, even though all power regulation features are not available, the entire notebook system must remain fully operational. Overall notebook power consumption and dissipation will increase by about 20 to 30 watts.

Proper monitoring and control of the processor's operating parameters is important in optimizing the notebook's performance and battery life. Power regulation in earlier personal computer systems is generally implemented through the appropriate use of a micro-controller and / or the system management interrupt (SMI). Current x86-based computer systems use an industry-supported power management method that is initiated by the Advanced Configuration and Power Interface Specification (ACPI) by Intel, Microsoft, and Toshiba on November 19, 1998. The ACPI is an operating system (OS) regulated power management method that uses features provided in Windows 9x and Windows NT or other compatible operating systems. The ACPI defines a standard interrupt (system regulated interrupt or SCI) that handles all ACPI events. System management interrupts are generated by devices that inform the OS about system events.

As part of this power management method, the ACPI specifies sleep and suspend states. The sleep state temporarily shuts down the processor and the operation can be stored for several milliseconds. The notebook enters the sleep state when an internal active watcher indicates that no processing occurs. When a keystroke is entered, the processor restarts when the mouse moves or data is received via the modem.

The pause state can cause several subsystems (eg, a display or hard drive) to stop and save a few seconds of operation. The pause state allows the current context of the system (sufficient for the computer to resume processing of the currently launched application) to memory (pause to RAM) or to hard drive (pause to disk) and power down peripherals. To the

ACPI defines the system's standard power state as well as the power state of individual components. The ACPI also defines standard methods for entering systems and devices into different power modes, and has features that enable the reporting of events, the monitoring and regulation of system temperatures, and the battery conditioning. ACPI power management includes a number of system power states for notebook PC operation. The Gx state represents the overall operating state of the system. The Cx processor state, the Dx device state, and the Sx sleep state define the state and sleep state of the system, such as pause-to-RAM and pause-to-disk. The four total Gx states are shown in FIG. 1A.

When the computer is operating in the G0 state, the CPU may have four computing states shown in FIG. 1B. On some platforms, it is not necessary to support all CPU states. For example, C1 and C2 for some systems provide latency for power dissipation and recovery. Thus, the designer will choose to implement only one of these states. Also, different systems will implement specific CPU states differently. Unlike the sleep state, when the power of the various parts of the computer system is lowered, all systems remain powered up in computational states.

When the computer is in a G1 state (sleep), the system will be in one of four sleep states shown in FIG. 1C. Unlike the Cx state, some sleep states do not present significantly different behavior for a given design. Thus, it is reasonable not to implement one or more states in a particular system.

As shown, the ACPI environment provides a number of mechanisms for handling heat and power dissipation. However, designs for notebook performance that approximate the performance of desktop computers require the processor to run faster and dissipate more heat. However, it would be desirable if the notebook suitably adapted to this environment to provide the appropriate level of performance given in the operating environment. When ACPI and current power management technologies provide some degree of supervisory control based on the notebook computer's operating environment, there is a need to provide advanced power management technologies that respond more efficiently to the environment in which the notebook computer is used. . It is also desirable to dynamically adapt to the needs of various environments without significantly impacting the user.

The present invention relates to portable computers and their associated performance and heat dissipation.

1A is a table showing four total Gx states.

1B is a table showing four computation states.

1C is a table showing various sleep states.

2 illustrates a state machine implementing various modes of operation that allow a processor to dynamically adapt to its environment.

3A summarizes the various modes of operation shown in FIG. 2.

3B provides example performance parameters for various modes of operation.

4 is a graph showing the voltage, frequency and power correlation.

5 is a block diagram of a high unit of a computer system according to an embodiment of the present invention.

6 illustrates one embodiment of a clock control circuit in a CPU.

7 illustrates operation of controlling voltage and frequency in accordance with one embodiment of the present invention.

8 illustrates the use of power on suspend CPU context lost (POSCCL) in one embodiment of the invention.

9A is a timing chart illustrating POSCCL pause and its corresponding resume operation.

9B is a table showing the signals shown in FIG. 9A.

10 illustrates the use of a programmable logic device to validate a driving mode change.

11 illustrates an implementation of the logic device of FIG. 10.

12 is a timing diagram illustrating operation of the logic device of FIG.

FIG. 13 illustrates a driving mode control register used in one south bridge implementation to validate a driving mode change.

14 is a high-level schematic diagram of a south bridge implementation providing jumper inputs and register inputs for voltage and frequency control.

15 is a flow chart of implementing a driving mode change in a south bridge integrated circuit.

16 illustrates an exemplary docking station for use in a notebook computer incorporating the various modes of operation described above.

The use of the same reference numerals in different drawings indicates similar or identical components.

Thus, a notebook or similar computing device may use external power sources (AC adapters, auto adapters or other external power sources) to select performance criteria during battery operation, attachment and / or activation of additional cooling devices, Monitor system environments such as user definable profiles. When a change is caused to any of these factors, the system level software imparts appropriate operating parameters or "run states" for the processor of the computing device.

Each operating state has different limitations on available power and power dissipation, and the situation changes while the notebook is in use. Ideally, in each operating state, the processor makes full use of the available power and power dissipation ceiling. To change the operating state, the system changes the core clock frequency and core voltage of the processor. Since the processor frequency determines the minimum required voltage for operation, the voltage and frequency of operation for the processor core are simultaneously changed. As the core frequency changes, so does the core voltage.

In one embodiment, a method of controlling power consumption of an integrated circuit in an electronic system is provided. The method includes operating the integrated circuit at a first voltage and a first frequency. When the system detects a change in at least one of a number of operational features in the electronic system, in response to detecting the change, the system stops clock operation on at least a substantial portion of the integrated circuit. . Updated frequency control information is provided to the clock control logic in response to the detected change, and updated voltage control information is provided to the voltage control circuit in response to the change. Once the updated information is provided, the system is configured to operate the clocks to operate the integrated circuit at a second clock frequency corresponding to the updated frequency control information and at a second voltage corresponding to the updated voltage control information. Restart

In another embodiment, a computer system having an integrated circuit having a first logic portion coupled to receive a first clock and a first voltage. The programmable voltage regulating circuit provides a variable voltage level for the first voltage in accordance with the voltage control signals provided to the voltage regulating circuit. The clock control circuit generates a first clock at a frequency determined according to the frequency control signal. Control circuitry receives an indication of a change in a number of operating characteristics in the computer system. The control circuit responds to a change in one of the operating characteristics by providing updated voltage control signals and frequency control signals indicative of a new voltage value for the first voltage and a new frequency for the first clock. The new voltage value and new frequency correspond to the detected change in the operating characteristics.

Notebook computers or other portable computing devices in accordance with one embodiment of the present invention allow the operation of the notebook computer and its processor to dynamically adapt to changes in its environment to provide improved performance and battery life. To determine these changes, the notebook computer can be configured to remove applications or external power sources (AC adapter, auto adapter or other external power source), changes in thermal environment (secondary cooling devices built into the AC adapter, cooling capability). Or attaching port replicators, docking stations or other attachable devices with cooling capabilities in a notebook that can be used due to the availability of external power, user definable profiles in battery operation (eg, Monitor changes such as performance or maximizing battery life).

When a change is detected in any of these or other parameters, the notebook computer adapts to the change by entering an appropriate mode of operation that sets the operating frequency, operating voltage, power consumption and power dissipation capabilities of the processor. This can be accomplished by generating an interrupt that causes level software to run that imposes appropriate operating parameters for the various operating modes of the computing device when parameter changes are detected. Preferably, the notebook computer changes dynamically appropriately without requiring the user to leave the applications or system software.

The various operating modes reflect different environments in which the notebook must operate. For example, in some circumstances, battery life is more important than performance when operating on battery power. However, when playing video clips, performance will probably be more important. When connected to an AC adapter or auto-adapter, battery life is not an important issue. Ideally, in each mode of operation the processor takes full advantage of the available power and power dissipation peaks.

CPU heat and power regulation is improved by changing the CPU voltage in addition to changing the clock frequency. Each operating mode maps processor frequency and voltage of operating parameters to performance requirements, dynamic changes in power consumption constraints and power dissipation constraints to provide the user with improved performance and battery life. Since the processor frequency determines the minimum required voltage for operation, the operating voltage and frequency for the processor core are simultaneously changed. Thus, reducing the voltage with frequency is a very efficient way to reduce the power consumption of the processor of the system when the environment is powered or thermally limited or when power conservation is required. Battery life is improved by making it at least possible for the voltage provided to the CPU to verify proper operation at the target frequency of operation. In practice, this enables the lowest possible CPU power consumption at a given operating frequency. The system can optimize power and frequency within specified limits. In addition, thermal regulation is optimized for a given frequency of CPU operation.

Changes in the core clock frequency of the processor have a nearly linear effect on the power dissipated by the processor. Thus, a 20% reduction in clock frequency reduces 20% of the power dissipated by the processor. The range of change is important, because the ratio of the lowest frequency to the highest frequency is usually greater than 2: 1. As a result, the power of the processor will be changed by a similar ratio. Changes in the core voltage of the processor have a nearly square law effect. In other words, the potential power savings are proportional to the square of the percentage of voltage reduction. Although the range of voltage change is generally less than 50%, the square law effect causes a significant change in the power of the processor if the core voltage of the processor is reduced. High performance processors receive multiple voltages including a voltage for the I / O region and a voltage for the core logic region, the core logic voltage being high enough to cause the I / O region to drive signals out of the chip. As required, it should be borne in mind that it is lower than the voltage required in the I / O region.

In FIG. 2, a state machine is shown that implements various modes of operation that allow the processor to dynamically adapt to its environment. Since it is desirable for a notebook to operate with the performance of a desktop computer, operating mode 3 (11) is docked to a docking station that provides auxiliary power and auxiliary cooling, for example, maximum system performance (clock frequency and heat). Divergence). This would require the docking station to include a fine cooling system for allowing air to pass through the processor heatsink or for conducting heat from a processor with, for example, a heat pipe or heat plate. The heat pipe is used to conduct heat to a docking station where heat sinks and fans are used to dissipate the heat.

If the system is not docked, the system may enter operation mode 1 (13) or operation mode 0 (15). When operating from the battery (driving mode 0 or 1), the user can choose between power conservation and performance. Run mode 1 is a performance mode that is as high as run mode 2 and maintains processor speed requiring active cooling. This high level of performance reduces battery life as a result of increased power dissipation by the processor and also by the requirement to drive cooling devices such as fans to help heat dissipation. In the performance / battery operating mode, performance is limited by the limitations of active cooling.

In battery mode, battery life is also more important than performance. In maximum battery life mode, operating mode 0, the limitations of passive cooling provide the highest performance limits. The maximum limit will be higher than actual performance due to the desire to extend battery life by reducing power consumption by the processor below the performance limit. The ability to operate without active cooling in battery save mode (operation mode 0) relies on low power dissipation in a stop clock / Grant state where the processor core clocks stop. Otherwise power will have to be consumed during active cooling.

In addition, at least one mode of operation will be provided between the two extremes of operation mode 1 and operation mode 0. The " between two extremes " mode provides active cooling rather than a lower performance goal that results in active cooling that needs to be switched less frequently. This mode of operation has the advantage of lower power consumption and less frequent consumption of power by the cooling fan. Additional battery modes are provided with greater granularity between the performance highlighted in drive mode 0 and the battery life highlighted in drive mode 0. In one embodiment, the user will specify various battery operating modes via a control panel applet similar to the method of selecting a time delay prior to the display or hard drive sleep.

Run mode 2 17 provides external power (eg from an AC adapter), while the notebook computer is not coupled. Operation mode 2 provides maximum performance limited by thermal considerations. The lack of auxiliary cooling limits the performance of Run Mode 2 to less than the Run Mode 1 performance. However, if the notebook is equipped with an active cooling device, the notebook can be used continuously in driving mode 2 without concern for power consumption. This allows the CPU to operate at a higher frequency than run mode one.

Each mode of operation is intended to provide maximum performance within the limits of available cooling mechanisms and battery life requirements. 3A summarizes the various modes of operation with total dissipated power (TDP). Various environments are possible to facilitate or warn the user of the operation. For example, a DVD player can check the operation mode when it is started. ACPI manages tables representing performance levels. If operating in driving mode 0 (battery saving mode), a warning message may be generated indicating that the full frame rate of recording playback is not possible until the user selects one of the other operating modes.

The computer system must provide a small waiting period between modes of operation. The user must wait for example a waiting period of up to 1 second, and preferably the waiting period should not be recognized by the user.

3B provides a table of exemplary performance parameters for various modes of operation. For example, in run mode 0, the CPU voltage is 1.6 volts and the CPU frequency is 200 MHz. In contrast, operation mode 3 provides 400 MHz operation at 2.2 volts.

FIG. 4 shows a graph showing a comparison of power reduction for a notebook that reduces the average frequency of operation through "throttling" described above. The left vertical axis represents voltage. The right vertical axis represents watts. Line 41 represents the voltage required as a function of frequency for a typical notebook processor. Midline 43 represents power as a function of frequency and represents the power savings available from frequency reduction. As shown, power saving is generally linear. It should be appreciated that power savings from frequency reduction are equivalent to power savings provided from throttling. Line 45 shows power as a function of voltage and frequency and shows the power savings available from the reduction of both voltage and frequency. It should be appreciated that throttling is used in combination with a reduction in both voltage and frequency to further reduce the effective speed or power dissipation of the processor. In a typical notebook system, additional power savings at 200 MHz are equivalent to at least 45 minutes of battery life.

Operational mode changes are initiated by software, and once initiated, the state machine performs its operations while the processor is controlled by state machine logic that is in a sleep state. The operating mode logic may be implemented with individual logic devices conferred to standard south bridge power regulation or other location appropriate to the computer system or may be combined with power regulation features of a south bridge integrated circuit. The software required to change the mode of operation can be initiated by SMI or by SCI features combined in a standard south bridge. The required software can use existing routines to put the processor into sleep or pause mode and then resume operations.

In one embodiment, the processor changes the internal bus-multiplier state and manages or restores the state of the internal registers through chipset control. This feature enables multiple modes of frequency operation without powering down the system or without manually reconfiguring the bus frequency (BF) to be initiated.

Because sleep and pause states require the processor to be stopped, it is impossible for the system software to control all sleep, pause, and restore operations. To overcome this problem, a state machine is provided within the input / output integrated circuit (known as the south bridge) that controls the sleep and pause operations and the final stages of the resume operation. Many notebook computers use state machines within the South Bridge integrated circuit to provide common power regulation features. One such integrated circuit is the 82371 AB PCI-TO-ISA / IDE XCELERATOR (PIIX4) from Intel Corporation. The power regulation features included therein extend battery life by reducing power consumption and safely operate the processor by controlling heat generation and dissipation. Others use separate microcontrollers for work, and most notebook PCs rely on the South Bridge to provide hardware for heat and power regulation. The south bridge is one chip of a chipset that includes a north bridge. The north bridge provides a memory controller function as well as a bridge function between a peripheral component interconnect (PCI) bus and a host bus connected to the processor. The south bridge is also connected to the PCI bus (which acts as the primary input / output bus in the computer system) and providing an interface to (or integrated into) the legacy devices on the ISA bus; It provides a variety of functions, including providing an interface to various other input / output busses (e.g., universal serial bus (USB)) and providing various power conditioning related functions. South Bridge chipsets from various manufacturers commonly use the registers, timers and state machines used in the Intel PIIX4 South Bridge. PIIX4 compatibility at the current South Bridge can be extended to support the disclosed mobile operating modes.

In the example embodiment shown in FIG. 5, voltage regulator 501 supplies core voltage 502 (CPU) 503 (designated as V _cc2 in an x86 processor environment). In the illustrated embodiment, the south bridge 505 controls the voltage level supplied to the CPU 503 by supplying voltage control signals VID [4: 0] to the voltage regulator 501. AMD-K6 to control the processor frequency In a typical implementation such as used in a processor, three bus frequency input pins BF [2: 0] are used to determine the internal operating frequency of the processor. The south bridge 505 controls the operating frequency of the CPU 503 by supplying BF (bus frequency) to the CPU. The bus clock signal 506 supplied from the clock generator 507 to the CPU 503 is internally multiplied by the ratio determined by the CPU by the value of the three bus frequency pins. The multiplication factor is, in one embodiment, from 2.5 times the bus clock to 6.0 times the bus clock. Other multiplication factors are possible depending on the particular system implementation.

6 illustrates one embodiment of a clock control circuit in a CPU. The frequency divider circuit 61 receives the BF pins, which are sampled during the assertion of the processor reset signal CPURST. The sampled values are applied to a phase locked loop (PLL) clock multiplier / synthesizer circuit for a time sufficient for the PLL to stabilize. The values of the BF pins are latched in the frequency divider 61 at the falling edge of the CPURST signal. The reset pulse is long enough to confirm that the clock multiplier circuit is stabilized. The bus clock 63 is supplied to a phase (frequency) detector 64 that supplies a control voltage 65 to a voltage controlled oscillator (VCO) 67. The VCO supplies a clock with a frequency determined by a bus clock frequency multiplied by a value determined from the BF pins to the core logic of the CPU. Gate logic 68 is used to escape the CPU core clocks when the appropriate gate signal 69 is asserted to stop the core clocks.

The additional BF pins are larger in clock multiplier values to confirm that battery life mode (driving mode 0) is fully supported, i.e., that the processor is operating sufficiently slow, such as a faster processor is provided. Used to provide a range.

5, the south bridge 505 provides an enable signal 509 to the clock generator 507 to cut off the clock supplied to the CPU 505 to minimize the power consumed by the CPU. Thus, south bridge 505 programs the voltage regulator, controls the clock generator, manages the power for throttling of the processor via the STPCLK # signal 510 and controls the BF-pins by controlling the BF-pins. Control the multiplier. The south bridge also creates a special protocol required to change the clock multiplier within the processor and to change the core voltage to manage the conversion between the operating modes. If no direct operating system (OS) support for changing the operating mode is provided, the transition between the operating modes is preferably transparent to the extent possible for the operating system and the user.

A way in which transparency can be achieved is a system management interrupt (SMI) used when a change in docking or AC / battery state is detected. The interrupt is not used by the ACPI method and is transparent to the operating system. When a change is detected, a short wait period of up to about 1 second for the change can be tolerated and a shorter wait period is preferred. It should be appreciated that operating system support is provided in some embodiments, and that transparency is not an advantage.

As shown in FIG. 5, jumper 511 provides a default state to the clock multiplier and voltage regulator at startup. The south bridge receives the jumper signals at eight jumper input pins IBF [0: 2] and IV [0: 4]. The number of jumpers and jumper inputs varies depending on the particular design. The setting of jumpers 511 with resistors 513 provides the default value to both the voltage regulator control pins voltage ID (VID) pins and the processor clock multiplier pins (BF pins). The default values are provided to the South Bridge 505. When powered, the south bridge provides default values of the VID pins and BF pins to the voltage regulator and the CPU, respectively. However, for the conversion between the above-described operating modes, the south bridge 505 according to an embodiment of the present invention selects internal registers as a source for output signals provided to the voltage regulator and the CPU, not the jumper inputs described above. .

In the embodiment disclosed in FIG. 5, three output bits are used to control the clock frequency and five output bits are used for control of the CPU core voltage regulator. However, many other bits will be used depending on the particular clock frequency method and voltage regulator used. In addition, certain bits need not be dedicated as voltage or frequency control bits. Thus, if the south bridge provides 10 inputs for the jumpers and 10 outputs for clock and frequency control, some applications require only three frequency control pins and five voltage control pins, while Other applications would require four or five for each. Thus, the input bits and outputs are not dedicated as frequency or voltage control bits. Thus, if the voltage regulator can use seven control bits, seven control bits are used for voltage control and three are used for frequency control. This provides flexibility in implementation without the need to change the south bridge. In some implementations, the processor provides default static VID signals as shown at 514 that does not depend on jumper settings.

In order to change both the voltage and frequency of the processor, processor operations need to be stopped, i.e. the processor clocks need to be stopped, at least such clocks being registers and latches or other circuit nodes in the time sensing path. It may need to be supplied to storage components, such as this, causing unexpected situations. In current X86 architectures this is accomplished by first asserting the STPCLK # signal so that the CPU stops distributing its internal clock. Upon receipt of the STPCLK # signal, the CPU completes the current activity command and asserts a "Stop Grant" indication. Once the "stop accept" is received, the clocks are stopped at clock generator 507 using enable signal 509. Conventionally, the ACPI architecture provides a number of latency and sleep operations that are modified to implement latency processor operation in the context supported and required for the South Bridge.

7 is a flowchart illustrating an operation for controlling voltage and frequency according to an embodiment of the present invention. The processor uses a voltage regulator 501 to receive the appropriate voltage control signals VID [0: 4] and a frequency control circuit to receive the appropriate frequency control signals (e.g., BF signals) (70). Assume that we operate in normal operating mode at. The computer system detects a change in power source and operating characteristics such as thermal environment or user-selected operating parameters (step 71). In response to detecting the change, the system stops the processor in step 72 by stopping its clocks and determines a new frequency and corresponding voltage setting appropriate for the new mode of operation. This information is stored in the registers of the south bridge or in another suitable location of the computer system. The updated voltage and frequency control signals are supplied to the appropriate voltage and frequency control circuit at steps 73 and 74 and the processor resumes operation at step 75.

The resume operation is started from one of the last operations of the pause operation. One of the above steps in the restart operation considered in connection with FIG. 7 is for the restart operation of sending a frequency control signal update indication (e.g., reset (CPURST)) to the processor. The frequency control update or valid signal indicates to the processor that there is valid data on the BF pins that should be used for generation of the core clock. If a CPU reset is used for this purpose, the reset is only applied to the processor and not to those parts of the computer system that do not require a reset.

In one embodiment, the processor senses the values of the frequency control signals (on the BF pins) when the reset signal is asserted and latches these values on the falling edge of the reset (see FIG. 6). Also, a non-reset signal will be asserted to instruct the processor that a new frequency control signal value exists. If the reset signal is used to indicate that new frequency control (BF) signals are available, the processor will lose the context for reset assertion and, for example, the values in the processor registers will be lost. Thus, the processor context must be saved before applying the reset or it will not be possible to resume where the application was interrupted. Once the reset is complete, the processor context can be restored from where it is stored using a processor operating at a new frequency and voltage setting. It is desirable to minimize the waiting period for the restart operation, and therefore to restore the processor context as soon as possible.

Sleep and pause states require the processor to be stopped. Thus, it is impossible for the system software to directly control some adjustment operations. To overcome this problem, state machines in the South Bridge control the system to suspend processor operation and suspend other system devices. Once the system is in a sleep or pause state, the South Bridge monitors for a number of possible events to wake up the system. If an event occurs, another state machine arranges the system to resume operation. The same hardware and software used to provide the sleep and pause states can also be used to perform the conversion between the operating modes.

As previously disclosed, the STPCLK # (where # indicates that the signal is active low) input of the processor is often used to temporarily suspend operation and protect power. The processor enters a stop accept state with the use of the STPCLK # signal. In this state, the core clocks are stopped although the minimization logic that includes the clock multiplier logic is still active. The control register LVL2 in the south bridge is read to initiate the sequence used by the current south bridge chips to place the socket-7 processor in the stop accept state. The result is an STPCLK # asserting that the processor should stop processor clocks. The south bridge indicates that the processor deviates from its core clock by waiting for the processor to complete its current operation and apply the stop accept indication. The south bridge asserts the ZZ pin (selectively pausing the L2 SRAM). This is enabled by ZZ_EN in the CNTB register of the South Bridge.

When a weather event is detected, the South Bridge deasserts the ZZ pin (if this selection was enabled) and deasserts STPCLK #. Using this control sequence, which can save significant power while waiting for an event such as the next key strike, processor clocks can be stopped for changes in core frequency associated with changes in the modes of operation described above. This change in sequence asserts the SLP # signal causing portions of the compatible processor to enter a power down state.

More power can be saved by stopping the clock supplied to the processor clock multiplier circuit to remove a portion of the processor that is still active as previously described. The clocks at clock generator 507 will be stopped as part of the sequence to convert the operational modes described above. Initiating the sequence, at the PIIX4-compatible south bridge, the software reads the control register LVL3 in the south bridge and causes STPCLK # to assert in order to clock off the processor and put the processor in deep sleep. do. The south bridge waits for a stop acceptance. The ZZ pin is optionally asserted to pause the L2 SRAM. This is enabled by ZZ_EN in the CNTB register. At this time, SLP # is declared. SUS_STAT1 # is asserted to the north bridge to put system memory into auto-refresh mode. CPU_STP (enable 509 in FIG. 5) is asserted to disable the clock synthesizer (clock generator 507) output for the CPU bus clock.

When a weather event is detected, the South Bridge first unclaims CPU_STP to enable the CPU bus clock output of the clock synthesizer. The timer in the South Bridge (known in the industry as the "Burn Timer") counts so that the time for the CPU PLL is fixed. The value used by the timer is loaded from the CLK_LCK register set by the BIOS during the power-on self-test (POST) sequence of the system. Finally, the SUS_STAT1 #, SLP #, ZZ pin (if the selection was enabled) and STPCLK # are deasserted.

The sleep state machine may perform the more complex operations required to pause the system by setting SUS_EN (bit 13) and loading the appropriate value (bits [12:10] in the power regulation control register of the South Bridge). Can be. The values indicate the type of pause / resume operation required. Table 1 below describes the types of pause / resume operations available and the associated values in the power regulation control register in the south bridge. The resumption waiting period varies depending on the type of the pause operation. For example, a pause for a disk resume wait period is typically less than 30 seconds, a pause for RAM is about 1 second, and a power on pause with a managed context is about 20 ms. Context management significantly reduces the wait time on resume.

Bit [12:10] Pause form 000 Soft Off or Suspend to Disk (STD) 001 Suspend to RAM (STR) 010 Power on pause, context lost (POSCL) 011 Power On On Suspend, CPU Context Lost (POSCCL) 100 Power on pause, context hold (POS) 101 Action (clock throttling will be active) 110 Hold 111 Hold

As mentioned above, asserting a reset informing the processor of a change in the BF signal to cause the clock frequency associated with changes in operating modes causes the processor context to be lost. When the reset is used to latch new BF pin values as shown in Figure 8, one of the pause operations to restore the CPU context is used.

8 illustrates the use of POSCCL in one embodiment of the present invention once a new operating environment is detected, i.e., a new mode of operation is required, and a new voltage and frequency setting is loaded into the appropriate register in step 801. FIG. It is a flowchart showing. The registers will be in the south bridge or computer system. Once these registers are loaded, the processor context is saved and the resume operation is set in step 803 by specifying a restart address. Storing the processor context includes flushing the internal cache of the processor and storing the state of the process in DRAM. Setting the jump requires setting a start vector address (actual mode) and setting the required flag byte, so that the BIOS immediately goes to the restore routine after CPU reset instead of rebooting the system. Will diverge. The X86 processors start running in the address range F000: FFF0 after reset. In a conventional x86 personal computer system, the BIOS ROM is in the address range. The BIOS must examine the flag bytes in RAM and fork to execute special code, such as when the BIOS restores the processor context or performs a cold boot.

After the processor context has been stored, the software initiates a south bridge state machine that pauses the processor at step 805 by reading a register in the south bridge. The final operations of the pause state machine initiate a new mode of operation implemented as a state machine. The new operation mode logic updates the voltage and frequency control signals provided to the voltage regulator and frequency control logic in the CPU, respectively, with the new voltage and frequency control settings, and supplies a weather indication to initiate the resume state machine at step 809. . It should be appreciated that the voltage supplied to the core logic is changed while the core clocks are off, reducing the risk of adverse effects of the voltage change. Also, as described below, the core voltage is varied while the reset is supplied to the processor. Although the processor need not be reset when the core voltage changes, it is desirable to prohibit processor operation until the core voltage has stabilized to a new value. The resume state machine applies a reset signal to the processor such that the new frequency value is applied to the clock multiplier logic. After sufficient time to match the phase locked loop (PLL) of the processor, for example about 1 ms or less, the resume state releases the reset in step 813. The CPU then begins executing and jumps to the POSCCL resume routine where its address was previously set to restore the CPU context at step 815. The processor may resume processing at the terminated location without impacting the application on use at the time of operation mode change rather than at the time affecting the POSCCL.

9A is a timing diagram illustrating operation of the South Bridge in POSCCL pause and corresponding restart operation. The transition from the on state to the pause state is shown on the left side of Fig. 9A, and the transition from the pause state to the on state is shown on the right side of Fig. 9A. Once the processor enters sleep state in POSCCL, RTC alarm, SMB event, serial port, ring indicator, system's soft power button, external SMI (EXTSMI), system lid rise, full standby timer alarm, USB It may be awakened by an activity, such as an IRQ [1,3: 15], or Universal Purpose Input 1 (GPI1) assertion. In one embodiment described above, general purpose inputs to the South Bridge are used when initiating events that wake up the processor. The signals shown in FIG. 9A are shown in FIG. 9B. The various signals shown in FIG. 9B are provided as general purpose outputs (or will not be used in special notebook PC designs).

Programmable Logic Device Implementation

Prior to the detailed description of the various South Bridge implementations used in the system shown in FIG. 5, another method of providing a quick time to market solution will be disclosed. In the method, a PIIX4-compatible south bridge with a logic device such as a programmable logic device (PLD) supplies the signals required for the (BF-pins) frequency control inputs of the processor and requires various modes of operation. Reprogram the core voltage power supply as required. The programmable logic device may be a programmable array logic (PAL) device or a programmable logic array (PLA) or other suitable logic device.

In FIG. 10, the programmable logic device 101 receives values from jumpers 511 and sends eight output bits, five bits to the CPU core voltage regulator, three frequency control bits BF [2: 0]. The CPU 503 is provided. These bits control the processor frequency logic on the voltage regulator 501 and the CPU 503, respectively. The south bridge 103 also provides a number of control signals to the programmable logic device 101 and receives weather signals from the programmable logic device 101 as described above. The PLD shown in FIG. 10 enables the implementation of the above described operation mode conversions without requiring a design change to other system components.

If necessary, the bits supplied for voltage and frequency control are allocated in different ways by assigning more bits to frequency control and less bits to voltage control depending on the need of the voltage regulator and the desired frequency range of operation. Be aware that it can be. In practice, all the usable bits below may be used for voltage or frequency or both. For example, a typical processor such as the AMD-K6 processor requires only three bits for frequency setting. Programmable voltage regulators are available with four or five control bits. In many applications, the full range or accuracy of the voltage regulator is not required and some control inputs to the regulator remain high or low. Thus, the method provides flexibility by allowing a variable number of voltage and frequency control signals to be used based on the needs of a particular system.

In FIG. 11, one implementation of programmable logic device 101 is shown in more detail. In the implementation shown, there are 13 inputs and 9 outputs, and the design can be implemented with a standard programmable array logic (PAL) device. Signals derived from the south bridge are clocked by the real time clock (RTC) (32 kHz); Thus, high speed logic devices are unnecessary.

There are eight input flip-flops 1101 connected as a serial shift register that receives a shift signal 1102 and a data in signal 1104 from the south bridge 103. The south bridge 103 is one shift output (indicated by GPO-X) as a shift signal supplied to the PLD 101 and the other universal output as GPO-Y as the data in signal supplied to the PLD 101. Instructed). PLD 101 includes eight output flip-flops 1103 that receive input signals from select circuit 1105, such that one of the input flip-flops or the jumper settings IBF [0: 3] and IV [0: 3]). In a power on reset, the flip-flops remain reset until Power Okay (PWROK) 1107 is asserted. When PWROK 1107 is asserted, South Bridge 103 sends a reset to the process.

The default value of the voltage and frequency control signals indicated by the jumper setting must be resupplied to the frequency and voltage control circuits if a system reset is generated by pressing a reset button or by software or by another mechanism. It should be recognized. Thus, the state of the GPO bit used to derive data in 1104 should be defaulted to logic 0 if the bit is used as a select signal for select logic 1105 as shown in the disclosed embodiment. If data in 1104 is zero in the system reset, it is confirmed that the default values from the jumper settings are appropriately selected by selection logic 1105. In some implementations, very few bits of the PIIX4-compatible south bridge bits have this characteristic (eg, GPO [27: 28,30]), so the GPO-X and GPO-Y bits are such bits. It is selected from these. Through the use of one of these bits, it is confirmed that the start jumper settings can be sent to the voltage regulator and the BF-pins of the processor during a reset in the implementation shown. Other implementations will be apparent to those familiar with the prior art. Although additional GPO signal (s) from the south bridge can be used to supply the multiplexer select signal, the use of the data in signal 207 as multiplexer select reduces the number of GPO pins required.

When the system is initially turned on, the rising edge of the CPURST signal causes the default or starting voltage and frequency settings to be loaded into the output register 1103 to be supplied to the voltage regulator 501 and the CPU 503. Loading of the output registers will immediately set the voltage regulator to an initial value. The default frequency settings will also be output. CPURST causes the processor to load its BF-pin inputs and sets up an initial bus clock multiplier to generate the CPU core clock.

Once a request for a transition to a new mode of operation has been detected by the notebook system before a pause / resume sequence has changed the processor voltage and bus clock multiplier, the GPO bits on the south bridge can be used to retrieve new values. Used to load into input registers 1101. With respect to FIG. 12, when the shift signal 1102 is used to shift new voltage and frequency settings on the signal line 1104 that are data into the input register 1101, a setup for the conversion sequence occurs at 121. do. Once the setup is complete, the pause operation asserting STPCLK # and SLP # disclosed in FIG. 12 and storing the process context is performed.

As disclosed, the GPO bit 1104 used to input data into the shift registers adjusts the multiplexer 1105. Leaving the bit high during the pause / resume sequence adjusts the multiplexer to supply the outputs of the shift registers to the inputs of the output registers 1103 instead of the jumpers. The serial data is written to a logic device that writes to the appropriate GPIO ports.

Once the core voltage and frequency have been changed in the input register 1101, the south bridge is allowed to perform a POSCCL operation such that the south bridge supplies a signal indicating that the pause operation is complete or nearly complete. As shown in Figure 12, although other signals may also be used, the signal is the SLP # signal. The signal indicates the end point of the pause sequence and is supplied to the PLD 101 as a trigger (TG #) 1109. In this particular implementation, TG # is active low. PLD 101 generates an event that initiates operation, i.e., wakes up the processor by logically combining the trigger signal with a data input 1107 in gate 1111. This feeds the SLP # to South Bridge input GP11 # as the weather event (active low), and sets the new processor frequency multiplier because the South Bridge input GP11 # cycles the processor reset as previously disclosed. A useful standard POSCCL is detected as a weather event that causes operation to resume. Thus, as shown in FIG. 12, the end point of the temporary operation causes the weather event. Alternately, this results in the restart sequence shown in FIG. Once the restart sequence is complete, the GPO signal 1107 used as the data input goes low.

The assertion of CPURST during the restart sequence loads the values from the input registers 1101 into an output register 1103. Values in output registers 1103 feed the new frequency multiplier settings and the core voltage settings to the processor and voltage regulator, respectively. Thus, the new voltage settings are applied to the core logic of the processor when a CPU reset is asserted. The new frequency multiplier ratio BF-pin settings are sampled by the CPU on the rising edge of CPURST and latched to the processor on the falling edge of CPURST. Resuming the POSCCL allows time to resynchronize the processor (PLL).

The use of the PLD allows the unmodified South Bridge and the processor to be used in notebook systems with the ability to convert between modes of operation.

To keep the operating mode logic and software as simple as possible, the bus clock frequency should not vary between 66 MHz and 100 MHz during the change. This is because the BF settings are conventionally 1/2 x units (e.g., 2x, 2.5x, 3x, 3.5x, etc.) that limit the granularity of the processor clock frequency units. If greater completeness can be tolerated, these changes will be implemented. The frequency change of the bus clock affects the splitter ratios used to generate Peripheral Component Interconnect (PCI) and Accelerated Graphics Port (AGP) clocks. When changing the clock ratios, it will be necessary to place the memory to sleep or power down.

The implementation described above uses a variable voltage regulator supply, such as National Semiconductor's LM4130, and its output voltage can be controlled by chipset logic (including external devices). Preferably, the voltage regulator supplies at least four control bits, the output voltage allows a minimum range of 1.45 to 2.2 volts, and can be adjusted in units of 50 mV (or smaller). A wider range is desirable in some applications. The control pins of the voltage regulator should be for default operation at mode 0 (battery saving) voltage level upon power up. The chipset or other suitable logic will adjust the CPU voltage supply for the right mode of operation when the system is activated.

South Bridge Implementation

In order to provide an implementation that reduces the number of components required to change the operating modes as disclosed, the south bridge provides the logic required for changing between various operating modes rather than using an external logic device. can be changed. A high level implementation of such a system is disclosed in FIG. 5.

One method of implementing the south bridge is to integrate logic contained in the PLD into the south bridge. However, the logic can be simplified because the various signals required to interface the south bridge to the PLD can be eliminated. In addition, the use of a data input signal such as the multiplexer signal can be eliminated. In fact, the input registers are preferably loaded in parallel rather than serially, thus eliminating the need for a shift signal. Once it is determined that a new mode of operation is required, the resistor in the south bridge is supplied with the appropriate voltage and frequency settings.

In one implementation, the south bridge uses one of the combinations of bits [12:10] that are not currently used (eg, 110) to create a new sleep type in the power management control register (see Table 1 above). define. These bits are variously pointed out as a sleep form or a pause form. When the flip enable bit (or pause enable) is set to 1 and the sleep type bits are set to 110, the system causes a transition in the notebook operating modes.

Referring to Fig. 13, the driving mode control register 130 supplies the control information necessary for the conversion to the new driving mode. The two bit operating mode field 131 is a status field that identifies the current operating mode as high performance (00), AC power (01), battery performance (10) or battery saving mode (11). Additional modes of operation will require additional bits. The five bit core voltage field 132 defines the control bits for the new core voltage, and the four bit CPU clock frequency control bits 133 define the CPU core frequency. As mentioned above, clock control in the CPU will be implemented as a frequency multiplier of the bus clock. In one implementation, when the reset control bit is 1, the CPU is reset in an operation mode transition, and when the reset control bit is 0, the CPU is not reset. If a reset is supplied to the CPU to change the operating core frequency, storing the processor context prior to the reset and resetting the processor context after the reset signal is deasserted as disclosed for the POSCCL sequence. It is necessary to provide a restart operation to restore.

In another implementation, the processor is separated from a reset and has an input signal informing the processor when to latch the clock frequency control bits. In this case, the latch mode CMD bit 135 is asserted. In this implementation, the south bridge adds a frequency latch control signal (CMD) 515 to the CPU indicating when to latch the new frequency control bits in addition to the frequency control bits BF [0: 2]. (See FIG. 5). When the frequency latch control signal (CMD) 515 is asserted, BF pin settings are acquired upon assertion of the CMD 515 signal and latched at the falling edge of the CMD 515. Implementations for acquiring the BF pin settings based on the latch control signal CMD are of course possible. The use of the latch control signal (CMD) 515 provides a transition to a new mode of operation without having to provide a reset meaning that the processor context is not lost. Thus, the conversion takes significantly less time than the POSCCL pause and resume operation.

If the CPU reset signal is not used to mean a frequency change, once a need for a change in operating modes is detected, software loads the appropriate values in register 130 and stops the processor clocks. The clocks can be stopped at the processor using the STPCLK # signal previously described above. The new voltage and frequency control bits are output by the south bridge and the frequency control latch signal (CMD) 515 is asserted to indicate that updated frequency control signals are available. The CPU samples the frequency control bits (BF pins) upon assertion of the latch control signal (CMD) 515 and latches new values upon deassertion of the signal. Hardware within the south bridge maintains the latched control signal (CMD) 515 asserted for a time sufficient to allow the processor PLL to stabilize. Once the processor PLL is stabilized, the south bridge hardware deasserts the STPCLK # signal, and the processor resumes operation without the application or user recognizing the change in the operation mode. The time for the conversion is, for example, 100 ms or less.

If the reset is used to indicate a change in frequency, to avoid the need for a change to the processor, a sequence similar to the POSCCL shown in FIG. 9A will be used, and new control signals for voltage and frequency may be used. It is provided between the trailing portion of the power on suspend (POS) and the assertion of the reset in 91 in FIG. 9A.

The transition sequence from one mode of operation to another is initiated when an interrupt (eg, SCI) is generated due to an operation mode event. The event will occur because the notebook computer is connected to or disconnected from a docking station, port replicator or other device that is not capable of removing significant amounts of thermal energy from the notebook; Or other events when the AC power is applied or removed, or the battery operates low or causes a change in the operating mode.

The system management software programs the operation mode control register 130 with the new core voltage and new clock frequency control bits once the event is detected. The software sets the sleep type bits to 110 as well as the sleep enable bit. Reading special register LVL3 in South Bridge 505 initiates a hardware state machine that performs the POSCCL sequence. The use of the operation mode control register 130 will be employed in the South Bridge implementation or in the PLD implementation previously disclosed.

As another method of initiating the change in a driving mode sequence, for example by reading the LVL3 register in a non-ACPI environment, a write (or read) register 130 initiates the control logic to implement the driving mode change. It is used as a trigger. This trigger will be used when the operation mode change uses the latch control signal CMD or the reset signal. In this case, saving the processor context must be completed before writing the register if reset is used. If a latch control signal (CMD) 515 is used, the signal is strobe to indicate that the BIF signals are valid after the register 130 is written, for example for one PCI clock. Will be.

With respect to FIG. 5, the south bridge should recognize that it is still necessary to confirm that the default values from the jumper settings 511 are supplied to the CPU 503 and the voltage regulator 501. With reference to FIG. 14, in a manner similar to the PLD implementation, a multiplexer 1414 that selects between values in the control register 130 and jumper settings 511 in accordance with the select signal 142 supplied from control logic 144. ) Is provided. Control logic 144 implements the pause and resume sequences shown, for example, in Figure 9A, including the necessary pause and resume state machines. Multiplexer 141 outputs a value from jumper settings 511 that selects the default jumper settings in response to a reset (eg, power on reset or other hard or soft reset). To feed. Also, after the clocks are stopped and before the reset or CMD signal is supplied to the load at the rising edge of the reset of the CMD, either at the new frequency setting or assuming that the falling edge latches the new frequency setting. ) Is loaded.

With respect to FIG. 13, control bit 136 defines whether the clock generator 507 is disabled during the operation mode conversion. Using the STPCLK # from the South Bridge to disable the core cpu clocks, the clock generator 507 may disable the clocks supplied to the CPU (as in POSCCL). The clock frequency control bits are then updated and the clocks are returned back to the clock generator 507. It should be appreciated that clock generator 507 may be combined with other system components. It is desirable to have a clock generator whose outputs can be enabled by the GPO control bits of the south bridge. The clock generator allows a large number of PLL cells to support the various clock frequencies required in a special design, for example, the CPU at 100 MHz or 66 MHz, the serial devices at 24 KHz and 48 KHz, and the design supporting PCI devices at 33 MHz. do.

With respect to FIG. 15, the flowchart describes the overall operation of the south bridge incorporating hardware to cause driving mode changes. When an event is detected that causes an operation mode change, such as when an additional power source becomes available as previously disclosed, the software sets the required values for the register 130 in step 1501. At step 1503, a determination is made whether the reset control bit 134 is set in the register 130 or not. If so, it is required to store the processor context at step 1504. This determines the precise slip shape to be used by the south bridge. If the reset control bit 134 is not to be used, then the latch command bit 135 is set and step 1504 of storing the processor context will be omitted. Of course, only one bit needs to be used to indicate whether to use the reset or latch command signal. If access to the register 130 is used as a trigger to initiate a change in operating mode, the context needs to be stored prior to this access. Once the processor context is stored in step 1504, or if the reset is not used, the state machine in the south bridge can take over following the steps affecting the operation mode change.

In step 1505, the software performs a read of the register LBL3 to initiate a state machine sequence that affects the operation mode change. In step 1507, the South Bridge asserts STPCLK #. The state machine or other suitable hardware and / or software waits for a stop accept special bus cycle to be received which is an indication from the processor that the processor has turned off its internal core clocks. It should be appreciated that the stop accept acknowledgment may be performed without monitoring of the CPU bus cycles by simply waiting for a predetermined time above the maximum time taken by the processor to reach the stop accept state.

In any case, once a stop accept is confirmed or assumed that the predetermined time limit has been reached and a stop accept state exists in the processor, it is determined whether the stop clock bit 136 in the control register 130 has been set. If the bit is set, then at step 1513, the clock output from the clock generator 507 to the CPU is turned off using the stop clock line (enable 509). At step 1515, new voltage and frequency control settings are assigned to the voltage regulator and the BF pins, respectively. In step 1517, it is determined whether the stop clock bit (enable 509) has been asserted. If so, then at step 1519, clock generator 507 is enabled to output the clock to the CPU and to provide sufficient time for the PLL to stabilize. In step 1521, it is determined whether a reset is used to latch into the updated frequency control values. If so, then at step 1523, a CPU reset is strobe to latch the new frequency control bits. If the reset is not used, the CMD signal 515 is strobe by the south bridge to cause the processor to latch to the new frequency without reset. In step 1527, the STPCLK # signal is deasserted. This allows the CPU to resume supplying CPU core clocks. The processor resumes performing step 1529. If the context is lost by using a reset, it should be recognized that the context is then restored. This may be accomplished under software control rather than under hardware (eg state machine) control.

The use of register 130 provides an embodiment in which the use of a reset or latch control signal CMD may be selected, and the turning off of clocks out of the processor may be selected. In other embodiments, the south bridge (or other suitable integrated circuit) will not provide an option. In other words, in other embodiments, a reset is always used or the latch control command signal is always used. In addition, the change operation mode sequence always turns off clocks out of (or internally) the processor or leaves these clocks always on.

If the notebook PC uses 66 MHz and 100 MHz bus clock frequencies, a fraudulent clock generator can slew the CPU clock while multiple PLL cells are consistent with other system demand frequencies. The clock generator may slew the CPU frequency in a predetermined range while maintaining a rate of change in the CPU clock frequency within the jitter constraints of the CPU to prevent the clock multiplier circuitry in the processor from unlocking.

Thermal management

Adjusting the processor to operate frequencies and voltages optimizes power conservation and heat generation and dissipation according to the environment. In addition, thermal management capabilities are required. ACPI has two built-in methods, one passive and one active, for thermal management. The passive method relies on inhibiting the processor to generate less heat, while the active method uses a cooling device such as a fan to remove heat from the processor and system. Suitable heat detectors measure the temperature of the processor for passive and active methods. The thermal design is based on one or more thermal regions. In each zone, up to three thermal thresholds are defined:

There are two methods used today for thermal monitoring: full system monitoring and CPU-single monitoring. The full board monitoring method includes a means for measuring a total voltage (eg, CPU core, CPU I / O, 3.3V, 5V 12V, -12V-5V), fan rotation speed, temperature of the CPU and temperature of the board. To provide. Devices such as the National LM78 will be used for this system monitoring method. The CPU-single monitoring method may use the National LM75. The LM78 has an open collector output that is used to generate an interrupt when the temperature of the processor is above an acceptable limit or when the temperature changes by a predetermined amount. The System Management Bus (SMBus) is used to program the overtemperature and temperature hysteresis values in the device. The SM bus is a slow 2-bit serial bus that is used to communicate with surveillance devices such as heat detectors, chassis intrusion alert detectors and provides fan speed control. Conventional south bridges have an SMBus interface so that system software can communicate with (set up and control) these devices and read from these devices (can receive data from such devices). The National LM77 device has individual outputs that indicate overtemperature, or that the temperature is above or below a predetermined set point, and provides additional reliability. If ACPI fails to respond to the setpoint interrupt, an output indicating overtemperature may shut down the system through hardware.

ACPI manages temperature set-points compared to the processor temperature. If the temperature exceeds the set-point, an action is taken by the processor to reduce heat dissipation (passive method) or to extract heat from the system (active method). Necessary registers and interfaces are generally included in the PIIX4 south bridges. Many new South Bridges are compatible with PIIX4. This helps to reduce the effort to adapt ACPI BIOS and operating system modes for other company's chipsets.

ACPI manages set-points for processor thermal management. One is a failsafe set-point that will initiate blocking if the processor is too hot. Other set-points relate to the "active" and "passive" cooling methods of ACPI. Each method or both methods can be integrated into a notebook design incorporating the modes of operation described above.

In the active cooling mode, ACPI turns the cooling device on or off based on a temperature report generated by a sensor placed on the processor heat sink or by a sensor placed directly on the processor. When the temperature sensor detects a change in temperature (usually 5 degrees), the temperature sensor reports the new temperature to the thermal management of the ACPI. If the temperature is above the limit provided in the ACPI table, the cooling device is turned on. When the temperature sensor reports a decrease to a temperature where the temperature is above another table value, the cooling device is turned off.

These thresholds can be programmed. It should be appreciated that the software will be able to dynamically adjust the thresholds for optimal results. For example, if the active cooling threshold is exceeded, the system software runs the system fan at low speed and reprograms the active cooling threshold at a higher temperature. If the system temperature continues to rise, it will eventually exceed the new cooling threshold. In response, the fan speed will be increased and, if appropriate, the active cooling threshold can be set again at a higher point.

Generally, the cooling device is a small fan encased on or near the heat sink of the processor. Operating the fan circulates air from outside the case of the notebook PC to cool the processor more than can only be done by conduction and convection. The active cooling system can be made more precise. When coupled, an external fan at the port replicator or docking station can further circulate air. Other technologies used include refrigeration devices such as heat pipes and larger heat dissipation plates or Peltier coupling devices that have been used to cool desktop processors in the past.

The mobile system uses different active cooling devices and temperature set points in the ACPI tables for operation in each mode (AC / battery and combined / uncoupled). Because active devices consume power, it is recommended that these devices accept certain limited usage in run mode 0, battery life mode. Active cooling is a good method when the system is operating from an AC-wire adapter and an external power source such as a car adapter or an aircraft adapter.

In passive cooling mode, ACPI power management dynamically reduces or increases the "speed" of the processor needed to maintain the processor operating concentration at a safe level. Obviously, throttling down the processor and reducing its performance and allowing it to operate at some reduced speed, but today's processors can provide adequate performance for running applications such as word processing. This throttling method, used in most notebooks and directly supported by ACPI and PIIX4-compatible south bridges, allows the processor to selectively start and stop using the processor's STPCLK # (stop clock) input. Reduce the average processor speed.

Most throttling implementations use three bit granularities. The power ranges from 12.5% to 12.5% in 100% increments. (It should be appreciated that 0 is not an acceptable value.) When the temperature rises to the upper limit, throttling begins to the extent determined by the ACPI table value until the temperature falls below the lower limit.

The stopping and starting of the processor is not noticeable to the user. The reason is that the frequency at which the start / stop operation occurs is faster than humans can recognize. PIIX4-compatible chipsets use a real-time clock to drive a three-bit counter that determines the power.

Mobile systems operating in extended battery life mode (operation mode 0) should use clock throttling if necessary to reduce heat generation. Mobile systems must have sufficient manual cooling when operating in operating mode 0 at room temperature of 25 degrees C, which requires little throttling. In elevated temperature environments, the processor may be adjusted more often.

In order to achieve the desktop performance level when the notebook PC is combined, it requires additional thermal assistance, for example from a docking station (or other ways of providing additional cooling power and external power). The additional power dissipated in this way allows for higher CPU power allocation, allowing the processor to operate at desktop power and performance levels.

With respect to FIG. 16, a docking station implemented in a notebook is shown. 16 illustrates the use of a Peltier device 163 in the docking station 162 to cool the probe 165 that inserts into the back of the notebook computer 161 when the notebook system is coupled in the docking station 162. An example system is shown. The probe 165 contacts the heat sink of the processor and conducts heat. The probe 165 is cooled by the Peltier device 163 which requires several watts of power available from the AC operating power source of the docking station.

Other choices such as heat pipe technology are available. Heat pipes generally consist of tubes filled with refrigerant under water or other low pressure. When one end is heated by the processor, the refrigerant absorbs heat as it evaporates. The steam moves to the other end of the pipe, which is cooled by a heat sink. The vapor liquefies as it cools and returns to the starting point by capillary action through the wick. Heat pipes can be manufactured in many different ways and connected to large surfaces such as metal cases to dissipate heat. Thus, the notebook docking station method includes a fan, heat sink and heat pipe to conduct heat from the notebook computer when coupled to enable the increased performance desired in operating mode 3.

If heat conduction is used, it should be recognized that the user access portion rises above about 50 ° C. Areas without contact usually have to be uncomfortable to touch. It should be appreciated that when forced air from the docking station increases the cooling of the processor, it causes noise and dust problems.

The mechanical and electrical design supports the necessary sensing functions such that the notebook computer is connected and currently connected, when disconnected, when additional power and / or additional cooling is available, or user defined. It is possible to detect when the operating state changes. The notebook PC must also detect when AC power is applied first, when AC power is present, and when AC power is removed. The design includes the power and reset buttons, the capacity of the remaining battery when the main battery is present (i.e. smart battery), the state of charge of the battery, the remaining capacity of the battery when the additional battery is present in the selection bay, It should support detecting all standard notebook states such as battery charge state. It should be detected that the charge states include fast charge, trickle charge, battery failure (eg short circuit) and not charged. Detect when a pause button (or key combination) is pressed to pause or wake the system and when the cover is opened or closed (e.g. a choice to pause and wake or block the backlight). do.

The system includes at least two set points for processor case temperature and temperature “warning” (one set point for turning on a cooling device such as a fan when the temperature is near a safe upper limit for operation, and the temperature is One setpoint for immediate protective action should be detected when a critical upper limit is reached to prevent damage to the processor. If a fan is used for additional cooling, confirmation is provided that the fan is running (preferably the speed of the fan can be detected). The sensing capability described above is known in the art and is not disclosed herein.

As noted above, notebook computers dynamically adapt to their environment to provide improved power and thermal management and optimize their performance in the environment. It is to be understood that the description of the invention disclosed is for the purpose of description and is not intended to limit the scope of the invention disclosed below. For example, the present invention is directed to the type of mobile computers (designated as laptops or portable computers) indicated in notebooks, the disclosure being that computing, telephone / fax and networking features or modes of operation are available. It will be used in other utilizing computing devices such as personal digital assistants (PDAs), which are portable devices that combine communication devices and / or other small form factor operations to attest. Other variations and modifications of the disclosed embodiments are made on the basis of the disclosed details without departing from the scope and spirit of the invention as set forth in the claims below.

Claims (12)

A method of controlling power consumption of an integrated circuit in an electrical system, the method comprising: Operating the integrated circuit at a first voltage and a first frequency; Detecting a change in at least one of a plurality of operating characteristics in the electrical system; In response to detecting the change, stopping clock operation in at least a substantial portion of the integrated circuit; Supplying updated frequency control information to clock control logic in response to the change; Restarting the clocks to operate the integrated circuit at a second clock frequency corresponding to the updated frequency control information. The method of claim 1 wherein the method is: Supplying updated voltage control information to a voltage control circuit in response to the change; Operating the integrated circuit at a second voltage corresponding to the updated voltage control information. 3. The system of claim 2, wherein the clock control logic is placed on the integrated circuit, wherein at least some clock signals are active on the integrated circuit, wherein the clocks are stopped on a substantial portion of the integrated circuit. And stop at a substantial portion of the integrated circuit in accordance with a clock control signal supplied to the integrated circuit. 3. The method of claim 2, wherein the frequency control information is supplied to clock multiplier logic on the integrated circuit as clock multiplier information. 5. The method of any one of the preceding claims, wherein said integrated circuit is a processor, wherein said electrical system is a notebook computer system. 5. The method of any one of claims 1 to 4, wherein the operating characteristics include power source characteristics and a thermal environment. Method according to any of the preceding claims, wherein the operating characteristics comprise user-selected operating parameters. 7. The method of claim 6, wherein the power characteristic includes the presence of external power, wherein the thermal environment comprises the use of additional cooling. 5. The method of claim 1, further comprising storing a processor context prior to stopping the clocks and restoring the processor context before resuming the clocks. 6. Characterized in that the method for controlling power consumption. In a computer system, the system is: An integrated circuit comprising a first clock portion and a first logic portion adapted to receive a first voltage; A programmable voltage regulator circuit, wherein the voltage regulator circuit supplies a variable voltage level for a first voltage in accordance with voltage control signals supplied to the voltage regulator circuit; A clock control circuit adapted to generate a first clock at a frequency determined in accordance with the frequency control signals; Control circuitry adapted to receive an indication of a change in at least one of a plurality of operating characteristics in the computer system, the control circuitry having a new voltage value for a first voltage and a new frequency for a first clock. Responsive to a change in operating characteristics for supplying the voltage control signals and the frequency control signals, wherein the new voltage value and the new frequency correspond to a change in the operating characteristics. . 11. The method of claim 10, wherein the operating characteristics include the presence of external power and the availability of additional cooling, and include user-selected operating parameters that select between a battery performance mode and a battery saving mode for the computer system. Computer system. 11. The apparatus of claim 10, wherein the control circuit is placed on a second integrated circuit, the second integrated circuit is adapted to supply a clock stop signal to the integrated circuit, the clock stop signal in response to a change in operating characteristics. Asserted, the clock stop signal causes the first clock to stop on the integrated circuit, the clock stop signal is deasserted after signals representing a new voltage, and frequency control signals are sent to the voltage regulator and frequency control logic. A computer system, each of which is supplied.