KR20020049124A - Method for fabricating a thin film of a semiconductor device - Google Patents

Method for fabricating a thin film of a semiconductor device Download PDF

Info

Publication number
KR20020049124A
KR20020049124A KR1020000078218A KR20000078218A KR20020049124A KR 20020049124 A KR20020049124 A KR 20020049124A KR 1020000078218 A KR1020000078218 A KR 1020000078218A KR 20000078218 A KR20000078218 A KR 20000078218A KR 20020049124 A KR20020049124 A KR 20020049124A
Authority
KR
South Korea
Prior art keywords
reducing gas
ruthenium film
semiconductor device
thin film
ruthenium
Prior art date
Application number
KR1020000078218A
Other languages
Korean (ko)
Inventor
권일영
Original Assignee
박종섭
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 박종섭, 주식회사 하이닉스반도체 filed Critical 박종섭
Priority to KR1020000078218A priority Critical patent/KR20020049124A/en
Publication of KR20020049124A publication Critical patent/KR20020049124A/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/65Electrodes comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: A method for fabricating a thin film of a semiconductor device is provided to guarantee an excellent electrical characteristic by improving the purity of a ruthenium layer, and to increase capacitance by changing the shape of the surface of the ruthenium layer. CONSTITUTION: The ruthenium layer(14) is annealed in a reduction gas atmosphere so that the impurity inside the ruthenium layer is reduced and eliminated. The surface of the ruthenium layer reacts with the reduction gas and is embossed to form a capacitor in the annealing process.

Description

반도체 디바이스의 박막 제조 방법{Method for fabricating a thin film of a semiconductor device}Method for fabricating a thin film of a semiconductor device

본 발명은 반도체 디바이스의 박막 제조 방법에 관한 것으로서, 더욱 상세하게는 환원성 분위기에서 어닐링을 진행하여 루테늄(Ruthenium) 막질의 불순물을 제거하면서 캐패시터 용량을 확장하기 위한 표면처리가 이루어지도록 개선시킨 반도체 디바이스의 박막 제조 방법에 관한것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film of a semiconductor device, and more particularly, to an annealing in a reducing atmosphere, to remove ruthenium film impurities, and to improve the surface treatment for extending the capacitor capacity. It relates to a thin film manufacturing method.

통상, 반도체 소자는 많은 단위 공정을 거쳐서 제조되며, 이들 단위 공정들로써 산화, 식각, 이온주입, 평탄화공정 등이 예시될 수 있다.In general, semiconductor devices are manufactured through a number of unit processes, and examples of these unit processes may include oxidation, etching, ion implantation, planarization, and the like.

이 중 루테늄 막질을 증착하고, 이를 이용하여 캐패시터를 형성하는 공정이 포함된다.Among them, a process of depositing a ruthenium film and forming a capacitor using the same is included.

종래의 루테늄 막질을 증착한 후 캐패시터를 형성하는 공정에는 막질 특성을 개선시키기 위하여 질소 분위기에서 600℃의 온도에서 1분 정도 어닐링 공정이 진행된다.In the conventional process of depositing ruthenium film, a capacitor is formed, and annealing is performed for about 1 minute at a temperature of 600 ° C. in a nitrogen atmosphere in order to improve film quality.

그러나, 질소의 고유한 특성으로 인하여 증착 공정에서 루테늄 막질에 포함된 산소 성분을 환원시켜서 외부로 이탈시킬수 없다. 그러므로, 루테늄 박막이 고유하게 갖는 우수한 전기적 특성을 활용함에 있어서 이러한 환원되지 않은 산소 성분은 장애 요인이 되는 문제점이 있다.However, due to the inherent properties of nitrogen, the oxygen component contained in the ruthenium film cannot be reduced and escaped to the outside in the deposition process. Therefore, there is a problem that such an unreduced oxygen component is an obstacle in utilizing the excellent electrical properties inherent in the ruthenium thin film.

또한, 이러한 산소 성분은 후속되는 열공정에서 질화티타늄을 산화시켜서 소자 동작에 영향을 미친다. 즉 폴리 플러그의 배리어 메탈인 질화티타늄을 490℃ 이상의 환경에 노출시키는 열공정에서 산소 성분은 질화티타늄을 산화시킨다.This oxygen component also affects device operation by oxidizing titanium nitride in subsequent thermal processes. That is, the oxygen component oxidizes titanium nitride in a thermal process in which titanium nitride, which is a barrier metal of the poly plug, is exposed to an environment of 490 ° C or higher.

또한, 상술한 종래의 공정에서 루테늄의 표면 거칠기가 조절되기 어려워서 용이하게 캐패시터의 용량을 증가시키기 어려운 문제점이 있다.In addition, the surface roughness of ruthenium is difficult to be adjusted in the above-described conventional process, so that it is difficult to easily increase the capacity of the capacitor.

본 발명의 목적은 루테늄 막질에 포함된 산소 성분을 환원성 가스 분위기의 열공정에서 제거하여 소자의 특성을 개선시킴에 있다.An object of the present invention is to improve the characteristics of the device by removing the oxygen component contained in the ruthenium film in a thermal process of a reducing gas atmosphere.

본 발명의 다른 목적은 루테늄 막질의 표면을 환원성 가스 분위기의 열공정을 통하여 거칠게함으로써 캐패시터의 용량 증대를 꾀함에 있다.Another object of the present invention is to increase the capacity of the capacitor by roughening the surface of the ruthenium film through a thermal process in a reducing gas atmosphere.

도 1은 본 발명에 따른 반도체 디바이스의 박막 제조 방법에 의하여 공정 진행 전의 상태를 나타내는 단면도1 is a cross-sectional view showing a state before a process is progressed by a method for manufacturing a thin film of a semiconductor device according to the present invention.

도 2는 본 발명에 따른 반도체 디바이스의 박막 제조 방법에 의하여 공정 진행된 후의 상태를 나타내는 단면도2 is a cross-sectional view showing a state after a process is performed by a method for manufacturing a thin film of a semiconductor device according to the present invention.

본 발명에 따른 반도체 디바이스의 박막 제조 방법은 루테늄 막질을 환원성 가스 분위기에서 어닐링하여 상기 루테늄 막질 내부의 불순물을 환원시켜서 제거하여 이루어진다.In the method of manufacturing a thin film of a semiconductor device according to the present invention, the ruthenium film is annealed in a reducing gas atmosphere to reduce impurities in the ruthenium film.

또한, 상기 어닐링에서 캐패시터를 형성하기 위하여 상기 루테늄 막질의 표면이 상기 환원성 가스와 반응하여 엠보싱 처리가 이루어져서 캐패시턴스를 확보할 수 있다.In addition, in order to form a capacitor in the annealing, the surface of the ruthenium membrane may be reacted with the reducing gas to be embossed to secure a capacitance.

이하, 본 발명에 따른 반도체 디바이스의 제조 방법의 바람직한 실시예에 대하여 첨부도면을 참조하여 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, the preferred embodiment of the manufacturing method of the semiconductor device which concerns on this invention is described with reference to an accompanying drawing.

본 발명에 따른 실시예는 루테늄 막질(14)을 도 1과 같이 절연막(10) 사이에 형성된 컨택홀(12) 내부에 형성한 후 래피드 써멀 프로세스(rapid thermal process) 장비에서 열공정을 진행한다.According to the embodiment of the present invention, the ruthenium film 14 is formed in the contact hole 12 formed between the insulating films 10 as shown in FIG. 1, and then the thermal process is performed in a rapid thermal process equipment.

이때 공정 분위기는 환원성 가스가 주입되며, 공정 온도는 300℃ 내지 800℃ 정도로 설정되며, 공정 시간은 1분 내지 3분으로 설정된다. 그리고, 환원성 가스로는 NH3가 사용되며, 유량은 분당 1 리터 내지 분당 10 리터 정도로 설정되고, 압력은 1 torr 내지 760 torr 범위로 설정된다.At this time, the reducing atmosphere is injected into the process atmosphere, the process temperature is set to about 300 ℃ to 800 ℃, the process time is set to 1 minute to 3 minutes. NH3 is used as the reducing gas, the flow rate is set at about 1 liter per minute to about 10 liters per minute, and the pressure is set at a range of 1 torr to 760 torr.

이러한 공정 분위기에서 열 공정인 어닐링 공정이 진행되면, 환원성 가스 NH3에 의해서 루테늄 막질(14) 내부에 포함된 산소, 탄소, 및 수소 성분이 환원되어 제거된다. 그러므로, 루테늄 막질(14)은 고 순도 상태를 가져서 우수한 전기적 특성이 유지될 수 있다.When the annealing process, which is a thermal process, is performed in such a process atmosphere, oxygen, carbon, and hydrogen components contained in the ruthenium film quality 14 are reduced and removed by the reducing gas NH3. Therefore, the ruthenium film 14 has a high purity state and excellent electrical properties can be maintained.

또한, 열 공정이 진행됨에 따라서 루테늄 막질(14)의 표면은 Ru(NH3)x의 상태로 이동성이 향상된다.In addition, as the thermal process proceeds, the surface of the ruthenium film 14 is improved in the state of Ru (NH 3) x.

그러므로, 도 2와 같이 루테늄 막질(14)의 표면은 엠보싱 상태로 변형된다.Therefore, the surface of the ruthenium film 14 is deformed to the embossed state as shown in FIG.

이러한 루테늄 막질의 표면은 캐패시터를 형성함에 있어서 면적의 증가 효과를 얻어서 용량이 개선된다.The ruthenium film surface has an area effect in forming a capacitor, thereby improving capacity.

본 발명에 따른 실시예로써 환원성 가스로 NH3가 이용되었으나, 이에 국한되지 않고 H2와 같이 환원성을 갖는 가스가 제작자의 의도에 따라서 이용될 수 있다.As an exemplary embodiment according to the present invention, NH3 was used as the reducing gas. However, the present invention is not limited thereto, and a reducing gas such as H2 may be used according to the intention of the manufacturer.

또한, 루테늄 막질의 결정화 온도를 하향 조정하기 위하여 아르곤 가스나 질소 가스가 혼합되어 사용될 수 있다.In addition, argon gas or nitrogen gas may be mixed to adjust the crystallization temperature of the ruthenium film.

또한, 본 발명에 따라서 후속되는 열공정에서 폴리 플러그의 배리어 메탈인 질화막이 산화되는 것이 방지될 수 있다.Further, according to the present invention, oxidation of the nitride film which is the barrier metal of the poly plug in the subsequent thermal process can be prevented.

따라서, 본 발명에 의하면 루테늄 막질의 순도를 개선시킴으로써 우수한 전기적 특성을 확보할 수 있으며, 루테늄 막질의 표면의 형상 변형을 통하여 캐패시턴스를 향상시킬 수 있는 효과가 있다.Therefore, according to the present invention, it is possible to secure excellent electrical properties by improving the purity of the ruthenium film, and to improve the capacitance through the shape deformation of the surface of the ruthenium film.

또한, 후속되는 공정에서 열공정에서 폴리 플러그의 배리어 메탈인 질화티타늄이 산화되는 것이 방지되어 소자 특성을 개선시키는 효과가 있다.In addition, in the subsequent process, titanium nitride, which is a barrier metal of the poly plug, is prevented from being oxidized in a thermal process, thereby improving device characteristics.

Claims (8)

루테늄 막질을 환원성 가스 분위기에서 어닐링하여 상기 루테늄 막질 내부의 불순물을 환원시켜서 제거함을 특징으로 하는 반도체 디바이스의 박막 제조 방법.And ruthenium film quality is annealed in a reducing gas atmosphere to reduce and remove impurities in the ruthenium film quality. 제 1 항에 있어서,The method of claim 1, 상기 어닐링에서 캐패시터를 형성하기 위하여 상기 루테늄 막질의 표면이 상기 환원성 가스와 반응하여 엠보싱 처리함을 특징으로 하는 반도체 디바이스의 박막 제조 방법.And the surface of the ruthenium film is reacted with the reducing gas to emboss to form a capacitor in the annealing. 제 1 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 어닐링은 300℃ 내지 800℃의 온도, 1분 내지 3분의 시간, 분당 1리터 내지 분당 10리터의 유속, 저압의 환경에서 진행됨을 특징으로 하는 반도체 디바이스의 박막 제조 방법.The annealing is performed at a temperature of 300 ° C. to 800 ° C., a time of 1 minute to 3 minutes, a flow rate of 1 liter to 10 liters per minute, and a low pressure environment. 제 3 항에 있어서,The method of claim 3, wherein 상기 루테늄 막질의 결정화 온도를 조절하기 위하여 상기 환원성 가스에 질소 가스를 혼합함을 특징으로 하는 반도체 디바이스의 박막 제조 방법.And a nitrogen gas is mixed with the reducing gas to control the crystallization temperature of the ruthenium film. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 환원성 가스로 NH3를 이용함을 특징으로 하는 반도체 디바이스의 박막 제조 방법.The thin film manufacturing method of the semiconductor device characterized by using NH3 as said reducing gas. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 환원성 가스로 H2를 이용함을 특징으로 하는 반도체 디바이스의 박막 제조 방법.A method for manufacturing a thin film of a semiconductor device, characterized by using H2 as the reducing gas. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 루테늄 막질의 결정화 온도를 조절하기 위하여 상기 환원성 가스에 아르곤 가스를 혼합함을 특징으로 하는 반도체 디바이스의 박막 제조 방법.And argon gas is mixed with the reducing gas to control the crystallization temperature of the ruthenium film. 제 1 항 또는 제 2 항에 있어서,The method according to claim 1 or 2, 상기 루테늄 막질의 결정화 온도를 조절하기 위하여 상기 환원성 가스에 질소 가스를 혼합함을 특징으로 하는 반도체 디바이스의 박막 제조 방법.And a nitrogen gas is mixed with the reducing gas to control the crystallization temperature of the ruthenium film.
KR1020000078218A 2000-12-19 2000-12-19 Method for fabricating a thin film of a semiconductor device KR20020049124A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020000078218A KR20020049124A (en) 2000-12-19 2000-12-19 Method for fabricating a thin film of a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020000078218A KR20020049124A (en) 2000-12-19 2000-12-19 Method for fabricating a thin film of a semiconductor device

Publications (1)

Publication Number Publication Date
KR20020049124A true KR20020049124A (en) 2002-06-26

Family

ID=27683102

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020000078218A KR20020049124A (en) 2000-12-19 2000-12-19 Method for fabricating a thin film of a semiconductor device

Country Status (1)

Country Link
KR (1) KR20020049124A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011159691A2 (en) * 2010-06-18 2011-12-22 Applied Materials, Inc. Chemical vapor deposition of ruthenium films containing oxygen or carbon

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2011159691A2 (en) * 2010-06-18 2011-12-22 Applied Materials, Inc. Chemical vapor deposition of ruthenium films containing oxygen or carbon
WO2011159691A3 (en) * 2010-06-18 2012-06-14 Applied Materials, Inc. Chemical vapor deposition of ruthenium films containing oxygen or carbon

Similar Documents

Publication Publication Date Title
KR0165999B1 (en) Manufacture of semiconductor device
US7465617B2 (en) Method of fabricating a semiconductor device having a silicon oxide layer, a method of fabricating a semiconductor device having dual spacers, a method of forming a silicon oxide layer on a substrate, and a method of forming dual spacers on a conductive material layer
KR20020049124A (en) Method for fabricating a thin film of a semiconductor device
KR20020055884A (en) Method for manufacturing a capacitor in a semiconductor device
KR20040050519A (en) Method of manufacturing SRAM device
KR100504554B1 (en) method for manufacturing capacitor of semiconductor device
KR20000041429A (en) Method for fabricating capacitor which can prevent oxidation of bottom electrode
KR100565767B1 (en) Capacitor in semiconductor device and method for manufacturing the same
KR100434704B1 (en) Capacitor of semiconductor device and Method for fabricating the same
KR100379546B1 (en) Capacitor in semiconductor device and method of making the same
JP3685654B2 (en) Manufacturing method of DRAM capacitor dielectric film
KR100459945B1 (en) Method of manufacturing a semiconductor device
KR100233879B1 (en) Improved self-aligned silicide manufacturing method
KR100315038B1 (en) method of forming gate electrode for semiconductor device
KR100384844B1 (en) Method for fabricating semiconductor device
KR100417860B1 (en) mehtod for fabricating capacitor
KR20020050368A (en) Method of manufacturing a capacitor in a semiconductor device
KR20020048617A (en) Method for forming ta2o5 dielectric layer by plasma enhanced atomic layer deposition
KR100685637B1 (en) Method of manufacturing a capacitor in a semiconductor device
KR20020052846A (en) Method for fabricating semiconductor device
KR100418092B1 (en) Method of forming a capacitor in a semiconductor device
JP4106513B2 (en) Capacitor manufacturing method for semiconductor device
KR100359783B1 (en) Method for Fabricating Capacitor of Semiconductor Device
KR100673187B1 (en) Method of manufacturing a capacitor
KR20020017832A (en) Method for forming gate electrode in semiconductor device

Legal Events

Date Code Title Description
WITN Application deemed withdrawn, e.g. because no request for examination was filed or no examination fee was paid