KR20020045870A - Method for fabricating buried photodiode in CMOS image sensor - Google Patents

Method for fabricating buried photodiode in CMOS image sensor Download PDF

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KR20020045870A
KR20020045870A KR1020000075287A KR20000075287A KR20020045870A KR 20020045870 A KR20020045870 A KR 20020045870A KR 1020000075287 A KR1020000075287 A KR 1020000075287A KR 20000075287 A KR20000075287 A KR 20000075287A KR 20020045870 A KR20020045870 A KR 20020045870A
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buried photodiode
ion implantation
image sensor
cmos image
semiconductor substrate
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KR1020000075287A
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Korean (ko)
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이난이
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박종섭
주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14643—Photodiode arrays; MOS imagers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14609—Pixel-elements with integrated switching, control, storage or amplification elements
    • H01L27/1461—Pixel-elements with integrated switching, control, storage or amplification elements characterised by the photosensitive area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14603—Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Electromagnetism (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE: A method for fabricating a buried photodiode of a complementary metal oxide semiconductor(CMOS) image sensor is provided to remarkably improve the characteristic of the image sensor by increasing capacitance of the buried photodiode, and to increase the number of dies in a wafer by integrating a chip. CONSTITUTION: Impurity ions of the second conductivity type are implanted into a semiconductor substrate(201) of the first conductivity type by using the first ion implantation mask wherein plural portions of an active region of the buried photodiode are locally exposed. Impurity ions of the second conductivity type are implanted into the semiconductor substrate by using the second ion implantation mask wherein all of the active region of the buried photodiode is exposed. Impurity ions of the first conductivity type are implanted into a portion under the surface of the semiconductor substrate in the active region of the buried photodiode.

Description

씨모스이미지센서의 베리드포토다이오드 제조 방법{Method for fabricating buried photodiode in CMOS image sensor}Method for fabricating buried photodiode of CMOS image sensor {Method for fabricating buried photodiode in CMOS image sensor}

본 발명은 반도체소자 제조 기술에 관한 것으로, 더욱 상세하게는 베리드포토다이오드(buried photodiode)의 커패시턴스(capacitance)를 개선하기 위한 CMOS 이미지센서(image sensor) 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a CMOS image sensor for improving the capacitance of a buried photodiode and a method of manufacturing the same.

화상 인식 소자로 사용되는 CMOS 이미지센서의 단위화소 내부에는 그 구성 요소의 일부로써 베리드포토다이오드를 사용하고 있다. 베리드포토다이오드는 단위화소로 입사하는 빛을 전자로 바꾸어 주는 역할을 하기 때문에 센서의 특성을 좌우하는 주요 부분이다.A buried photodiode is used as part of a component pixel of a CMOS image sensor used as an image recognition device. The buried photodiode converts light incident on a unit pixel into electrons, which is a major part of the sensor's characteristics.

베리드포토다이오드는 실리콘기판위에 불순물 이온주입 공정을 통하여 형성시킨 불순물 접합층으로 구성된다. 이렇게 구성된 불순물 접합층에 바이어스를 가함으로써 공핍층을 형성시키고, 일정 시간 동안 입사하는 빛에 의해 실리콘기판에서 생성된 전자를 공핍층에 모으고 이를 회로적으로 읽어내는 방식을 통하여 화상 신호를 구현한다.The buried photodiode is composed of an impurity bonding layer formed on a silicon substrate through an impurity ion implantation process. A depletion layer is formed by applying a bias to the impurity bonding layer configured as described above, and an image signal is realized by collecting electrons generated in the silicon substrate in the depletion layer by the incident light for a predetermined time and reading them in a circuit.

따라서 베리드포토다이오드에 커패시턴스를 증가시켜야만 많은 양의 전자를 모을 수 있고 이에 의해 양호한 이미지신호를 얻을 수 있다.Therefore, the capacitance of the buried photodiode must be increased to collect a large amount of electrons, thereby obtaining a good image signal.

도 1으 종래기술에 따른 베리드포토다이오드 구조를 보여준다.Figure 1 shows a buried photodiode structure according to the prior art.

도 1을 참조하면, 베리드포토다이오드는 필드산화막(102)에 의해 둘러싸인 저농도 P형실리콘기판(101)의 액티브영역에 고에너지 저농도 불순물이온주입 및 저에너지 고농도 불순물 이온주입에 의해 각각 형성되는 N형불순물층(104)과 P형불순물층(106)에 의해 구성된다. 즉, P형불순물층(106)과 N형불순물층(104) 및 P형실리콘기판(101)에 의해 PNP 포토다이오드를 구성하게 된다. 도면부호 103은 베리드포토다이오드에 생성된 광전하 센싱노드로 전달하기 위한 트랜스퍼트랜지스터의 게이트전극이며, 105는 스페이서이다.Referring to FIG. 1, buried photodiodes are N-type formed by high energy low concentration impurity ion implantation and low energy high concentration impurity ion implantation, respectively, in the active region of the low concentration P-type silicon substrate 101 surrounded by the field oxide film 102. The impurity layer 104 and the P-type impurity layer 106 are formed. In other words, the P-type impurity layer 106, the N-type impurity layer 104, and the P-type silicon substrate 101 form a PNP photodiode. Reference numeral 103 denotes a gate electrode of a transfer transistor for transferring to a photocharge sensing node generated in the buried photodiode, and 105 denotes a spacer.

이러한, 베리드포토다이오드에 역바이어스를 인가하면 접합에서부터 공핍이 이루어지기 시작하여 최종적으로 N형불순물층(104)은 완전공핍되게 되고, 이 공핍층에 광전하를 모으게 된다.When the reverse bias is applied to the buried photodiode, depletion begins to occur from the junction, and finally, the N-type impurity layer 104 is completely depleted and collects photocharges in the depletion layer.

그런데, 현재 CMOS 이미지센서는 0.35㎛ 디자인 룰(design rule)로 축소(shrink)됨에 따라 베리드포토다이오드 영역 역시 축소되게 되고, 이에 의해 이미지신호 프로세싱을 위한 충분한 광전하를 얻을 수 없다는 문제가 발생하게 된다. 즉, 칩 사이즈가 적어지는 것에 대응하여 베리드포토다이오드의 커패시턴스를 확보하여야 하는 큰 문제점이 있게 된다.However, as the current CMOS image sensor is shrunk with a 0.35㎛ design rule, the buried photodiode region is also reduced, thereby causing a problem in that sufficient photocharge for image signal processing cannot be obtained. do. That is, there is a big problem that the capacitance of the buried photodiode must be secured in response to the chip size being reduced.

본 발명의 목적은 베리드포토다이오드의 커패시턴스 증대시키기 위한 CMOS 이미지센서의 베리드포토다이오드 제조방법을 제공하는 것이다.An object of the present invention is to provide a method for manufacturing a buried photodiode of a CMOS image sensor for increasing the capacitance of the buried photodiode.

도 1은 종래기술에 따라 제조된 베리드포토다이오드 구조를 보여주는 단면도,1 is a cross-sectional view showing a buried photodiode structure manufactured according to the prior art,

도 2a 내지 도 2c는 본 발명의 바람직한 실시예에 따른 베리드포토다이오드 제조 공정을 보여주는 단면도,2a to 2c are cross-sectional views showing a buried photodiode manufacturing process according to a preferred embodiment of the present invention,

도 3은 도 2a의 제1이온주입마스크 평면도.Figure 3 is a plan view of the first ion implantation mask of Figure 2a.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

201 : P형에피층기판 202 : 필드산화막201: P-type epilayer substrate 202: field oxide film

203 : 게이트전극 204 : 제1이온주입마스크203: gate electrode 204: first ion implantation mask

205 : 제2이온주입마스크 206 : N형불순물층205: Second ion implantation mask 206: N-type impurity layer

207 : 게이트 측벽 스페이서 208 : P형불순물층207 gate sidewall spacer 208 p-type impurity layer

상기 목적을 달성하기 위한 본 발명은, CMOS 이미지센서의 베리드포토다이오드 제조방법에 있어서, CMOS 이미지센서의 베리드포토다이오드 제조방법에 있어서, 베리드포토다이오드의 액티브영역이 국부적으로 다수군데 노출된 제1이온주입마스크를 사용하여 제1도전형의 반도체기판 내부에 제2도전형불순물을 제1이온주입하는 단계: 베리드포토다이오드의 액티브영역이 모두 노출된 제2이온주입마스크를 사용하여 상기 반도체기판 내부에 제2도전형불순물을 제2이온주입하는 단계: 및 베리드포토다이오드의 액티브영역의 상기 반도체기판 표면 아래에 제1도전형의 불순물을 이온주입하는 단계를 포함하여 이루어지며, 제1이온주입은 상기 제2이온주입보다 높은 에너지로 이루어짐을 특징으로 한다.The present invention for achieving the above object, in the buried photodiode manufacturing method of the CMOS image sensor, in the buried photodiode manufacturing method of the CMOS image sensor, the active region of the buried photodiode is locally exposed Injecting a first ion into a second conductive impurity into a first conductive semiconductor substrate using a first ion implantation mask using the second ion implantation mask in which all active regions of the buried photodiode are exposed. And implanting a second conductive impurity into a second ion into a semiconductor substrate; and implanting an impurity of a first conductive type under a surface of the semiconductor substrate in an active region of a buried photodiode. One ion implantation is characterized by consisting of a higher energy than the second ion implantation.

이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

도 2a 내지 도 2c는 본 발명의 바람직한 실시예에 따른 베리드포토다이오드 제조 공정을 보여준다.2a to 2c show a buried photodiode manufacturing process according to a preferred embodiment of the present invention.

먼저, 도 2a에 도시된 바와같이 P형실리콘기판(201)에 필드산화막(202)과 트랜스퍼트랜지스터의 게이트전극(203)을 형성한다.First, as shown in FIG. 2A, the field oxide film 202 and the gate electrode 203 of the transfer transistor are formed on the P-type silicon substrate 201.

그리고, 베리드포토다이오드의 액티브영역을 국부적으로 다수군데 노출시키는 제1이온주입마스크(204)를 형성하고, 이어서, 고에너지로 N형불순물을 제1이온주입한다. 도3에 제1이온주입마스크의 평면도가 도시되어 있다.Then, a first ion implantation mask 204 is formed to locally expose a large number of active regions of the buried photodiode, and then N-type impurities are first implanted with high energy. 3 is a plan view of the first ion implantation mask.

이어서, 도 2b에 도시된 바와 같이 베리드포토다이오드의 액티브영역을 모두 노출시키는 제2이온주입마스크(205)를 형성하고 N형불순물을 제2이온주입한다.Subsequently, as illustrated in FIG. 2B, a second ion implantation mask 205 exposing all active regions of the buried photodiode is formed and a second ion implantation is performed.

제1이온주입은 제2이온주입보다 높은 에너지로 실시하여 사영비정(Rp) 거리가 더 깊게 되도록 한다.The first ion implantation is performed at a higher energy than the second ion implantation so that the projection projection (Rp) distance is deeper.

이에 의해 N형불순물층(206)이 완성되는 바, 도면에 도시된 바와 같이 저면이 굴곡져 있어 P형실리콘기판(201)과의 접합 커패시턴스가 커지게 된다.As a result, the N-type impurity layer 206 is completed. As shown in the drawing, the bottom surface is bent to increase the bonding capacitance with the P-type silicon substrate 201.

이어서, 도 2c는 게이트전극(203) 측벽에 스페이서(207)을 형성하고, P형불순물 이온주입에 의해 P형불순물층(208)을 형성한다.2C, a spacer 207 is formed on the sidewall of the gate electrode 203, and a P-type impurity layer 208 is formed by implanting P-type impurity ions.

도 2c에서와 같이, 본 발명에 따른 베리드포토다이오드는 면적이 커져 커패시턴스가 증대되므로써, 광생성 및 저장 효율이 증대되게 된다.As shown in FIG. 2C, the buried photodiode according to the present invention has a larger area, thereby increasing capacitance, thereby increasing light generation and storage efficiency.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

본 발명은 베리드포토다이오드의 커패시턴스를 증대시켜 CMOS 이미지센서의 특성을 크게 개선하게 된다.The present invention increases the capacitance of the buried photodiode to greatly improve the characteristics of the CMOS image sensor.

또한 소자의 축소가 가능하여 칩의 고집적화를 앞당길 수 있고, 웨이퍼당 생산되는 다이 개수를 증가시킬 수 있다.In addition, the device can be scaled down, leading to higher integration of the chip and increasing the number of dies produced per wafer.

Claims (2)

CMOS 이미지센서의 베리드포토다이오드 제조방법에 있어서,In the buried photodiode manufacturing method of a CMOS image sensor, 베리드포토다이오드의 액티브영역이 국부적으로 다수군데 노출된 제1이온주입마스크를 사용하여 제1도전형의 반도체기판 내부에 제2도전형불순물을 제1이온주입하는 단계:Injecting a second conductive impurity into the first conductive semiconductor substrate using a first ion implantation mask in which the active region of the buried photodiode is locally exposed: 베리드포토다이오드의 액티브영역이 모두 노출된 제2이온주입마스크를 사용하여 상기 반도체기판 내부에 제2도전형불순물을 제2이온주입하는 단계: 및Injecting a second conductive impurity into a second ion into the semiconductor substrate using a second ion implantation mask in which all active regions of the buried photodiode are exposed; and 베리드포토다이오드의 액티브영역의 상기 반도체기판 표면 아래에 제1도전형의 불순물을 이온주입하는 단계Implanting impurities of a first conductivity type under the surface of the semiconductor substrate in an active region of a buried photodiode 를 포함하여 이루어진 CMOS 이미지센서 제조방법.CMOS image sensor manufacturing method comprising a. 제1항에 있어서,The method of claim 1, 상기 제1이온주입은 상기 제2이온주입보다 높은 에너지로 이루어짐을 특징으로 하는 CMOS 이미지센서 제조방법.And the first ion implantation is made of a higher energy than the second ion implantation.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100924045B1 (en) * 2007-12-27 2009-10-27 주식회사 동부하이텍 Image Sensor and Method for Manufacturing Thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100924045B1 (en) * 2007-12-27 2009-10-27 주식회사 동부하이텍 Image Sensor and Method for Manufacturing Thereof

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