KR20020045494A - METHOD OF FORMING SEMICONDUCTOR DEVICES HAVING SiOC LAYER - Google Patents

Abstract

PURPOSE: A method for forming a semiconductor device having low permittivity interlayer dielectric is provided to exactly form a micro pattern on a SiOC layer and to restrain a parasitic capacitance between interconnections or contact plugs by using the SiOC layer having a low dielectric constant. CONSTITUTION: A low permittivity carbon oxide silicon layer made of SiOC is formed on a substrate(100) by a CVD(Chemical Vapour Deposition) using a nitrogen included gas as a source gas or a carrier gas. A plasma processing is performed on the carbon oxide silicon layer by supplying gases, such as a helium, a hydrogen, an N2O, or an Ar gas to a processing chamber. A photoresist is deposited and patterned on the plasma processed carbon oxide silicon layer(111).

Description

A method of forming a semiconductor device having a low dielectric constant interlayer insulating film {METHOD OF FORMING SEMICONDUCTOR DEVICES HAVING SiOC LAYER}

The present invention relates to a method for forming a semiconductor device having a low dielectric constant film, and more particularly, to a method for forming a semiconductor device having a silicon carbide oxide film.

With the high integration of semiconductor devices, the size of individual devices and wirings is reduced. In addition, the distance between the device and the device and the wirings is also reduced. Therefore, the parasitic capacitance between the conductive region and the wirings increases, and the problem that the parasitic capacitance impairs the normal function of the semiconductor device increases. For example, an increase in parasitic capacitance causes resistance capacitance delay in the transmission of semiconductor device signals along with resistance. Since the RC delay degrades the characteristics of the semiconductor device and distorts the signal, various methods for preventing the RC delay have been sought.

As a method of alleviating the problem of parasitic capacitance, such as RC delay, the method of using a low dielectric film as a semiconductor device structure film, such as an interlayer insulation film between wirings, is mentioned. Low dielectric films are a relative concept to conventional interlayer insulating films used in semiconductor devices. For example, a silicon nitride film commonly used as an etch stop film, a capping film, or a spacer film has a high dielectric constant of about 8, and a silicon oxide film most commonly used as an interlayer insulating film has a relative dielectric constant of about 3.7 to 4.

Examples of the low dielectric film include silicon oxide films such as HSQ (hydro silsesquioxane) and MSQ (methyl silsesquoxan), organic polymer-based films formed by SOG (Spin On Glass), and silicon carbide (SiOC) films. Can be. However, the SOG-based silicon oxide film has a large relative dielectric constant gain and is not easy to treat the film precisely, compared with a conventional thermal oxide film and a CVD (chemical vapor deposition) oxide film. Therefore, there is a problem that the etching characteristics are poor and it is difficult to form the wiring trench by the contact hole or the damascene process. In addition, since the curing (curing) is not complete, there is a problem that the film is absorbed, contaminated in the subsequent process.

And a silicon carbide oxide film of carbon can be considered as the equivalent of a silicon oxide film doped (doping), methyl silsesquioxane (MSSQ: Methyl SilSesQuioxane) formed by coating or the like to the SOG method, or methyl groups (CH ₃ -) and Methyl silane-based other organic components formed by the same carbon-containing group by substituting one or more hydrogens in a silylene gas (SiH ₄ ) and gas containing silicon and oxygen elements such as N ₂ O and O ₂ Source gas is supplied with a carrier gas such as N ₂ , NH ₃ , helium (He), argon (Ar), and is usually made by plasma enhanced chemical vapor deposition (PECVD). When the relative dielectric constant of the silicon carbide oxide film is constant at about 2.7 to 2.9, parasitic capacitance can be reduced by 25 to 30% compared to the silicon oxide film.

However, there are some problems because the silicon carbide oxide film is used as an interlayer insulating film or the like. First, in connection with the patterning, there is a footing phenomenon of the photoresist pattern formed on the silicon carbide oxide film. The silicon carbide oxide film partially contains nitrogen atoms contained in the source gas or the carrier gas during the formation. The nitrogen atoms contained in the film are combined with hydrogen ions generated when the photoresist is exposed during the photolithography process for patterning the silicon carbide oxide film to form a polymer of a resin component in the photoresist, or Interfere with the opposite reaction. As a result, the photoresist pattern may not be clearly formed even after the development, and a footing phenomenon may occur in which a portion of the photoresist remains on the lower side of the photoresist pattern as shown in FIG. 1.

This putting phenomenon has a serious effect on chemically amplified photoresists that are increasingly used for the formation of fine patterns in the formation of highly integrated semiconductor devices. In the chemically amplified photoresist, the initial hydrogen ions generated by the sensitizer in the photoresist by the photosensitive reaction are related to the resin component in the surrounding photoresist by heat in the post exposure bake step before the photosensitive development. It causes a large amount of polymer degradation or binding reaction. More hydrogen ions may be generated during this process. However, when a few hydrogen ions generated at the beginning are combined with nitrogen contained in the silicon carbide film under the photoresist, a large amount of chemical reaction may not be triggered even after baking after exposure. Therefore, in the part where the photoresist and silicon carbide oxide film are in contact with each other, the photoresist to be removed remains after development due to lack of reaction.

Next, referring to the problem caused by ashing, oxygen plasma ashing is performed in the process of removing the photoresist pattern used as the etching mask. At this time, there is a problem that the silicon carbide of the interlayer insulating film surface layer is modified and damaged by oxygen plasma. When interacting with an oxygen plasma, the dielectric constant of silicon carbide is raised to a level similar to that of silicon oxide.

In the damascene process, a silicon carbide film is patterned to fill a trench or contact hole with a conductive material, and a chemical mechanical polishing (CMP) is performed to expose the silicon carbide film. Since the silicon carbide film itself is mechanically weak in film quality, a phenomenon such as micro scratch and peeling frequently occurs on the surface of the CMP process for the damascene process.

Another problem of the silicon carbide oxide film is that when the other film is laminated on the silicon carbide film, the adhesion force with the other film is low, so that the other film is not evenly formed or the formed film is easily peeled off.

Regarding the above problems of the silicon carbide oxide film, first, a method of eliminating the problems caused by ashing can be considered. For example, a method of using and removing a hard mask with a photoresist pattern to prevent the low dielectric film from being exposed to ashing oxygen plasma, and a method of using forming gas ashing to remove the photoresist pattern in a hydrogen / nitrogen atmosphere. May be considered. However, these methods have the aspect of lowering the process efficiency. In addition, the problem of mechanical damage in CMP and the like still remains.

In connection with the increase in dielectric constant and mechanical damage caused by ashing, a problem of leaving a thin layer of another insulating film on the silicon carbide film may be considered. By using this insulating film, it is possible to prevent degeneration and damage of the silicon carbide film due to oxygen plasma ashing, and to prevent direct damage of the silicon carbide film due to CMP. However, another problem arises when a silicon oxide film containing silane gas or tetraethyl orthosilicate (TEOS) gas as a source gas is deposited on a silicon carbide oxide film through PECVD. That is, the silicon carbide oxide film has a weak adhesion with these films, and these insulating films themselves are easily peeled off in a process such as CMP.

Looking at the example related to the adhesion of the silicon carbide oxide film, it may be considered to use an organic polymer-based material together with the silicon carbide oxide film as one of the low dielectric constant interlayer insulating film. At this time, examples of the organic polymer-based material used in the semiconductor device may include the Dow Chemical company's trade name SiLK and Alliedsignal trade name FLARE developed for use as a low dielectric constant insulating film (Mat. Res. Soc). Sym.Proc.Vol. 476, 1997: Materials Research Society). When using purely organic polymer-based material as an interlayer insulating film and applying the damascene process, the film has low thermal properties such as thermal conductivity and poor mechanical properties. In order to solve this problem, the interlayer insulating film is complementary to two layers, for example, the interlayer insulating film at the bottom of the contact hole is formed of silicon oxide film, and the interlayer insulating film at the top of the wiring trench is formed of organic polymer. It can be formed into a film. However, organic polymer film is formed by coating method (IEEE 2000, Copper Dual Damascene Interconnects with Very Low-k Dielectrics Targeting for 130nm Node)

At this time, it would be preferable if a silicon carbide oxide film could be used as the lower interlayer insulating film. However, in such a case, the adhesion force of the silicon carbide oxide film is low, so that the formation state of the applied organic polymer film is not uniform, resulting in process failure. In particular, the wafer periphery has a problem that the coating film is easily peeled off or the thickness is not uniform.

The present invention is to improve the various problems when using a silicon carbide film as a low dielectric film as described above, even when using an optical amplification type photoresist on the silicon carbide film, a clear photoresist pattern without putting It is an object to provide a method of forming a semiconductor device that can be formed.

Further, an object of the present invention is to provide a method for forming a semiconductor device without increasing the dielectric constant of the silicon carbide oxide film even when the photoresist pattern used for patterning the silicon carbide oxide film is removed by ashing.

It is still another object of the present invention to form a semiconductor device capable of preventing micro scratches and peeling and process defects from occurring during the CMP step when contacts and wirings are formed on the silicon carbide oxide film through a damascene process. To provide a way.

The present invention also provides a semiconductor device that can prevent a coating defect or a process defect due to peeling of a formed film when a CVD insulating film or an organic polymer coating insulating film is formed on a silicon carbide oxide film and subjected to damascene. It is an object to provide a method.

FIG. 1 is an electron micrograph showing that in the conventional process of patterning a silicon carbide oxide film, a footing phenomenon occurs in which a part of the photoresist to be removed is left under the photoresist pattern.

2 to 4 are process cross-sectional views schematically showing a part of the side surface of the substrate in each step in an example of the present invention.

5 to 9 are cross-sectional views showing process critical steps in another embodiment of the present invention.

10 and 13 are cross-sectional views showing some important steps of an embodiment of forming a silicon carbide interlayer insulating film in an SOG manner.

14 is a graph showing the accumulation distribution of parasitic capacitance in the embodiments and comparative examples of the present invention.

※ Explanation of codes for main parts of drawing

100: substrate 110, 111, 210, 211: silicon carbide oxide film

113,213: silicon carbide oxide film pattern 120: photoresist film

123: photoresist film pattern 125: photo mask

130: capping film 131: capping film pattern

140: contact hole 150, 250: groove

160,260: barrier metal pattern 170: contact plug

180,280: Wiring

A method of the present invention for achieving the above object comprises the steps of forming a silicon carbide film on a substrate, performing a plasma treatment on the silicon carbide film, and patterning the silicon carbide film.

In the present invention, a silicon carbide oxide film is typically formed by a CVD method such as PECVD and is made in an environment where nitrogen atoms are supplied to a source gas or a carrier gas.

The plasma treatment step of the silicon carbide film is performed by supplying a combination of one or more of helium, hydrogen, nitrogen oxide (N ₂ 0), oxygen, nitrogen, ammonia, and argon gas to a process chamber in which a substrate is placed. Can be. At this time, the plasma treatment is performed by forming a plasma environment in which the combination gas is converted into plasma.

In particular, in the present invention, it is preferable to use hydrogen plasma for plasma treatment. The hydrogen plasma treatment step may be accomplished by supplying hydrogen gas without source gas for stacking material films under PECVD conditions to form a plasma and acting a hydrogen plasma on the wafer surface.

Plasma application, including hydrogen plasma, is preferably performed by injecting hydrogen or other plasma source gas into the same chamber in situ immediately after forming a silicon carbide film in a PECVD apparatus, thereby reducing the process burden.

After the plasma treatment is performed in the present invention, a step of forming an organic polymer-based coating film, or a capping film made of an oxide film or a nitride film formed by CVD may be further provided.

In the present invention, the photolithography process used in the step of patterning the silicon carbide oxide film formed after the plasma treatment is a conventional photolithography process such as photoresist lamination, mask exposure, and development. It is conceivable that what is done through patterning is simply a contact hole and a case including a wiring trench, such as a damascene process.

In addition, in the present invention, in the case where an organic polymer-based coating film or CVD oxide film is further laminated and patterned after the plasma treatment, the conductive film may be further laminated and CMP subsequently.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Example 1

2 to 4 are cross-sectional views schematically showing a part of the side surface of the substrate in each step in an example of the present invention.

Referring to FIG. 2, a silicon carbide oxide film 110 is formed on a substrate 100 having a previous step. The silicon carbide oxide film 110 is mainly laminated with an interlayer insulating film, which is formed by a PECVD method, and is made under a pressure of about 1 to 10 Torr and a temperature of about 300 to 400 ° C. As the source gas, trimethyl silane gas for supplying silicon and carbon and N ₂ O and O ₂ gas for supplying oxygen are used, and nitrogen or argon gas is used as a carrier gas. At this time, instead of the tri-methyl silylene, a methyl xylene series such as mono-methyl silen, di-methyl silene, tetra-methyl silene may be used, or other organic silicon gas may be used. .

Then, plasma treatment is performed on the substrate 100 on which the silicon carbide oxide film 110 is formed to form a plasma-treated silicon carbide oxide film 111. The plasma treatment step may be performed in situ in the PECVD chamber in which the silicon carbide oxide film 110 of the previous step is formed. At this time, the temperature and pressure may be applied to a pressure of about 1 to 10 Torr and a temperature of 300 to 400 ℃ similar to the conditions for forming the silicon carbide oxide film 110, the gas to form a plasma helium, hydrogen, nitrogen oxides , Ammonia, nitrogen, oxygen, argon may be supplied individually or in combination.

However, the plasma processing gas is not limited to these gases, and a plasma source gas capable of combining nitrogen with hydrogen in the surface of the silicon carbide oxide film to saturate or remove nitrogen, or to form a stable nitrogen compound or other protective film on the surface of the silicon carbide oxide film. Is possible. The plasma treatment time is about 10 to 20 seconds.

Referring to FIG. 3, a chemically amplified photoresist film 120 is coated on a plasma treated silicon carbide oxide film 111 by a spin coating method. The photoresist film 120 is exposed to light under the photo mask 125. The photochemical reaction occurs at the exposed part, and in the case of the positive photoresist, the sensitizer causes the photochemical reaction to generate hydrogen ions.

Subsequently, the substrate subjected to the exposure is subjected to the baking after exposure at a temperature of about 80 ° C., and the decomposition reaction of the resin polymer of the photoresist in the region exposed by the heat and the acidic environment by the hydrogen ions already generated is actively performed.

Referring to FIG. 4, a post-exposure bake is performed and development is performed to form a photoresist pattern 123. The photoresist decomposed in the developing step is dissolved in and removed from the developer, and only the unexposed portion remains to form the photoresist pattern 123. The silicon carbide film below is etched using the photoresist pattern 123 as an etch mask to form a silicon carbide film pattern 113 having contact holes or the like.

Thereafter, the photoresist pattern 123 is removed and the conductive layer is stacked on the substrate to fill the etched portions such as contact holes of the silicon carbide oxide film.

On the other hand, Table 1 below shows the change in the relative dielectric constant resulting from several types of plasma treatment under the same conditions as in the embodiment after the silicon carbide film is formed, Table 2 is a helium plasma treatment after the silicon carbide film is formed In the case of the dielectric constant change over time is shown.

Type of plasma treatment Measured relative dielectric constant If not processed (deposited) 2.84 Helium (He) plasma treatment 2.91 Hydrogen (H ₂ ) plasma treatment 2.87 Nitric oxide (N ₂ O) plasma treatment 2.91

Plasma Treatment Time (Helium Plasma Treatment) Measured relative dielectric constant 0 (deposited) 2.84 20 seconds 2.91 40 seconds 2.91 60 seconds 2.90

In the results shown in the above tables, the relative dielectric constant change of the silicon carbide oxide film according to each plasma type of Table 1 is low as the increase rate less than 2%. In other words, the plasma treatment does not significantly affect the relative dielectric constant of the silicon carbide oxide film, and accordingly, the advantage of using the silicon carbide oxide film as an interlayer insulating film can be maintained. 5A to 5C are electron micrographs showing the no-put photoresist pattern obtained by various plasma treatments.

In addition, considering Table 2, the change in relative dielectric constant with time of the plasma treatment is also less than 2%, indicating that the margin of the plasma treatment process can be sufficient. In addition, although not clearly shown in the table, when the treatment time is about 10 seconds, the increase in the dielectric constant indicates a saturation state.

(Example 2)

Referring to FIG. 5, a silicon carbide film 110 is formed as an interlayer insulating film on a substrate 100 on which a substructure such as a MOSFET is formed. The silicon carbide oxide film 110 is formed by PECVD, and organic silane is used as the source gas such as trimethyl silane. At this time, a typical condition is a temperature of 250 to 400 degrees Celsius, a pressure of 1 to 10 Torr, the high-frequency power for plasma formation is applied to about 200watt at 13,6 MHz in 8-inch wafer single wafer CVD equipment. The processing time is adjusted according to the thickness of the silicon carbide oxide film 110.

Referring to FIGS. 5 and 6, following the deposition of the silicon carbide oxide film 110, hydrogen plasma is generated while supplying hydrogen to the processing gas to act on the surface of the substrate 100 on which the silicon carbide oxide film 110 is formed. As for the conditions of the hydrogen plasma treatment, it is preferable to apply the conditions similar to the PECVD film formation except for the source gas. For example, a temperature of 250 to 400 degrees Celsius, a pressure of 1 to 10 Torr, and a high frequency power for plasma formation were applied at about 200 watts at 13,6 MHz in an 8-inch wafer single wafer CVD apparatus to process the substrate for 10 to 200 seconds. do. The treatment time may vary depending on the processing conditions of the subsequent process. However, when the characteristics of the semiconductor device formed after the post-treatment are examined, the silicon carbide oxide film whose surface treatment is semi-saturated through the processing time of about 30 to 50 seconds ( 111).

When hydrogen plasma is applied to the silicon carbide film, the bond between the silicon atom and the hydroxyl group and the dangling bond of the silicon are removed, and thus the surface layer has many bonded structures of the silicon atom and the hydrogen atom. As a result, the mechanical strength of the silicon carbide oxide film and the adhesion with other films increase.

Referring to FIG. 7, after the hydrogen plasma treatment, the source gas is changed to TEOS or xylene gas to form an oxide film such as PETEOS (Plasma Enhanced TetraEthylOrthoSilicate) as a capping layer 130 on the hydrogen plasma-treated silicon carbide film 111. do. 5 to 7 is preferably performed in situ in the same PECVD equipment because it can reduce the process cost and time. In addition, a silicon nitride film, a silicon oxynitride film, a silicon carbide film, or the like can be used as the capping film.

Referring to FIGS. 7 and 8, a groove 150 for metal wiring is formed on the hydrogen plasma-treated silicon carbide oxide film 111 covered with the PETEOS oxide film by the capping film 130. The dual damascene method of forming the contact hole 140 in the contact area forming a part of the bottom surface of the groove 150 is adopted. Alternatively, the contact plug may be formed first, the interlayer insulating film may be covered, and then a groove for exposing the contact plug may be formed. The groove 150 and the contact hole 140 may be formed by forming a photoresist pattern (not shown) through photolithography and selectively capping the film 130 and the silicon carbide film 111 using the photoresist pattern as an etching mask. It usually consists of an etching step of etching. Subsequently, ashing is used to remove the photoresist pattern. In this case, the silicon carbide oxide film pattern 113 is covered with the capping film pattern 131 except for the region to be etched, and maintains a low dielectric constant even when subjected to the hydrogen plasma treatment to the action of the oxygen plasma.

8 and 9, the Ti / TiN barrier metal layer and the wiring CVD tungsten metal layer are sequentially stacked on the substrate on which the groove 150 and the contact hole 140 are formed. In addition, the capping layer pattern 131 is exposed by planarization of the metal layer and the barrier metal layer through chemical mechanical polishing (CMP). Accordingly, the barrier metal layer and the wiring metal layer except for the metal pattern filling the groove 150 and the contact hole 140 are removed, and the wiring 180 and the contact plug 170 are formed. The barrier metal pattern 160 is present between the wiring 180 and the contact plug 170 formed of the metal layer and the silicon carbide oxide film pattern 113. Since the capping film pattern 131 is firmly attached to the surface of the silicon carbide film pattern 113 through hydrogen plasma treatment with respect to the silicon carbide film, peeling of the capping film pattern 131 may be suppressed in the CMP process. However, the barrier metal layer stacked on the capping layer pattern 131 may be removed through subsequent etching separate from the planarization etching of the metal layer. In this case, the capping layer pattern 131 may be removed during the CMP process on the metal layer. Peeling can be suppressed while covering with metal.

Example 3

10 and 13 are cross-sectional views showing some important steps of an embodiment of forming a silicon carbide interlayer insulating film in an SOG manner.

Referring to FIG. 10, a silicon carbide oxide film 210 is laminated by applying a sol (SOL) type material including methyl silsesquioxane to the substrate 100 on which the transistor structure is formed. At this time, after forming the film by a conventional coating method, the solvent is removed and a hard bake process is performed to form a hard bake and a hardened silicon carbide oxide film 210 that leaves a solid material.

10 and 11, following formation of the silicon carbide oxide film 210, hydrogen plasma is generated while supplying hydrogen to the processing gas to act on the surface of the substrate 100 on which the silicon carbide oxide film 210 is formed. In the initial silicon carbide film 210, organic groups such as methyl groups are more likely to be bonded to the silicon atoms of the film, but silicon oxide and hydrogen atoms are more likely to be bonded to the silicon carbide film 211 subjected to the hydrogen plasma treatment. Therefore, it is possible to reduce problems of dielectric constant increase and mechanical damage of the silicon carbide oxide film.

11 and 12, the silicon carbide oxide film pattern 213 is formed by forming the groove 250 on the hydrogen plasma treated silicon carbide oxide film 211. More specifically, first, a photoresist pattern (not shown) is formed on the silicon carbide oxide film 211, and the groove 250 is formed in the wiring region by etching. The photoresist pattern is removed by ashing. At this time, the oxygen plasma is used for ashing, but since the silicon carbide film 211 is already treated with hydrogen plasma, the dielectric constant increase of the silicon carbide oxide film by ashing is insignificant.

12 and 13, the wire 250 is filled with the barrier metal and the copper metal in the groove 250. This completes the damascene process. More specifically, the barrier metal layer and the copper metal layer are stacked on the silicon carbide oxide film pattern 213 to fill the groove 250. The barrier metal layer and the copper metal layer stacked off the groove 250 and stacked on the silicon carbide oxide film pattern 213 are removed using CMP. Accordingly, the upper surface of the silicon carbide oxide film pattern 213 is exposed, and a wiring including the barrier metal pattern 260 and the metal pattern 280 is formed. Since the surface of the silicon carbide film pattern 213 is already subjected to hydrogen plasma treatment and resistant to mechanical cutting, the silicon carbide film pattern 213 is not easily damaged even during a CMP process. Therefore, it is possible to prevent the generation of particles due to abnormal peeling in this process, and to prevent the process failure of the semiconductor device.

14 is a silicon oxide film (FSG) containing a fluorine (F) component as an interlayer insulating film, a silicon carbide oxide film (SiOC) ashed with oxygen plasma after film formation, and hydrogen plasma treatment before oxygen plasma treatment after film formation. The graph shows so that parasitic capacitor values of a semiconductor device can be compared with respect to the case where each of the examples of the silicon carbide oxide film (SiOC) is used as an interlayer insulating film. According to this graph, when a silicon carbide oxide film is formed of a low dielectric film and exposed to oxygen plasma ashing, the dielectric constant is about the same as or slightly lower than that of a fluorine-containing silicon oxide film. However, it can be seen that when the hydrogen plasma treatment is carried out like the present invention before ashing, even when exposed to the oxygen plasma in ashing, the relative dielectric constant which is lower than that of the initial formation is lower than that of the fluorine-containing silicon oxide film. According to the present invention on the graph, there is a reduction in parasitic capacitance of about 15 to 30% compared to the conventional silicon carbide oxide film not subjected to hydrogen plasma treatment.

The following table shows the results of investigating whether the silicon carbide film was formed to a thickness of 5000 angstroms on the entire surface of the experimental wafer, and the capping film was peeled off when the CMP was carried out with two kinds of slurry after the capping film was laminated. In this case, the irradiation is carried out on (1) fluorine-containing silicon oxide film (FSG), (1) PECVD oxide film (PETEOS) using TEOS gas, or (3) PECVD oxide film (PEOX) directly using silicon carbide film BD. And (4) capped oxide film (NH ₃ PLASMA + TEOS) using TEOS gas after ammonia plasma treatment and (5) capped oxide film (H ₂ PLASMA + TEOS) using TEOS gas after hydrogen plasma treatment. This is done for the case of capping.

Slurry / capping FSG PETEOS PEOX NH ₃ PLASMA + TEOS H ₂ PLASMA + TEOS Slurry1 normal Peeling Peeling Peeling normal Slurry2 normal Peeling Peeling normal normal

According to inspection using In Line SEM (ILS), the major process defect is micro scratch. As a result, the peeling of the capping film can be prevented when the surface is treated with plasma before the capping film is formed. In particular, when the surface is treated with hydrogen plasma as in the present invention, the peeling can be more reliably prevented.

(Example 4)

In this embodiment, first, a silicon carbide oxide film is formed on the substrate as an interlayer insulating film. At this time, the forming method may be a coating method or a CVD method such as PECVD, but PECVD is preferable. Then, the plasma processing gas is added to the same atmosphere as the PECVD process except for the source gas for film formation. Thus, plasma is generated from gases such as ammonia, hydrogen, nitrogen, and oxygen to act on the wafer surface. The surface of the silicon carbide oxide film is modified. An organic polymer-based film is formed on the modified surface. The organic polymer-based film is formed by a coating method, and the film is cured through a curing process of 400 to 450 degrees after application. As the organic polymer film, a material having the thermal and mechanical properties of the semiconductor interlayer insulating film such as the trade name SiLK and the trade name FLARE and having a low dielectric constant is used. In this case, the organic polymer film may be uniformly coated on the silicon carbide oxide film by plasma treatment of the silicon carbide oxide film.

When the silicon carbide oxide film and the organic polymer film are successively stacked to form an interlayer insulating film, etching is performed to form wiring trenches for the exposed organic polymer film. Etching is performed until the silicon carbide oxide film forming the lower interlayer insulating film is exposed. Next, a contact hole is formed by patterning to etch the silicon carbide oxide film exposed on the bottom surface of the trench in a portion of the wiring trench. The difference between the two membranes can increase process margins in determining the timing of trench etching. Metal CVD is performed to fill the contact holes and wiring trenches. At this time, as the metal layer, copper, tungsten, or the like, which can lower the resistance, may be laminated. The metal layer is also laminated on the organic polymer film. Thus, to complete the wiring, the metal layer deposited on the organic polymer film is removed through the CMP, and the metal layer is left only in the trenches and contact holes.

As described above, when the contact is formed, the parasitic capacitance between the contact plugs can be suppressed even when the contact formation density is high due to the low dielectric constant of the silicon carbide oxide film. In addition, even when the thickness of the interlayer insulating film is thin, parasitic capacitance between the upper and lower layer wirings can be reduced.

According to the present invention, it is possible to form a clear photoresist pattern on the silicon carbide oxide film by preventing the conventional putting phenomenon while patterning the silicon carbide film in the semiconductor device. As a result, fine patterns can be accurately formed in the silicon carbide oxide film, and parasitic capacitance between interlayer wiring or between contact plugs can be effectively suppressed.

Claims (20)

Forming a silicon carbide oxide film on the substrate, Performing a plasma treatment on the silicon carbide oxide film; And depositing and patterning photoresist on the plasma-treated silicon carbide oxide film. The method of claim 1, The silicon carbide oxide film is formed by a CVD method, A method of forming a semiconductor device having a low dielectric constant interlayer insulating film, wherein a gas containing nitrogen atoms is supplied to a source gas or a carrier gas in the process of forming the silicon carbide oxide film. The method according to claim 1 or 2, Wherein the plasma processing step is a semiconductor device forming method having a low dielectric constant interlayer insulating film characterized in that the supply of at least one of helium, hydrogen, nitrogen oxides (N ₂ O), oxygen, argon gas to the process chamber on which the substrate is stacked . The method of claim 1, And forming said silicon carbide oxide film and said plasma treatment step are in situ in a process chamber for PECVD. The method according to claim 1 or 4, And forming the silicon carbide oxide film and performing the plasma treatment step under a pressure of 1 to 10 Torr and a temperature of 300 to 400 ° C. The method of claim 1, In the forming of the silicon carbide film, a gas of carbon and silicon is used as a gas of oxygen and a gas of silicon xylene-based in which at least one hydrogen group is substituted with a methyl group (CH ₃ −) in xylene. A method of forming a semiconductor device having a low dielectric constant interlayer insulating film, characterized by using nitrogen oxide (N ₂ O) or oxygen. The method of claim 1, And the photoresist is a chemically amplified photoresist that generates hydrogen ions (H +) during light exposure. The method according to claim 1 or 7, Patterning the stacked photoresist is An exposure step of exposing to a light source under a photo mask, Post exposure bake step, A semiconductor device forming method having a low dielectric constant interlayer insulating film, characterized by comprising a developing step. Stacking a silicon carbide oxide film (SiOC) on a substrate; Performing plasma treatment on the silicon carbide oxide film; and And forming a wiring through the damascene process in the silicon carbide oxide film. The method of claim 9, Using hydrogen plasma in the plasma treatment step, The plasma processing step; Between the steps of forming the wiring; And forming a capping insulating film on the silicon carbide oxide film. The method of claim 10, The insulating film is a semiconductor device forming method having a low dielectric constant interlayer insulating film, characterized in that made of a PECVD film made of a source gas of xylene or TEE (TetraEthylOrthoSilicate) gas. The method of claim 10, The hydrogen plasma processing step is a semiconductor device forming method having a low dielectric constant interlayer insulating film, characterized in that while applying a high-frequency electric field in a temperature of 250 to 400 degrees Celsius, pressure 1 to 10 Torr, hydrogen atmosphere. The method of claim 10, Forming a wiring through the damascene process is; Forming a photoresist pattern on the silicon carbide film; Forming a groove on the silicon carbide oxide film using the photoresist pattern as an etching mask; Removing the photoresist pattern on the substrate on which the groove is formed by ashing using oxygen plasma; Filling the groove by sequentially laminating a barrier metal and a wiring metal layer on the substrate on which the groove is formed; And removing the wiring metal layer laminated on the silicon carbide oxide upper surface by using chemical mechanical polishing (CMP). The method of claim 13, And the wiring metal layer is formed of copper. The method of claim 10, The damascene process first forms the grooves, And forming a contact hole in a specific region of said groove. The method of claim 10, And the silicon carbide oxide film is formed using a spin on glass (SOG) method. The method of claim 9, The plasma processing step; Between the steps of forming the wiring; A method of forming a semiconductor device having a low dielectric constant interlayer insulating film, further comprising the step of forming an organic polymer film using a coating method on the silicon carbide film. The method of claim 17, And depositing a silicon carbide oxide film on the substrate using an SOG method (coating method) or a PECVD method. The method of claim 17, The forming of the organic polymer film is a method of forming a semiconductor device having a low dielectric constant interlayer insulating film, characterized in that formed by forming a film on the substrate by a coating method and curing at a high temperature of 400 to 450 ℃. The method of claim 17, The damascene process may include forming a groove on the organic polymer film through a patterning process; And forming a contact hole in the silicon carbide oxide film through a patterning process in a specific region of the groove, the semiconductor device forming method having a low dielectric constant interlayer insulating film.