KR20020043736A - Semiconductor memory device - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided to reduce a power consumption by simply constituting a write/read circuit. CONSTITUTION: A semiconductor memory device comprises a clock signal generator(30), a delay circuit(32) generating a data input/output control signal(pcdin) by delaying an output signal of the clock signal generator(30), a NAND gate(NA5) inputted with a write enable signal(WE) having a "HIGH" level and an input data(Din), an AND gate(AN4) inputted with a clock signal(psum) and an output signal of the NAND gate(NA5), the other AND gate(AN5) inputted with the clock signal(psum), the input data(Din) and the write enable signal(WE), and word line control signal generators(40-1,40-2,40-3,40-4) respectively having NAND gates(NA6,NA7) and inverters. At this point, when a "LOW" level input data(Din) is supplied in write cycle, a lower word line is then selected to write the selected datum. As the same, when a "HIGH" level input data(Din) is supplied in write cycle, datum of an upper word line is written.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a single bit line cells.

As microprocessors and digital signal processing systems become faster, semiconductor memory devices applied to these systems also require high speed, high integration, and low voltage characteristics.

In accordance with this trend, a semiconductor memory device having single bit line cells for performing a low voltage and high-speed read / write operation while reducing the area of a bit cell has been proposed.

However, in the conventional semiconductor memory device having single bit cells, the write / read control circuit is configured to write data to the memory cells twice in a write cycle.

Accordingly, the conventional semiconductor memory device having single bit cells has a problem in that the write / read control circuit is complicated in structure and power consumed by writing data twice in a write cycle increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device having a simple write operation and a simple read / lead control circuit in the case of writing data to single bit cells.

The semiconductor memory device of the present invention for achieving the above object is a memory cell array having a plurality of memory cells connected between each of a plurality of bit lines, a plurality of upper word lines, and a plurality of lower word lines, A row address decoder for generating a plurality of word line selection signals in response to a first row address of a predetermined bit; in a write cycle, one of the upper and lower control signals is enabled and read according to the level of the input data. In the cycle, the upper (or lower) control signal is enabled, and the upper and lower control signals are received in a predetermined number of upper and lower parts in response to each of a predetermined number of decoding output signals that decode a second row address of a predetermined bit. Write / read control means for generating word line control signals, and the plurality of words And a word line driver which is enabled in response to each of the in select signals, and inputs the predetermined number of upper and lower word line control signals to drive the plurality of upper word lines and the plurality of lower word lines. It is characterized by.

1 is a block diagram illustrating a configuration of a semiconductor memory device having conventional unit bit cells.

FIG. 2 is a circuit diagram of an embodiment of the write / read control circuit shown in FIG.

3A and 3B are operation timing diagrams for explaining the operation of the semiconductor memory device having single bit cells to which the write / read control circuit shown in Fig. 2 is applied.

Figure 4 is a circuit diagram of an embodiment of a write / lead control circuit of a semiconductor memory device having single bit cells of the present invention.

5A and 5B are operation timing diagrams for explaining the operation of the semiconductor memory device having single bit cells to which the write / read control circuit shown in Fig. 4 is applied.

Hereinafter, a configuration and an operation of a semiconductor memory device having conventional single bit cells will be described with reference to the accompanying drawings.

1 is a block diagram showing the configuration of a semiconductor memory device having a conventional single bit line ^{cell, 2.3㎛ 2 16Mb CMOS SRAM (A} 16Mb CMOS SRAM with a single bit line memory cell with a 2.3㎛ ² Single- Bit-Line Memory Cell is published in the IEEE Journal of Solid State Circuits, Vol. 28, NO. 11, November 1993.

The semiconductor memory device shown in Fig. 1 includes a memory cell array 10, a row address decoder 12, a word line driver 14, a write / read control circuit 16, a column select gate circuit 18, and a data input / output control circuit. And a column address decoder 22.

The memory cell array 10 includes a plurality of single bit lines b1, b2,..., Bk, a plurality of upper word lines WiU, W2U, ..., WmU, and a plurality of lower word lines. (WIL, W2L, ..., WmL) A plurality of memory cells MC are connected between each other.

Each of the plurality of memory cells MC is configured by a latch LA formed of NMOS transistors N1 and N2 and inverters I1 and I2.

The word line driver 14 is enabled in response to the word line select signal WL1 and inverts the lower word line control signal pW1L to generate a control signal for selecting the lower word line W1L. Is generated in response to the word line selection signal WL1 and inverts the upper word line control signal pW1U to generate a control signal for selecting the upper word line W1U. An inverter I5 for generating a control signal for selecting the lower word line W2L by inverting the lower word line control signal pW2L in response to WL1, and an upper part in response to the word line selection signal WL1. The inverter I6 is configured to generate a control signal for selecting the upper word line W2U by inverting the word line control signal pW2U. Although not shown, the control signals for selecting the upper word lines W3U and W4U are generated by inputting the upper word line control signals pW3U and pW4U, which are enabled in response to the word line selection signal WL1, and lower. Inverters (not shown) for inputting word line control signals pW3L and pW4L to generate control signals for selecting lower word lines W3L and W4L. In the same manner as described above, the four upper and lower word line control signals (pW1L, pW1U), (pW2L, pW2U), which are enabled in response to the word line select signals WL2, ..., WLm, Control signal for selecting lower and upper word lines ((W1L, W1U), (W2L, W2U), ..., (WmL, WmU) by inputting (pW3L, pW3U), (pW4L, pW4U) Will occur respectively.

The function of each of the blocks shown in FIG. 1 will be described below.

The memory cell array 10 transmits data to the bit lines b1, b2,..., Bk in response to control signals for selecting upper and lower word lines W1U and W1L in a write cycle. Is written twice, and in the read cycle, the data stored in the latch LA in response to a control signal for selecting the upper or lower word lines W1U and W1L is selected from the bit lines b1, b2, ..., bk). The row address decoder 12 generates word line select signals WL1, WL2, ..., WLm for selecting word lines by decoding the row address Xi. The word line driver 14 is enabled in response to each of the word line select signals WL1, WL2, ..., WLm, and the word line control signals (pW1L, pW1U), (pW2L, pW2U), ( pW3L, pW3U), (pW4L, pW4U)) are input to control signals for selecting word lines (W1L, W1U), (W2L, W2U), (W3L, W3U), (W4L, W4U), respectively. Occurs. The write / read control circuit 16 generates upper and lower word line control signals each time an address input change in a write cycle, a change from a read operation to a write operation, or an input data change occurs. The pulse signals pATD, pWE, pDIN are generated by detecting an address input change, a change from a read operation to a write operation, or a change in input data. In addition, a pulse signal pcdin for input / output data (Din / Dout) transmission between the data lines (not shown) and the column select gate circuit 18 is generated. The column select gate circuit 18 selects the bit lines selected by selecting the bit lines b1, b2, ..., bk, respectively, in response to the column select control signals Y0, Y1, ..., Yk. Data is transmitted between (b1, b2, ..., bk) and data lines (not shown). The data input / output control circuit 20 transmits input / output data (Din / Dout) between the data lines (not shown) and the column select gate circuit 18 in response to the pulse signal pcdin. The column address decoder 22 generates column select control signals Y0, Y1, ..., Yk by decoding the column address Yj.

FIG. 2 is a circuit diagram of the embodiment of the write / lead control circuit shown in FIG. 1, which includes a clock signal combination circuit 30, delay circuits 32 and 34, and word line control signal generation circuits 36-1 and 36-2. 36-3, 36-4, AND gate AN1, inverters I7, I8, and I9, and NAND gates NA1, NA2, NA3, and NA4.

Each of the word line control signal generation circuits 36-1, 36-2, 36-3, ..., 36-4 is composed of AND gates AN2 and AN3 and inverters I10 and I11. have.

The operation of the circuit shown in Fig. 2 is as follows.

The clock signal combination circuit 30 generates the combined pulse signal pSUM by combining the pulse signals pATD, pWE, and pDin. In the write cycle, the write enable signals WE1 and WE2 are all at "high" level, and in the read cycle, the write enable signals WE1 and WE2 are all at "low" level. The AND gate AN1 generates the combined pulse signal pSUM as the pulse signal p1 in response to the write enable signal WE1 of the "high" level. The delay circuit 32 delays the pulse signal p1 by a predetermined time to generate a pulse signal pcdin, and the delay circuit 34 delays the pulse signal p1 by a predetermined time. Inverters I7 and I8 invert the pulse signals p1 and p2, respectively. At this time, the pulse signal p1 is generated before the pulse signal p2. The NAND gates NA1 and NA3 generate a "high" level signal regardless of the input data Din when the pulse signal p1 is at "high" level, and the pulse signal p1 is at "low" level. When the input data Din is at the "high" level, signals of the "low" level and the "high" level are generated, respectively. When the input data Din is at the "low" level, the signals of the "high" level and "low" level are generated. Occurs each. The NAND gates NA2 and NA4 generate signals of the "low" level and the "high" level, respectively, when the input data Din is the "high" level when the pulse signal p2 is the "low" level. When the data Din is at the "low" level, signals of the "high" level and the "low" level are generated. The NAND gates NA2 and NA4 generate a signal of a "high" level regardless of the pressure data Din when the pulse signal p2 is at the "high" level. The AND gate AN2 and the inverter I10 are the lower word line control signals having the "low" level when the output signals of the NAND gates NA1 and NA2 are at the "high" level when the decoding signal X0X1 is at the "high" level. (pW1L) is generated. The AND gate AN3 and the inverter I11 are the upper word line control signals of the "low" level when the output signals of the NAND gates NA3 and NA4 are at the "high" level when the decoding signal X0X1 is at the "high" level. (pW1U).

The other word line control signal generating circuits 36-2, 36-3, and 36-4 are lower word line control signals pW2L in response to the "high" level decoding signals XOBX1, X0X1B, and X0BX1B, respectively. , pW3L, pW4L) and upper word line control signals pW2U, pW3U, pW4U, respectively.

3A and 3B are operation timing diagrams for explaining the operation of a semiconductor memory device having single bit cells to which the write / read control circuit shown in Fig. 2 is applied, and Fig. 3A is a "low" level of input data Din. 3B shows an operation timing diagram when the input data Din is at the "high" level, respectively. FIG. 3B shows an operation timing diagram when the "high" level decoding signal XOX1 is generated. It represents.

In FIG. 3A, when the "high" level decoding signal X0X1 is generated, and in the write cycle, when the "high" level pulse signal p1 and the "low" level pulse signal p2 are generated, NAND gates are generated. The output signals of (NA1, NA3) become the "high" level, and the output signals of the NAND gates NA2, NA4 become the "low" level and "high" level, respectively. Then, the AND gate AN2 and the inverter I10 generate the lower word line control signal pW1L at the "high" level, and the AND gate AN3 and the inverter I11 control the upper word line at the "low" level. Generate the signal pW1U. The data input / output control signal pcdin is generated by delaying the pulse signal p1, and the input data Din is transmitted to the selected bit line in response to the control signal pcdin of the "high" level. The data is written to the memory cell MC once the word line W1U is selected in response to the upper word line control signal pW1U having the "low" level.

Then, when the "low" level pulse signal p1 and the "high" level pulse signal p2 are generated, the output signals of the NAND gates NA2 and NA4 become the "high" level, and the NAND gates The output signals of (NA1, NA3) become "high" level and "low" level, respectively. Then, the AND gate AN2 and the inverter I10 generate the lower word line control signal pW1L at the "low" level, and the AND gate AN3 and the inverter I11 control the upper word line at the "high" level. Generate the signal pW1U. By the word line W1L being selected in response to the "low" level lower word line control signal pW1L, data is written once more to the memory cell MC.

In Fig. 3B, when the "high" level decoding signal X0X1 is generated, and the "high" level pulse signal p1 and the "low" level pulse signal p2 are generated, the lower word of the "low" level is generated. The line control signal pW1L is generated, and accordingly, the word line W1L is selected to write data to the memory cell MC once.

Then, when the pulse signal p1 at the "low" level and the pulse signal p2 at the "high" level are generated, the upper word line control signal pW1U at the "low" level is generated, and thus the word line ( By selecting W1U), data is written to the memory cell MC once again.

That is, the conventional semiconductor memory device having single bit cells first writes the input data through the NMOS transistor N1 connected to the upper word line W1U when the input data Din is at the "low" level. The data is once again written through the NMOS transistor N2 connected to the word line W1U.

On the other hand, when the input data Din is at the "high" level, the data is first written through the NMOS transistor N2 connected to the lower word line W1L and the NMOS transistor N1 connected to the upper word line W1U. Rewrite the data once again.

In the read cycle, the upper word line control signal becomes the "low" level, and the lower word line control signal is fixed to the "high" level. Therefore, only the upper word lines W1U, W2U, ..., WmU are selected in the read cycle, and the lower word lines W1L, W2L, ..., WmL are not selected.

That is, a conventional semiconductor memory device having single bit cells writes data twice in a write cycle and writes data once in a read cycle. In the read cycle, data is read once. Therefore, there is a problem that the write operation is not simple and the configuration of the write / read control circuit is complicated.

4 is a circuit diagram of an embodiment of a write / read control circuit of a semiconductor memory device having single bit cells of the present invention, wherein the clock signal generation circuit 30, the AND gates AN4 and AN5, the delay circuit 32, NAND gate NA5 and word line control signal generation circuits 40-1, 40-2, 40-3, 40-4.

Each of the word line control signal generation circuits 40-1, 40-2, 40-3, and 40-4 is composed of NAND gates NA6 and NA7 and inverters I12 and I13.

The operation of the circuit shown in Fig. 4 is as follows.

The operation of the clock signal generation circuit 30 is referred to the description shown in FIG. The delay circuit 32 delays the output signal of the clock signal generation circuit 30 to generate a data input / output control signal pcdin. The NAND gate NA5 nonlogically multiplies the write enable signal WE of the "high" level and the input data Din. The AND gate AN4 multiplies the clock signal psum by the output signal of the NAND gate NA5, and the AND gate AN5 performs the clock signal psum, the input data Din, and the write enable signal WE. Multiply by.

The NAND gate NA6 and the inverter I12 multiply the output signal of the decoding signal X0X1 and the AND gate AN4 to generate an upper word line control signal pW1U. The NAND gate NA7 and the inverter I13 generate a lower word line control signal pW1L by ANDing the decoded signal X0X1 and the output signal of the AND gate AN5.

5A and 5B are operation timing diagrams for explaining the operation of a semiconductor memory device having single bit cells to which the write / read control circuit shown in Fig. 4 is applied, and Fig. 5A is a "low" level of input data Din. 5B shows an operation timing diagram when the input data Din is at the "high" level, respectively. FIG. 5B shows an operation timing diagram when the "high" level decoding signal XOX1 is generated. It represents.

In Fig. 5A, when a "high" level decoding signal X0X1 is generated, and in a write cycle, when a "high" level pulse signal psum is generated, the NAND gate NA5 generates a "high" level signal. The AND gates AN4 and AN5 generate signals of the "high" level and the "low" level, respectively. The NAND gate NA6 and the inverter I12 generate the high word line control signal pW1U at the "high" level, and the NAND gate NA7 and the inverter I13 generate the low word line control signal at the "low" level. pW1L). The data input / output control signal pcdin is generated by delaying the pulse signal psum, and the input data Din is transmitted to the selected bit line in response to the control signal pcdin of the "high" level. The data is written to the memory cell MC by selecting the lower word line W1L in response to the lower word line control signal pW1L having the "low" level.

In Fig. 5B, when the "high" level decoding signal X0X1 is generated and the "high" level pulse signal psum is generated, the NAND gate NA5 generates a "low" level signal, and the AND gate AN4 and AN5 generate signals of "low" level and "high" level, respectively. The NAND gate NA6 and the inverter I12 generate the upper word line control signal pW1U at the "low" level, and the NAND gate NA7 and the inverter I13 generate the lower word line control signal at the "high" level ( pW1L). The data input / output control signal pcdin is generated by delaying the pulse signal psum, and the input data Din is transmitted to the selected bit line in response to the control signal pcdin of the "high" level. The data is written to the memory cell MC by selecting the upper word line W1U in response to the upper word line control signal pW1U having a "low" level.

That is, in the semiconductor memory device having single bit cells of the present invention, when the "low" level input data Din is applied in the write cycle, the lower word line is selected to write the data, and the "high" level input data. When (Din) is applied, the upper word line is selected and data is written.

In the read operation, the AND gate AN5 generates a "low" level signal, and the AND gate AN4 always outputs a "high" level signal regardless of the input data Din. As a result, only the upper word line is selected and data is read.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Therefore, in the semiconductor memory device having the unit bit cells of the present invention, since the data is written only once in a write cycle, the configuration of the write / read control circuit is simple, thereby reducing power consumption.

Claims (4)

A memory cell array having a plurality of bit lines, a plurality of upper word lines, and a plurality of memory cells connected between each of the plurality of lower word lines; A row address decoder for generating a plurality of word line select signals in response to a first row address of a predetermined bit; In the write cycle, one of the upper and lower control signals is enabled according to the level of the input data, and in the read cycle, the upper (or lower) control signal is enabled, and the second row address of the predetermined bit is set. Write / lead control means for generating the upper and lower control signals into a predetermined number of upper and lower word line control signals in response to each of a predetermined number of decoded output signals decoded; And A word line which is enabled in response to each of the plurality of word line selection signals and drives the plurality of upper word lines and the plurality of lower word lines by inputting the predetermined number of upper and lower word line control signals A semiconductor memory device comprising a driver. The method of claim 1, wherein each of the plurality of memory cells A first transfer gate for transferring data between the bit line and the first node in response to a signal transmitted to the upper word line; A second transmission gate for transmitting data between the bit line and the second node in response to a signal transmitted to the lower word line; And And a latch connected between the first node and the second node to latch data. The method of claim 1, wherein the light / lead control means Enable the upper (lower) word line control signal in response to the input data of the first level in the write cycle and enable the lower (higher) word line control signal in response to the input data of the second level; And enabling the upper (or lower) word line control signal in the read cycle. The method of claim 3, wherein the light / lead control means A first non-logical gate for non-logically multiplying the input data and the write enable signal; A first logical gate for generating the upper (lower) control signal by ANDing the clock signal and the output signal of the first non-logical gate; A second logical gate for generating the lower control signal by performing an AND operation on the clock signal, the input data, and the write enable signal; A predetermined number of second non-logical gates for nonlogically multiplying each of the predetermined number of decoded signals and the upper control signal to generate the predetermined number of upper (lower) word line control signals; And And a predetermined number of third non-logical gates for non-logically multiplying each of the predetermined number of decoding signals and the lower control signal to generate the predetermined number of lower (upper) word line control signals. .