KR20020042924A - 4 mask patterning design method - Google Patents

4 mask patterning design method Download PDF

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KR20020042924A
KR20020042924A KR1020000072283A KR20000072283A KR20020042924A KR 20020042924 A KR20020042924 A KR 20020042924A KR 1020000072283 A KR1020000072283 A KR 1020000072283A KR 20000072283 A KR20000072283 A KR 20000072283A KR 20020042924 A KR20020042924 A KR 20020042924A
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South Korea
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difference
exposure part
mask
thin film
film transistor
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KR1020000072283A
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Korean (ko)
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최현묵
김억수
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주식회사 현대 디스플레이 테크놀로지
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Priority to KR1020000072283A priority Critical patent/KR20020042924A/en
Publication of KR20020042924A publication Critical patent/KR20020042924A/en

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    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333Constructional arrangements; Manufacturing methods
    • G02F1/1343Electrodes
    • G02F1/134309Electrodes characterised by their geometrical arrangement
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/1368Active matrix addressed cells in which the switching element is a three-electrode device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/786Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Abstract

PURPOSE: A four-mask patterning designing method is provided to make transmissivities in horizontal and vertical directions uniform by adjusting the slit size in a gray-tone area. CONSTITUTION: An active layer including an insulating layer and a layer for forming source and drain electrodes are sequentially formed on a glass substrate including a gate electrode. A photoresist is coated on the source and drain electrode layer, exposed using a mask having a full exposure part, non-exposure part and a partial exposure part, and developed, to accomplish a gray-tone pattern. The laminated layers are sequentially etched using the gray-tone pattern, to form a thin film transistor.

Description

4 마스크의 패터닝 디자인방법{4 MASK PATTERNING DESIGN METHOD}4 MASK PATTERNING DESIGN METHOD}

본 발명은 TFT-LCD 제작에 있어서 4 마스크의 패터닝 디자인방법에 관한 것으로, 보다 상세하게 TFT-LCD 제작에서 반도체 또는 FPD 등 포토 마스크를 이용하여 패터닝하는 4 마스크의 패터닝 디자인방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a patterning design method for four masks in TFT-LCD fabrication, and more particularly, to a patterning design method for four masks for patterning using photomasks such as semiconductor or FPD in TFT-LCD fabrication.

주지된 바와 같이, 현재 LCD-TFT 패널을 제조하는 데 있어서 생산단가를 낮추기 위하여 4 Mask(기존의 5∼7Mask) 기술개발에 있어서, 부분 노광부(GRAY-TONE AREA)를 패터닝하는 데 있어서 고전 TFT구조(일자형)를 이용하는 것이 가장 용이한 제조기술이나, 이러한 한계는 각 사의 TFT 특성을 향상하는 데 장애가 되고 있다.As is well known, high-definition TFT in the patterning of the GRAY-TONE AREA in the development of 4 Mask (traditional 5-7 Mask) technology in order to lower the production cost in manufacturing the LCD-TFT panel. It is the manufacturing technique which is easy to use the structure (straight type), but this limitation is an obstacle to improving the TFT characteristics of each company.

이를 극복하기 위하여 4 마스크(MASK) 제조기술의 개발이 활발하게 진행중이다. 상기한 4 마스크(MASK) 개발에서의 핵심기술은 기존의 비노광부와 노광부로 구분하여 패터닝하던 것을 부분 노광부(GRAY TONE AREA)를 만들어 ONE MASK로 동시에 두가지 패턴을 형성하는 것으로써, 현재 5 마스크(MASK)공정의 ACTIVE LAYER와 소스/드레인 레이어(SOURCE/DRAIN LAYER)를 동시에 형성하는 기술이 개발되어지고 있다.In order to overcome this problem, the development of 4 mask manufacturing technology is actively underway. The core technology in the development of the four masks is to divide the existing non-exposure part and the exposure part by patterning to make a partial exposure part (GRAY TONE AREA) to form two patterns simultaneously with the ONE MASK. A technique for simultaneously forming an active LAYER and a source / drain layer of a (MASK) process has been developed.

이러한 기술을 위해서는 특수한 마스크(MASK)제조가 필수적이며, 이를 위하여 반투과막을 이용하는 방법과, 노광장비의 해상도이하의 슬릿패턴(SLIT PATTERN)을 다수개 삽입하는 방법이 있으나, 전자의 경우 마스크(MASK) 제작에 많은 설비투자와 공정수를 요구하게 되므로 제조비용이 상승되는 문제가 있다.For this technology, the manufacture of a special mask is essential. For this purpose, there is a method of using a transflective film and a method of inserting a plurality of slit patterns below the resolution of an exposure apparatus. ) It requires a lot of equipment investment and the number of processes for manufacturing, there is a problem that the manufacturing cost is increased.

따라서, 노광장비의 해상도이하의 슬릿패턴(SLIT PATTERN)을 다수개 삽입하는 방법이 일반화되어 있다. 그러나 상기한 슬릿패턴(SLIT PATTERN)을 다수개 삽입하는 방법도 부분 노광지역의 포토레지스트 두께의 균일성을 조절하는 것이 문제가 되는 바, 그 두께의 균일도에 따라서 박막트랜지스터 채널(TFT-CHANNEL)의 길이가 결정되고 결국 패널(PANEL)의 전기적인 특성을 좌우하기 때문이다.Accordingly, a method of inserting a plurality of slit patterns (SLIT PATTERN) of less than or equal to the resolution of an exposure apparatus is common. However, in the method of inserting a plurality of slit patterns described above, it is a problem to control the uniformity of the photoresist thickness in the partial exposure area, and according to the uniformity of the thickness of the thin film transistor channel TFT-CHANNEL This is because the length is determined and ultimately determines the electrical characteristics of the panel.

도 1a, 1b, 1c는 종래의 4 마스크에 사용된 TFT 구조를 나타낸 도면이며, 도 2는 일반적인 노광장비로 인한 패터닝시의 수평, 수직방향의 해상도 변화를 나타내는 도면이다.1A, 1B, and 1C are diagrams illustrating a TFT structure used in a conventional four mask, and FIG. 2 is a diagram illustrating a change in resolution in horizontal and vertical directions during patterning due to general exposure equipment.

상기한 관점에 있어서 현재 개발중인 TFT 구조는 고전적(NORMAL)타입인 일자형 타입이 주종으로 되어 있다. 한편, 현재 5 마스크(MASK)에서 사용중인 슬릿 바(2, 4, 6)가 L.U 등의 구조로 이루어진 상기 슬릿 바(2, 4, 6)를 패터닝하는 데 있어서 가장 큰 문제점은 단일의 박막트랜지스터의 패턴내에서의 부분적 광투의 분포가 균일하지 못하다는 점인 바, 이러한 문제점 중의 하나가 도 2에 도시된 바와 같이 노광장비의 렌즈(10) 특성상 레티클(Reticle: 8)로부터의 투과광의 수직 및 수평방향의 광경로차가 각기 상이하므로 같은 디자인일 경우 그 투과율에 차이가 발생되어 결과적으로 TFT 채널의 치수(CD) 불균일성에 의한 문제가 초래된다.In view of the above, the TFT structure currently being developed is mainly a straight type which is a NORMAL type. On the other hand, the biggest problem in patterning the slit bars (2, 4, 6) made of a structure such as LU is the slit bar (2, 4, 6) currently used in the five mask (MASK) is a single thin film transistor The distribution of the partial light transmission in the pattern of is not uniform, one of these problems is the vertical and horizontal of the transmitted light from the reticle (8) due to the characteristics of the lens 10 of the exposure equipment as shown in FIG. Since the optical path differences in the directions are different from each other, a difference occurs in the transmittance of the same design, resulting in a problem due to the nonuniformity (CD) of the TFT channel.

본 발명은 상기한 종래 기술의 사정을 감안하여 이루어진 것으로, 노광장비의 광경로차에 의한 투과율을 분석하고 이에 해당하는 차이를 TFT 마스크 디자인시 부분 노광부(GRAY-TONE AREA)에 들어가는 슬릿 사이즈(SLIT SIZE)를 조절하여 보상 설계함으로써 수직 및 수평방향의 투과율을 일정하게 되도록 한 4 마스크의 패터닝 디자인방법을 제공함에 그 목적이 있다.The present invention has been made in view of the above-described situation of the prior art, and analyzes the transmittance caused by the optical path difference of the exposure equipment, and the corresponding difference in the slit size (GRAY-TONE AREA) in the TFT mask design ( It is an object of the present invention to provide a method of designing a pattern of four masks in which the transmissive design in the vertical and horizontal directions is made constant by adjusting the SLIT SIZE).

도 1a, 1b, 1c는 종래의 4 마스크에 사용된 TFT 구조를 나타낸 도면,1A, 1B and 1C show a TFT structure used in a conventional four mask,

도 2는 일반적인 노광장비로 인한 패터닝시의 수평, 수직방향의 해상도 변화를 나타내는 도면,2 is a view showing a change in resolution in the horizontal and vertical direction during patterning due to a general exposure equipment,

도 3은 부분노광을 위한 기존의 설계를 도시한 도면,3 shows a conventional design for partial exposure;

도 4는 본 발명에 따른 부분노광을 위한 4 마스크의 패터닝 설계를 도시한 도면이다.4 shows the patterning design of four masks for partial exposure in accordance with the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

2, 4, 6:슬릿바, 8:레티클,2, 4, 6: slit bar, 8: reticle,

10:렌즈.10: Lens.

상기한 목적을 달성하기 위해, 본 발명의 바람직한 실시예에 따르면 LCD-박막트랜지스터 패널의 제조에 있어서, 게이트 전극이 형성된 글라스위에 절연층을 포함한 액티브 레이어(ACTIVE LAYER), 소스/드레인 전극재를 순차적으로 적층하는 단계와; 적층된 전극재의 상면에 포토레지스트를 코팅한 후에 완전노광부, 비노광부, 부분노광부를 갖는 마스크를 이용하여 노광하는 것과 현상함으로써 부분노광패턴(GRAY-TONE PATTERN)을 완성하는 단계와; 그 패턴을 이용하여 적층된 필름을 순차적으로 식각함으로써 박막트랜지스터를 형성하는 단계로 이루어진 것을 특징으로 하는 4 마스크의 패터닝 디자인방법이 제공된다.In order to achieve the above object, according to a preferred embodiment of the present invention, in the manufacture of an LCD-thin film transistor panel, the active layer (ACTIVE LAYER), the source / drain electrode material including an insulating layer on the glass on which the gate electrode is formed sequentially Laminating with; Coating a photoresist on the stacked electrode material and then exposing and developing the photoresist using a mask having a complete exposure part, a non-exposure part, and a partial exposure part to complete a GRAY-TONE PATTERN; The patterning design method of the four masks which consists of forming a thin film transistor by sequentially etching the laminated | multilayer film using the pattern is provided.

바람직하게, 상기 박막트랜지스터의 구조는 공정마진을 확보하기 위하여 U자형 또는 L자형의 서로 다른 방향(수직, 수평, 대각방향)의 구조를 갖는 것중 어느 하나인 것을 특징으로 한다.Preferably, the structure of the thin film transistor is characterized in that any one having a structure of different directions (vertical, horizontal, diagonal) of the U-shaped or L-shaped in order to secure a process margin.

보다 바람직하게, 서로 다른 방향의 부분노광부(TFT CHANNEL AREA)의 슬릿바 디자인(SLIT BAR DESIGN)을 서로 다르게 삽입함으로써 그 슬릿바의 차가 0.5㎛이내 인 것을 특징으로 한다.More preferably, the difference between the slit bars of the slit bar design of the TFT CHANNEL AREA in different directions is different from each other by 0.5 μm or less.

또한, 슬릿바 디자인의 차이는 방향성(광경로차)에 의한 차이를 투과율로 환산하여 그 투과율차가 20%이내인 것을 특징으로 한다.In addition, the difference in the slit bar design is characterized in that the transmittance difference is within 20% by converting the difference due to the directionality (optical path difference) into the transmittance.

이하, 본 발명에 대해 도면을 참조하여 상세하게 설명한다.EMBODIMENT OF THE INVENTION Hereinafter, this invention is demonstrated in detail with reference to drawings.

도 3에 도시된 바와 같이, X, Y 방향에 대하여 동일한 슬릿바(SLIT BAR: 6)의 사이즈를 디자인하였을 경우 각 방향에서는 균일한 그레이-톤 패턴(GRAY-TONE PATTERN)을 얻을 수 있었으나, X, Y의 평균두께의 차는 Y방향의 값이 0∼20% 작은 값을 얻었으며, 이 결과 파이널 채널(FINAL CHANNEL)의 치수는 0∼0.3㎛차를 나타내게 되었다.As shown in FIG. 3, when a size of the same slit bar (SLIT BAR) 6 was designed for the X and Y directions, a uniform gray-tone pattern (GRAY-TONE PATTERN) was obtained in each direction. , The difference in the average thickness of Y was obtained by the value of 0 to 20% smaller in the Y direction. As a result, the dimension of the final channel was 0 to 0.3 μm.

이것은 슬릿바(6) 사이즈(SLIT BAR SIZE: A)의 약 5% 변동치에 해당하는 것으로써, 본 발명에서는 Y방향(광경로차가 일반부에 비하여 심한 곳)으로 슬릿바 사이즈(SLIT BAR SIZE)를 A×(95%이하)로 설계(도 4에 도시됨)한다.This corresponds to about 5% fluctuation of the slit bar 6 size (SLIT BAR SIZE: A). In the present invention, the slit bar size (SLIT BAR SIZE) is adjusted in the Y direction (where the optical path difference is severe compared to the general part). Design as Ax (95% or less) (shown in FIG. 4).

즉, 서로 다른 방향의 부분노광부(TFT CHANNEL AREA)의 슬릿바 디자인(SLIT BAR DESIGN)을 서로 다르게 삽입함으로써 그 슬릿바의 차가 0.5㎛ 이내로 되게 한다.That is, by inserting the SLIT BAR DESIGN of the TFT CHANNEL AREA in different directions differently, the difference between the slit bars is within 0.5 μm.

또한, 슬릿바 디자인의 차이는 방향성(광경로차)에 의한 차이를 투과율로 환산하여 그 투과율차가 20% 이내로 되게 한다. 그러므로써, 상대적으로 투과율을 향상시키면 광 경로차 및 방향성에서 기인되는 차이를 보상해 줄 수 있다.Further, the difference in slit bar design causes the difference in directionality (light path difference) to be converted into transmittance so that the transmittance difference is within 20%. Therefore, relatively improving the transmittance can compensate for the difference caused by the optical path difference and the directionality.

상기한 구성의 본 발명의 일실시예에 따른 4 마스크의 패터닝 디자인방법의 기능과 작용을 첨부된 도면을 참조하여 상세하게 설명한다.With reference to the accompanying drawings will be described in detail the function and operation of the four mask patterning design method according to an embodiment of the present invention of the above configuration.

파이널 채널의 크기(CD)에 형성되는 동일한 슬릿바(SLIT BAR: 6)의 사이즈를 디자인하였을 경우 X, Y의 각 방향에서는 균일한 그레이-톤 패턴(GRAY-TONE PATTERN)을 얻을 수 있었으나, X, Y의 평균두께의 차는 Y방향의 값이 0∼20% 작은 값을 얻었으며, 이 결과 파이널 채널(FINAL CHANNEL)의 치수는 0∼0.3㎛차를 나타내게 되었다. 이것은 슬릿바(6) 사이즈(SLIT BAR SIZE: A)의 약 5% 변동치에 해당하는 것으로써, 본 발명에서는 이를 보상하기 위하여 Y방향(광경로차가 일반부에 비하여 심한 곳)으로 슬릿바 사이즈(SLIT BAR SIZE)를 A×(95%이하)로 설계한다.When the size of the same slit bar (SLIT BAR) 6 formed in the size of the final channel (CD) was designed, a uniform gray-tone pattern (GRAY-TONE PATTERN) was obtained in each of the X and Y directions. , The difference in the average thickness of Y was obtained by the value of 0 to 20% smaller in the Y direction. As a result, the dimension of the final channel was 0 to 0.3 μm. This corresponds to a change of about 5% of the slit bar 6 size (SLIT BAR SIZE: A), and in the present invention, in order to compensate for this, the slit bar size (SLIT in the light path difference is severe compared to the general part) in order to compensate for this. Design BAR SIZE) to A × (95% or less).

그러면, 상기 슬릿바(6) 사이즈의 변동이 보상됨으로써 상대적으로 투과율을 향상시키면 광 경로차 및 방향성에서 기인되는 차이를 보상해 줄 수 있다.Then, the variation in the size of the slit bar 6 is compensated for, thereby improving the transmittance, thereby compensating for the difference caused by the optical path difference and the directionality.

한편, 본 발명의 실시예에 따른 4 마스크의 패터닝 디자인방법은 단지 상기한 실시예에 한정되는 것이 아니라 그 기술적 요지를 이탈하지 않는 범위내에서 다양한 변경이 가능하다.Meanwhile, the method of designing a pattern of four masks according to an embodiment of the present invention is not limited to the above-described embodiment, but various modifications can be made without departing from the technical gist of the present invention.

상기한 바와 같이, 본 발명에 따른 4 마스크의 패터닝 디자인방법은 박막트랜지스터 어레이 패널(TFT ARRAY PANEL)을 4 마스크 PHOTO PROCESS를 이용하여 제조하는 방법으로 4 마스크의 장점인 제조비용을 절감할 수 있으며, 동시에 기존 4 마스크에 사용되는 박막트랜지스터(일자형)의 구조를 탈피하여 자유롭게 U자 및 L자형의 구조를 선택할 수 있고, 부분 노광지역(TFT CHANNEL AREA)간 방향성, 광경로차에 의해서 발생하는 채널의 치수차에 대한 보상이 가능하여 공정마진이 넓은 박막트랜지스터 구조의 선택 및 품질향상이 가능해진다.As described above, the method of designing a pattern of a four mask according to the present invention is a method of manufacturing a thin film transistor array panel (TFT ARRAY PANEL) using a four mask PHOTO PROCESS to reduce the manufacturing cost, which is an advantage of four masks. At the same time, it is possible to freely select the U- and L-shaped structures by removing the structure of the thin film transistor (straight-type) used in the existing four masks, and the channel generated by the directionality and the optical path difference between the TFT CHANNEL AREAs. Compensation for the dimensional difference enables the selection and quality improvement of thin film transistor structures with wide process margins.

Claims (4)

LCD-박막트랜지스터 패널의 제조에 있어서, 게이트 전극이 형성된 글라스위에 절연층을 포함한 액티브 레이어(ACTIVE LAYER), 소스/드레인 전극재를 순차적으로 적층하는 단계와;A method for manufacturing an LCD thin film transistor panel, comprising: sequentially stacking an active layer including an insulating layer and a source / drain electrode material on a glass on which a gate electrode is formed; 적층된 전극재의 상면에 포토레지스트를 코팅한 후에 완전노광부, 비노광부, 부분노광부를 갖는 마스크를 이용하여 노광하는 것과 현상함으로써 부분노광패턴(GRAY-TONE PATTERN)을 완성하는 단계와;Coating a photoresist on the stacked electrode material and then exposing and developing the photoresist using a mask having a complete exposure part, a non-exposure part, and a partial exposure part to complete a GRAY-TONE PATTERN; 그 패턴을 이용하여 적층된 필름을 순차적으로 식각함으로써 박막트랜지스터를 형성하는 단계로 이루어진 것을 특징으로 하는 4 마스크의 패터닝 디자인방법.And forming a thin film transistor by sequentially etching the laminated film using the pattern. 1항에 있어서, 상기 박막트랜지스터의 구조는 공정마진을 확보하기 위하여 U자형 또는 L자형의 서로 다른 방향(수직, 수평, 대각방향)의 구조를 갖는 것중 어느 하나인 것을 특징으로 하는 4 마스크의 패터닝 디자인방법.The patterning method of claim 1, wherein the thin film transistor has any one of U- and L-shaped structures having different directions (vertical, horizontal, and diagonal directions) in order to secure a process margin. Design method. 제 2항에 있어서, 서로 다른 방향의 부분노광부(TFT CHANNEL AREA)의 슬릿바 디자인(SLIT BAR DESIGN)을 서로 다르게 삽입함으로써 그 슬릿바의 차가 0.5㎛이내 인 것을 특징으로 하는 4 마스크의 패터닝 디자인방법.The patterning design method of 4 masks according to claim 2, wherein the slit bar difference is less than 0.5 占 퐉 by inserting the SLIT BAR DESIGNs of the TFT CHANNEL AREAs in different directions differently. . 제 3항에 있어서, 슬릿바 디자인의 차이는 방향성(광경로차)에 의한 차이를투과율로 환산하여 그 투과율차가 20%이내인 것을 특징으로 하는 4 마스크의 패터닝 디자인방법.The patterning design method of 4 masks according to claim 3, wherein the difference between the slit bar designs is that the difference in directionality (optical path difference) is converted into transmittance and the transmittance difference is within 20%.
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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498575B1 (en) * 2000-12-26 2005-07-01 호야 가부시키가이샤 Grayton mask
US7288790B2 (en) 2002-11-20 2007-10-30 Samsung Electronics Co., Ltd. Thin film transistor array panel and manufacturing method thereof
US7688417B2 (en) 2004-12-17 2010-03-30 Samsung Electronics Co., Ltd. Thin film transistor array panel and method for manufacturing the same
US8581312B2 (en) 2010-11-11 2013-11-12 Samsung Display Co., Ltd. Thin film transistor array panel and manufacturing method thereof

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100498575B1 (en) * 2000-12-26 2005-07-01 호야 가부시키가이샤 Grayton mask
US7288790B2 (en) 2002-11-20 2007-10-30 Samsung Electronics Co., Ltd. Thin film transistor array panel and manufacturing method thereof
US7358124B2 (en) 2002-11-20 2008-04-15 Samsung Electronics Co., Ltd. Thin film transistor array panel and manufacturing method thereof
US7884365B2 (en) 2002-11-20 2011-02-08 Samsung Electronic S Co., Ltd. Thin film transistor array panel and manufacturing method thereof
US7688417B2 (en) 2004-12-17 2010-03-30 Samsung Electronics Co., Ltd. Thin film transistor array panel and method for manufacturing the same
US7876412B2 (en) 2004-12-17 2011-01-25 Samsung Electronics Co., Ltd. Thin film transistor array panel and method for manufacturing the same
US8581312B2 (en) 2010-11-11 2013-11-12 Samsung Display Co., Ltd. Thin film transistor array panel and manufacturing method thereof
US9064756B2 (en) 2010-11-11 2015-06-23 Samsung Display Co., Ltd. Thin film transistor array panel and manufacturing method thereof

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