KR20020041511A - buffer phase lineup apparatus using DPRAM - Google Patents

Abstract

PURPOSE: A buffer phase arrangement apparatus using DPRAM(dual port RAM) is provided to arrange a reference clock and a data received at a reference frame pulse by embodying 16-level buffer using DPRAM. CONSTITUTION: A buffer phase arrangement apparatus includes a receiving retiming part(100), a first counter generator(110), DPRAM, a second counter generator(130), a selector(140), and a reference retiming part(150). The receiving retiming part(100) performs retiming process a received data with a clock signal. The first counter generator(110) generates 4-bit counter for write/address action to DPRAM by using a received frame pulse signal and a clock signal. DPRAM independently performs reading/writing action with a dual port. The second counter generator(130) generates 4-bit counter for read/address action on the DPRAM by using the reference clock signal and the reference frame pulse signal. The selector(140) selects a data of the DPRAM. The reference retiming part(150) performs retiming process 2:1 selected data with the reference clock signal.

Description

Buffer phase liner apparatus using DPRAM

The present invention relates to a 2.5Gbps synchronous optical transmission device. In particular, a buffer phase alignment using DPRAM to align received data in a reference clock and a reference frame pulse by implementing a 16-stage buffer using DPRAM (Dual Port Random Access Memory) Relates to a device.

FIG. 1 is a block diagram of a conventional phase aligning apparatus. As shown in FIG. 1, a 1: 2 demux control unit 11 generating an enable signal having 12 MHz and 25 MHz for demultiplexing, and 51 MHz data as 25 MHz data is shown. 25M 1,2 demux section 12 for demultiplexing, 12M 1: 2 demux section 13 for demultiplexing 25MHz data into 12MHz data, and selector section for selecting 2: 1 for demultiplexed 12MHz ( 14) a demux unit 10, a mux control unit 30 for generating an enable signal having 12 MHz and 25 MHz for multiplexing, and a 12M 2: 1 mux unit 22 for multiplexing 12 MHz data to 25 MHz; And a mux unit 20 including a 25M 2; 1 mux unit 23 for multiplexing 25 MHz data into 51 MHz data, and a transmission / reception unit 24 for retiming 51 MHz data by flip-flop. A description with reference to 2 to 4 as follows.

As shown in FIG. 2, after retiming the received 51 MHz data (shift 1), the data is once again hitted by the clock (clk) (shift 2), and at this time Demux 25 enable ) When the signal has a "high" component, the shift1 and shift2 data are clocked, and the 1: 2 demuxed 25MHz data1 and data2 are output.

The 25MHz data generated as described above is also applied to the 12MHz 1: 2 demux of 1: 2 demuxed data 1 and 1: 2 demuxed 25MHz data 2 in the same manner as shown in FIG. Like the mux structure, the shift data 11 and the shift data 22 are the same.

At this time, when the 12M enable is "high", when clocked to the 12M data 1, 2, 3, 4 comes out.

3, the 51M high speed data is demultiplexed into 12M low speed data, and the demultiplexed 12M data groups A and B are selected by the 2: 1 selector as shown in FIG.

By selecting data in the low speed stage as described above, the probability of error occurrence is reduced, and the 2: 1 selection data should be synchronized to the system clock. The reason for synchronizing with the system clock is that the received clock and the system clock are always the same. Because it cannot have a phase, it is easy to process the system clock by lowering to 12M low data with the received data and clock as described above.

When the 12M enable signal generated by the system clock and the frame pulse is low as 12 and 3M demuxed data 1, 2 and 3, 12M data 1 and 2 are obtained by hitting the system clock (muxed 25M data). First bit of 1, the first bit of muxed 25M data2), 12M data3,4 are brought to the system clock when the 12M enable signal is high (second bit of muxed 25M data1 <second bit of muxed 25M data2) ).

When the 25M enable signal is low, the muxed 25M data 1 and the muxed 25M data 2 of FIG. 4 are obtained by hitting the system clock with the muxed 25M data 1 (the first bit of the muxed 51M data). When the 25M enable signal is high, the muxed 25M data2 is hit by the system clock (the second bit of the muxed 51M data).

Through the above process, 12M low speed data is multiplexed into 51M high speed data, and the received data is synchronized with the system clock by retiming the multiplexed data back to the system clock.

As such, too much logic is required to implement a field program gate array (FPGA), and the power consumed is increased, thereby increasing the possibility of error.

In addition, the conventional phase aligner uses too many registers (flip-flops) as one clock, and the divided clock also uses too many registers, so the fanout of the clock when the temperature environment test of the optical transmission device is performed. This causes delays and can't ignore errors.

In addition, since it is a four-stage buffer, if the received flame pulse is more than four clocks apart from the reference flame pulse, phase alignment is prevented.

Accordingly, the present invention has been made in view of the above-described problems, and eliminates skew occurring during high-speed data transfer between boards and implements a 16-stage buffer using DPRAM to implement a reference clock and a reference frame. The purpose is to align the received data in pulses.

1 is a block diagram of a conventional phase alignment device.

2 is a structural diagram of a typical 25M 1: 2 demux.

3 is a structural diagram of a typical 12M 1: 2 demux.

4 is a structural diagram of a general mux.

5 is a configuration diagram of a phase alignment device applied to the present invention.

Figure 6 is a structural diagram of the diffraction applied to the present invention.

Fig. 7 is a timing diagram when using a diffiram applied to the present invention.

<Description of the symbols for the main parts of the drawings>

10: demux unit 11: demux control unit

12: 25M 1,2 Demux part 13: 12M 1: 2 Demux part

14: selector 20: mux

22: 12M 2: 1 musbu 23: 25M 2; 1 musbu

24: transmission and reception retiming unit 30: mux control unit

100: reception retiming unit 110: first counter generating unit

120: DPRAM 130: second counter generator

140: selector unit 150: reference retiming unit

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

An embodiment of the present invention buffer phase alignment device,

A reception retiming unit for retiming the received data into a clock signal;

A first counter generator for generating a 4-bit counter for writing / addressing to dual port random access memory (DPRAM) with the received flame pulse signal and a clock signal;

DPRAM, which has dual ports and can read and write independently simultaneously,

A second counter generator for generating a 4-bit counter to read / address the DPRAM using a reference clock signal and a reference frame pulse signal;

A selector unit for selecting data of the DPRAM;

Preferably, the reference clock signal includes a reference retiming unit for retiming data selected 2: 1.

The data received in the reference clock signal and the reference frame pulse signal may be aligned by implementing a 16-stage buffer of the DPRAM.

5 is a configuration diagram of a phase aligning device applied to the present invention, and as shown therein, a reception retiming unit 100 for retiming the received 51 MHz data to a received 51 MHz clock, and a received flame pulse and a clock. A first counter generator 110 for generating a 4-bit counter for write_address of the DPRAM, a DPRAM 120 capable of independently reading and writing simultaneously with a dual port, a reference clock (SYS_CLK) and a reference frame pulse ( SYS_FP), a second counter generator 130 for generating a 4-bit counter to read_address the DPRAM, a selector 140 for selecting data of the DPRAM, and 2: 1 for the reference clock SYS_CLK. It is composed of a reference retiming unit 150 for retiming the selected data, which will be described with reference to FIGS. 6 and 7 as follows.

Retime the received 51M data RX_DATA to the received clock RX_CLK, and generate a 4-bit counter with the received frame pulse RX_FP and RX_CLK, and the generated 16 counter is a dual port as shown in FIG. Port) It is input as the write_address value of RAM.

The received data is stored at the input address (write_address), and the data received according to the sequentially increasing address is also stored over time, and the write_address is repeatedly countered from 0 to 15.

When the data is used as above, 16 counter values are generated by the reference clock (SYS_CLK) and the reference frame pulse (SYS_FP), and this value is input to read_address of DPRAM, and by the input address. The read data value is the output.

Here, the initial read_address value is adjusted to start at address 8 of the write address of the DPRAM, which is read with sufficient time between the write time and the read time in the DPRAM.

Looking at this in terms of time is shown in Table 1.

Table 1

As described above, the data read through the DPRAM is phase aligned with the reference clock SYS_CLK and the reference frame pulse SYS_FP, and the data A group and the data B group read through the DPRAM are stored in the cell SEL signal. 2: 1 is selected, and once again, the reference clock (SYS_CLK) is retimed to synchronize with the reference clock.

As shown in FIG. 7, skew refers to a phenomenon in which each data is slightly out of phase with each other when 48 pieces of data are received. If this skew is severe, data received by a reference clock cannot be read correctly.

This eliminates the skew that occurs when data is transferred between boards in a 2.5 Gbps synchronous optical transmitter and transfers 48 received 51.84 Mbps data with this skew to the reference frame pulse (SYS_FP) and reference clock (SYS_CLK) signals. The phases are aligned and synchronized.

As described above, according to the present invention, the clock used in the register uses only the retiming portion and the address generating portion, so that the fan out of the clock does not occur during the temperature environment test. The 48 channels of received data can be aligned to the reference clock and reference flame pulses until the impulse and reference flame pulses differ by 16 clocks.

Claims (2)

A reception retiming unit for retiming the received data into a clock signal; A first counter generator for generating a 4-bit counter for writing / addressing to dual port random access memory (DPRAM) with the received flame pulse signal and a clock signal; DPRAM, which has dual ports and can read and write independently simultaneously, A second counter generator for generating a 4-bit counter to read / address the DPRAM using a reference clock signal and a reference frame pulse signal; A selector unit for selecting data of the DPRAM; And a reference retiming unit configured to retime the 2: 1 data selected by the reference clock signal. The buffer phase alignment device of claim 1, wherein the data received in the reference clock signal and the reference frame pulse signal are aligned by implementing a 16-stage buffer of the DPRAM.