KR20020040981A - Circuit for protecting write error of memory - Google Patents

Abstract

PURPOSE: A circuit for preventing the writing error of a memory is provided to prevent the unexpected unit setting in advance by lowering the supply voltage of the memory in case of error. CONSTITUTION: The circuit is composed of the first, second, third, and fourth resistance(R1,R2,R3,R4), an operation amplifier(400), an inductor(L1), and a capacitor(C1). The operation amplifier is impressed the five-voltage power in non-inverting terminal(+) through the first resistance, and done a control signal(Vi) in inverting terminal(-) through the third resistance. The second resistance connects the earth with the non-inverting terminal of the operation amplifier and the fourth resistance connects the operation amplifier output with the inverting terminal of the operation amplifier. A low pass filter(410), composed of the inductor and the capacitor, removes a ripple mixed to an output signal of the operation amplifier and supplies to a memory. In conclusion, as the operation voltage of the memory gets under the regular voltage, the command is not valid. That is why prevents the data from being written to the memory.

Description

CIRCUIT FOR PROTECTING WRITE ERROR OF MEMORY}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a write error prevention circuit of a memory storing supplying data, and more particularly to a circuit for preventing a write error of a memory by controlling a supply voltage of the memory using a digital signal.

1 shows a connection relationship between a conventional memory controller and a memory.

Referring to FIG. 1, the memory controller 110 may include a memory E2PROM (Electrically Erasable and Programmable Read Only Memory 120) through a memory address bus E2PROM_ADDRESS_BUS [12: 0] and a memory data bus E2PROM_DATA_BUS [7: 0]. Connected with The memory controller 110 controls the memory 120 connected through the memory control signals E2PROM_CE, E2PROM_OE, and E2PROM_WE.

2 is a structural diagram of a conventional address map, which is divided into a memory data backup area and a memory data area in the memory controller.

Referring to FIG. 2, the memory controller 110 reads data in a memory area and stores the data therein, so that the area has a different address from that of the memory itself. If the main controller 100 writes wrong data in the memory 120 when the unit total address map includes the memory address area, the fact is not known.

3 is a diagram illustrating a control relationship between a conventional main controller, a memory controller, and a memory.

1 to 3, in the conventional apparatus, the unit UNIT is set by the main controller 100 at the first setting. Here, the main controller 100 performs a method of setting the unit directly or automatically reading data from the memory 120. The main controller 100 directly writes data to the internal memory area of the memory controller 110 and writes data to the memory 120 through the memory controller 110. The memory controller 110 reads data of the memory 120 by the main controller 100 or reads itself when an abnormality occurs in the main controller 100. However, when the main controller 100 fails, the memory controller 110 automatically reads data of the memory 120 and sets the unit within the unit. That is, when an abnormality of the main controller 100 occurs, the unit reads the data of the memory 120 again and sets the unit. Here, when the main controller 100 has an abnormality, the data of the memory 120 is read again because an error of the main controller 100 itself and the main controller 100 cannot be distinguished from each other. Then, the unit cannot set the desired setting due to an incorrect write command of the master controller 100.

As such, the conventional memory controller 110 reads data from the memory 120 and resets the unit when an incorrect write command is transmitted from the main controller 100, and thus the default setting state of the unit is changed. Since there is a problem that can change the service is wrong.

Accordingly, an object of the present invention is to provide a circuit for preventing a write error of a memory in order to solve a problem caused when an incorrect write command comes to the memory due to an abnormal controller.

1 is a diagram illustrating a connection relationship between a conventional memory controller and a memory.

2 shows a conventional address map;

3 is a diagram illustrating a control relationship between a conventional main controller, a memory controller, and a memory;

4 is a block diagram of a memory write error prevention circuit according to the present invention;

The present invention for achieving this object is characterized by lowering the operating voltage supplied to the memory below a certain voltage in order to prevent the wrong data is written to the memory after the unit configuration is completed.

In the present invention, the operating power is applied to the non-inverting terminal through the first resistor, the control signal is applied to the inverting terminal through the third resistor, and the second resistor connected to the ground is connected to the non-inverting terminal. A resistor is connected between the inverting terminal and the output and implemented as an op amp that outputs an operating voltage supplied to the memory. The present invention further includes a low pass filter for removing ripples mixed in the output of the off amplifier.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

4 is a block diagram of a circuit for preventing a write error of a memory according to an exemplary embodiment of the present invention, and includes first to fourth resistors R1, R2, R3, and R4, an op amp 400, an inductor L1, and a capacitor ( C1).

Referring to FIG. 4, an OP-AMP (OP-AMP) 400 receives a 5 V power supply through a first resistor R1 to a non-inverting terminal (+) and a memory controller through a third resistor R3. The control signal Vi is applied to the inverting terminal (−) from 110. The second resistor (R2) is connected to the non-inverting terminal (+) of the op amp 400 and the ground, the fourth resistor (R4) of the inverting terminal (-) and the op amp 400 of the op amp 400 Connect the output.

The low pass filter 410 is implemented as an inductor L1 and a capacitor C1, and removes ripples mixed in a signal output from the op amp 400 to the memory 120. do.

The voltage E2PROM_VCC supplied to the memory by the write error protection circuit of the memory according to the embodiment of the present invention is represented by Equation 1 below.

Where R4 = (2/3) x R3 and R2 = (3/2) x R1,

E2PROM_VCC = 5-(2/3) x Vi.

First, the memory controller 110 applies the control signal Vi of the low state (0V) to the op amp 400 while the unit configuration is made. Then, the operational amplifier 400 supplies an operating voltage E2PROM_VCC of 5V to the memory 120. Therefore, the memory 120 is in a state where normal operation is possible.

In contrast, the memory controller 110 applies a control signal Vi of a high state to the op amp 400 after a unit configuration is completed. Then, when the op amp 400 receives the control signal Vi in the high state (3.3V), the op amp 400 supplies the operating voltage E2PROM_VCC of about 3V to the memory 120. Therefore, since the memory 120 does not perform any operation on the command transmitted as the supplied operating voltage becomes lower than or equal to the predetermined voltage, data may be prevented from being written to the memory 120.

As described above, the present invention controls the operation power supply of the memory to prevent the write error of the memory. Therefore, the present invention can prevent setting of a unit different from the one intended by preventing data from being written incorrectly in the memory when an abnormality occurs in the main controller when the unit is to be set by reading the data in the memory.

Claims (3)

In the write error prevention circuit of the memory, The operating power is applied to the non-inverting terminal through the first resistor, the control signal is applied to the inverting terminal through the third resistor, and the second resistor connected to the ground is connected to the non-inverting terminal, and the fourth resistor is applied to the non-inverting terminal. And an op amp connected between the inverting terminal and the output and outputting an operating voltage of the memory supplied to the memory. The method of claim 1, And a low pass filter implemented by an inductor and a capacitor to remove ripples mixed in the output of the op amp. The method of claim 1, wherein the op amp, And a control signal from a memory controller controlling the memory after the configuration of the unit is completed, thereby lowering an operating voltage supplied to the memory to a predetermined voltage or less.