KR20020039210A - Memory device having exterior delay control mechanism for adjusting internal clock of data processing and memory module including the same - Google Patents

Abstract

PURPOSE: A semiconductor memory device is provided whose data delay time is controlled from the external, and a memory module comprising the same is provided which reduces a skew. CONSTITUTION: The synchronous semiconductor memory device(10) comprises a clock buffer(12), a command signal/address buffer(11), a memory cell array(13) and a data input/output circuit. The data input/output circuit comprises a data input buffer(15) and a data output buffer(17). The semiconductor memory device is connected to an external delay circuit(19) through an additional pin. The clock buffer generates the first internal clock(PCLK1) and the second internal clock(PCLK2) by being synchronized to a system clock(CLK). The command signal/address buffer latches a command signal/address(CMD/ADD) from a memory controller and outputs the CMD/ADD to the memory cell array. The delay circuit is installed on the memory module and generates the third internal clock(PCLK3) by delaying the second internal clock in response to the second internal clock.

Description

Memory device having an external delay control mechanism for adjusting internal clock of data processing and memory module including the same}

The present invention relates to a semiconductor memory device, and more particularly, to a synchronous semiconductor memory device capable of adjusting a data delay time outside of a semiconductor memory device and a memory module having the same.

In general, a synchronous semiconductor memory device operates in synchronization with a clock generated by a transition of a system clock.

That is, in the synchronous semiconductor memory device, all operations of the synchronous semiconductor memory device, such as a command signal and an address, write data, and read data, are referred to as an external clock (or system clock). Is motivated by.)

1 is a block diagram of a conventional synchronous semiconductor memory device having a fixed data delay time. The data delay time (hereinafter, referred to as a data delay time) refers to a time delay until the synchronous semiconductor memory device receives a command signal CMD / address ADD from a memory controller and inputs / outputs data. . Referring to FIG. 1, a synchronous semiconductor memory device 1 includes a clock buffer 2, a command signal / address buffer 3, a memory cell array 5, a data input buffer 7 and a data output buffer 9. Equipped.

The clock buffer 2 outputs a plurality of internal clock signals having different predetermined pulse widths in response to the input external clock CLK. The clock buffer 2 of FIG. 1 is a first internal clock signal PCLK1 having a predetermined pulse width and synchronized with the external clock CLK for convenience of description, and having a predetermined pulse width. 2 shows an internal clock signal PCLK2.

When writing data to the synchronous semiconductor memory device 1, the command signal / address buffer 3 is generated from a memory controller (not shown) in synchronization with the first internal clock PCLK1. And a command signal CMD, and the data input buffer 7 writes the data WDT to the memory cell array 5 in synchronization with the second internal clock PCLK2.

In addition, when reading data from the synchronous semiconductor memory device 1, the command signal / address buffer 3 is synchronized with the first internal clock signal PCLK1 and the address ADD generated from the memory controller and The command signal CMD is received, and the data output buffer 9 outputs data RDT from the memory cell array 5 in synchronization with the second internal clock PCLK2.

Although the data delay time of the conventional synchronous semiconductor memory device can be changed in a very limited manner by adjusting the setup, all operations of the synchronous semiconductor memory device are performed in synchronization with the external clock CLK, and the synchronous semiconductor memory Since the data delay time of the device is fixed inside the chip, the data delay time cannot be adjusted outside of the synchronous semiconductor memory device.

FIG. 8 is a block diagram illustrating a memory module including a semiconductor memory device having a conventional fixed data delay time and an output timing of data. Referring to FIG. 8, the memory module 50 includes a plurality of semiconductor memory devices 51, 53, 55, and 57, a first bus 52, and a second bus 54.

The address ADD / command signal CMD / system clock CLK / first system clock CLK1 / second system clock CLK2 are connected to the semiconductor memory devices 51 and 53 through the first bus 52. 55 and 57, and the second bus inputs and outputs data in parallel to the semiconductor memory devices 51, 53, 55, and 57 as data input / output buses.

Referring to FIG. 8, due to the structure of the first bus 52, the semiconductor memory device 53 has a time of? T after the semiconductor memory device 51 and the semiconductor memory device 55 has a? T time of the semiconductor memory device 51. After a time, assuming that a read command is transferred to the semiconductor memory device 57 after 3Δt of time than the semiconductor memory device 51, each of the semiconductor memory devices 51, 53, 55, and 57 has a read command. In response, it sends out data after a fixed time (column address strobe latency).

Therefore, the semiconductor memory device 53 is Δt after the semiconductor memory device 51, and the semiconductor memory device 55 is 2 Δt after the semiconductor memory device 51, and the semiconductor memory device 57 is the semiconductor memory device ( The data read out after the time of 3Δt from 51) is output to the second bus 54. Therefore, there is a problem that skew occurs because there is a time difference of up to 3Δt between data read out of the semiconductor memory device 51 of the conventional memory module and data read out of the semiconductor memory device 57.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a synchronous semiconductor memory device configured on an external memory module to freely control a data delay time and a memory module capable of reducing skew by providing the synchronous semiconductor memory device. .

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a block diagram of a conventional synchronous semiconductor memory device having a fixed data delay time.

2 is a block diagram of a synchronous semiconductor memory device capable of adjusting a data delay time on an external memory module according to an embodiment of the present invention.

3 is a block diagram of a synchronous semiconductor memory device capable of adjusting a data delay time on an external memory module according to another exemplary embodiment of the present invention.

4 is a block diagram of a synchronous semiconductor memory device capable of adjusting a data delay time on an external memory module according to another embodiment of the present invention.

5 is a block diagram of a synchronous semiconductor memory device capable of adjusting a data delay time on an external memory module according to another embodiment of the present invention.

6 is a block diagram of a synchronous semiconductor memory device capable of controlling a data delay time using an external control pin according to another embodiment of the present invention.

7 is a block diagram of a synchronous semiconductor memory device capable of adjusting a data delay time on an external memory module according to another embodiment of the present invention.

FIG. 8 is a block diagram illustrating a memory module including a synchronous semiconductor memory device having a fixed data delay time in the related art, and an output timing of data.

FIG. 9 is a block diagram illustrating a memory module including a synchronous semiconductor memory device capable of adjusting a data delay time on an external memory module according to an exemplary embodiment of the present invention, and illustrating output timing of data.

In order to achieve the above technical problem, a semiconductor memory device according to a first embodiment of the present invention includes a buffer, a data input / output circuit, and a delay circuit. The buffer receives an address and a command signal in response to a first internal clock synchronized with an external clock, and the input / output circuit is configured to delay a second internal clock synchronized with the external clock by a predetermined time through the delay circuit. 3 Synchronizes with the internal clock to input and output data to / from memory cells of the memory cell array.

Preferably, the delay circuit is configured on a memory module external to the semiconductor memory device to control the delay.

A memory device according to a second embodiment of the present invention includes a buffer, a data input / output circuit and a delay circuit. The buffer receives an address and a command signal in response to the first internal clock synchronized with the first external clock, and the input / output circuit delays the second internal clock synchronized with the second external clock for a predetermined time through a delay circuit. Synchronizes with the third internal clock to input / output data to / from the memory cells of the memory cell array. Preferably, the frequency of the second internal clock is higher than the frequency of the first internal clock, and the delay circuit is configured on a memory module external to the semiconductor memory device to control the delay.

A memory device according to a third embodiment of the present invention includes a frequency divider circuit, a buffer, a data input / output circuit, and a delay circuit. The division circuit divides a first internal clock synchronized with an external clock, the buffer buffers an address and a command signal in synchronization with an output signal of the division circuit, and the data input / output circuit is synchronized with the external clock. The second internal clock is delayed by a predetermined time through the delay circuit, and data is input and output to / from the memory cells of the memory cell array in synchronization with the third internal clock. Preferably, the frequency of the output clock of the frequency divider circuit is lower than the frequency of the third internal clock, and the delay circuit is configured on a memory module external to the semiconductor memory device to control the delay.

Preferably, the delay circuit in any one of the first to third embodiments is a transmission line or an RC circuit.

A memory device according to a fourth embodiment of the present invention includes a buffer, a delay synchronization loop, a delay circuit, and a data input / output circuit. The buffer receives an address and a command signal in response to a first internal clock synchronized with the external clock, and the delay synchronization loop generates a third internal clock that is phase locked to a second internal clock synchronized with the external clock. And the delay circuit delays the output signal for a predetermined time in response to the output signal of the delay synchronization loop and feeds it back to the input of the delay synchronization loop, and the data input / output circuit is synchronized with the third internal clock. Input and output data to and from memory cells. Preferably, the delay circuit is a capacitor, configured on a memory module external to the semiconductor memory device to control the delay.

A memory device according to a fifth embodiment of the present invention includes a plurality of delay circuits, a demultiplexer, and a data input / output circuit. The plurality of delay circuits delay the input signal differently for a predetermined time to generate a first internal clock synchronized with the external clock, and the demultiplexer delays the second internal clock synchronized with the external clock in response to an external control signal. Outputs an input signal to circuits, and the data input / output circuit inputs and outputs data to / from memory cells of a memory cell array in synchronization with the first internal clock, and preferably, the external control signal is controlled outside of the semiconductor memory device. do.

A memory device according to a sixth embodiment of the present invention includes a plurality of delay circuits, a multiplexer, and a data input / output circuit. The plurality of delay circuits delay the first internal clock synchronized with an external clock differently from each other for a predetermined time, and the multiplexer selects one of the output signals of the delay circuits in response to an external control signal to synchronize with the external clock. Outputs to and from an internal clock, and the data input / output circuit outputs data to / from a memory cell of a memory cell array in synchronization with the second internal clock, and preferably, the external control signal is controlled outside of the semiconductor memory device. do.

The memory module according to the present invention includes a first bus, a second bus, and a semiconductor memory device. The memory module includes a plurality of semiconductor memory devices packaged on a printed circuit board, and the first bus supplies first and second external clocks, address and command signals to the semiconductor memory devices. The second bus is a bus for inputting and outputting data in parallel to the plurality of semiconductor memory devices. Preferably, each of the plurality of semiconductor memory devices may be at least one of the semiconductor memory devices according to the first to sixth embodiments.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements.

2 is a block diagram of a synchronous semiconductor memory device capable of adjusting a data delay time according to a first embodiment of the present invention on a memory module external to the memory chip. The data delay time is measured until the synchronous semiconductor memory device receives a command signal (hereinafter referred to as CMD) and an address (hereinafter referred to as ADD) from the memory controller, that is, CMD / ADD and receives data. It's time.

Referring to FIG. 2, the synchronous semiconductor memory device 10 includes a clock buffer 12, a command signal / address buffer 11, a memory cell array 13, and a data input / output circuit, wherein the data input / output circuit is a data input circuit. A buffer 15 and a data output buffer 17 are provided.

In addition, the semiconductor memory device 10 may be connected to a delay circuit 19 external to the semiconductor memory device 10. That is, the semiconductor memory device 10 may be provided with an additional pin for connecting to the delay circuit 19.

The clock buffer 12 has a predetermined pulse in synchronization with the system clock CLK and the first internal clock PCLK1 having a predetermined pulse width in synchronization with the system clock CLK input from the outside of the semiconductor memory device 10. A second internal clock PCLK2 having a width is generated.

The command signal / address buffer 11 receives and latches CMD / ADD from a memory controller (not shown) and outputs the latched CMD / ADD to the memory cell array 13 in synchronization with the system clock CLK. .

The delay circuit 19 may be mounted on a memory module on which the semiconductor memory device 10 is mounted, and delays the second internal clock PCLK2 for a predetermined time in response to the second internal clock PCLK2 (hereinafter, referred to as a “delay time”). The third internal clock PCLK3 is generated. The third internal clock PCLK3 is defined as related to data input / output.

The delay circuit 19 may have a transmission line of a predetermined length for delaying the system clock CLK for a predetermined time or an RC circuit for delaying the phase of the system clock CLK.

Therefore, the delay may be controlled by a transmission line or an RC circuit configured and connected to the memory module on which the semiconductor memory device 10 is mounted. That is, the data delay time may be configured and controlled on the memory module outside the semiconductor memory device.

The data input buffer 15 receives the data WDT in response to toggling of the third internal clock PCLK3 to latch the received data WDT, and latches the received data WDT. 15).

The data output buffer 17 latches the data RDT read from the memory cell array 13 and outputs the latched data RDT to the external bus in response to the third internal clock PCLK3.

Referring to FIG. 2, a write data operation is written to the synchronous semiconductor memory device 10, and the semiconductor memory device 10 is synchronized with the first internal clock PCLK1 to write CMD / ADD, that is, write. Receive the command signal WRITE COMMAND. The synchronous memory device 10 receives the data WDT from the external bus (not shown) into the data input buffer 15 in synchronization with the third internal clock PCLK3 and stores the data WDT in the memory cell array 13.

Next, an operation of reading data from the synchronous semiconductor memory device 10 will be described. The synchronous semiconductor memory device 10 synchronizes with the first internal clock PCLK1 to perform CMD / ADD, that is, a read command signal READ COMMAND. Receive The synchronous semiconductor memory device 10 outputs the data RDT read from the memory cell array 15 to the outside of the semiconductor memory device 10 in synchronization with the third internal clock PCLK3.

Therefore, since the third internal clock PCLK3 related to data input / output can be delayed than the first clock PCLK1 related to CMD / ADD, the data delay time can be increased. That is, since the third internal clock PCLK3 can be controlled using the delay circuit 19, the data delay time can also be controlled from the outside of the semiconductor memory device 10.

3 is a block diagram of a synchronous semiconductor memory device capable of controlling a data delay time according to a second embodiment of the present invention on an external memory module. Referring to FIG. 3, the semiconductor memory device 10 includes a command signal / address buffer 11, a first clock buffer, a second clock buffer, a memory cell array 13, and a data input / output circuit. The data input / output circuit includes a data input buffer 15 and a data output buffer 17.

In addition, the semiconductor memory device 10 may be connected to a delay circuit 19 external to the semiconductor memory device 10. That is, the semiconductor memory device 10 may be provided with an additional pin for connecting to the delay circuit 19.

The first clock buffer 12 outputs the first internal clock PCLK1 having a predetermined pulse width synchronized with the first system clock CLK1 input from the outside, and the second clock buffer 14 is input from the outside. The second internal clock PCLK2 having a predetermined pulse width synchronized with the second system clock CLK1 is output.

The command signal / address buffer 11 receives and latches CMD / ADD in synchronization with the first internal clock PCLK1 from a memory controller (not shown), and latches the latched CMD / ADD in the memory cell array 13. Will output

The delay circuit 19 may be mounted on a memory module in which the semiconductor memory device 10 is mounted, and the third internal clock (the third internal clock PCLK2 delaying the second internal clock PCLK2 for a predetermined time in response to the second internal clock PCLK2). PCLK3) is output.

The third internal clock PCLK3 used for input / output of data is preferably higher than the frequency of the first internal clock PCLK1.

Since the configuration of the delay circuit 19 and the data input / output process of the semiconductor memory device 10 due to the delay circuit 19 are the same as those described with reference to FIG. 2, detailed descriptions thereof will be omitted.

4 is a block diagram of a semiconductor memory device capable of adjusting a data delay time according to a third embodiment of the present invention on an external memory module. Referring to FIG. 4, the semiconductor memory device 10 includes a clock buffer 12, a frequency divider 14, a command signal / address buffer 11, a memory cell 13, and a data input / output circuit. The data input / output circuit includes a data input buffer 15 and a data output buffer.

The clock buffer 12 has a first internal clock signal PCLK1 having a predetermined pulse width synchronized with the system clock CLK input from the outside and a second internal having a predetermined pulse width synchronized with the system clock CLK. Output the clock signal PCLK2. The clock buffer 12 may generate a plurality of internal clock signals that are synchronized with the system clock CLK and have different predetermined pulse widths.

The frequency division circuit 14 divides the frequency into the third internal clock having a frequency lower than the frequency of the first internal clock PCLK1 in response to the first internal clock PCLK1.

The command signal / address buffer 11 outputs CMD / ADD to the memory cell array 13 in synchronization with the third internal clock PCLK3. The delay circuit 19 may be mounted on a memory module in which the semiconductor memory device 10 is mounted, and delay the second internal clock PCLK2 by a predetermined time in response to the second internal clock PCLK2. 4 Generate internal clock (PCLK4).

In addition, the semiconductor memory device 10 may be connected to a delay circuit 19 external to the semiconductor memory device 10. That is, the semiconductor memory device 10 may be provided with an additional pin for connecting to the delay circuit 19.

The frequency of the fourth internal clock PCLK4 used for the input / output of data is preferably higher than the frequency of the third internal clock PCL3.

Since the configuration of the delay circuit 19 and the data input / output process of the semiconductor memory device 10 due to the delay circuit 19 are similar to those described with reference to FIG. 2, a detailed description thereof will be omitted.

5 is a block diagram of a synchronous semiconductor memory device capable of controlling and controlling a data delay time according to a fourth embodiment of the present invention on an external memory module. The semiconductor memory device 20 of FIG. 5 includes a clock buffer 22, a command signal / address buffer 21, a memory cell array 23, a phase locked loop 29, and a data input / output circuit. The data input / output circuit includes a data input buffer 25 and a data output buffer 27.

In addition, the semiconductor memory device 20 may be connected to a delay circuit C configured outside the semiconductor memory device 20. That is, the semiconductor memory device 20 may be provided with an additional pin for connecting to the delay circuit (C). Delay circuit (c) may be composed of a capacitor.

The clock buffer 22 has a first internal clock signal PCLK1 having a predetermined pulse width synchronized with the system clock CLK input from the outside and a second internal having a predetermined pulse width synchronized with the system clock CLK. Output the clock signal PCLK2. The clock buffer 22 may generate a plurality of internal clock signals that are synchronized with the system clock CLK and have different predetermined pulse widths.

The command signal / address buffer 21 outputs CMD / ADD to the memory cell array 23 in synchronization with the first internal clock PCLK1.

The DLL (delay locked loop) 29 uses a negative feedback of the phase so that the phase difference between the second internal clock PCLK2 which is an input signal of the DLL 29 and the third internal clock PCLK3 fed back is decrease or increase the phase difference or zero. The DLL 29 is well known to those skilled in the art, and thus a detailed description thereof will be omitted.

Referring to FIG. 5, the negative feedback loop of the DLL 29 includes a terminal A that may be connected on a memory module external to the semiconductor memory device 20. The variable capacitive load C can be connected via the terminal A. FIG. Therefore, the phase of the feedback third internal clock PCLK3 may be controlled by the variable capacitive load C.

Referring to FIG. 5, the operation of writing data to the semiconductor memory device 20 will be described. The semiconductor memory device 20 receives a CMD / ADD, that is, a write command signal in synchronization with the first internal clock PCLK1.

The DLL 29 of the semiconductor memory device 20 has a third internal clock delaying the second internal clock PCLK2 by a predetermined time in response to the second internal clock PCLK2 through the variable capacitance C connected to the negative feedback loop. (PCLK3) is generated. Therefore, the semiconductor memory device 20 latches the data WDT from the external bus in synchronization with the third internal clock PCLK3 and stores the data WDT in the memory cell array 13.

Next, the operation of reading data from the semiconductor memory device 20 will be described. The semiconductor memory device 20 receives a CMD / ADD, that is, a read command signal in synchronization with the first internal clock PCLk1.

The DLL 29 of the semiconductor memory device 20 generates a third internal clock PCLk3 delaying the second internal clock PCLK2 by a predetermined time in response to the second internal clock through a variable capacitance connected to the negative feedback loop. . The semiconductor memory device 20 outputs the data RDT read from the memory cell array 15 to the external bus in synchronization with the third internal clock PCLK3 delayed by the variable capacitor C. FIG.

Therefore, the data delay time of the semiconductor memory device 20 can be freely adjusted by configuring it on the external memory module of the semiconductor memory device 20 through the control of the variable capacitive load C on the memory module.

6 is a block diagram of a synchronous semiconductor memory device capable of externally controlling a data delay time through an external pin of a semiconductor memory device according to a fifth embodiment of the present invention.

Referring to FIG. 6, the semiconductor memory device 30 includes a clock buffer 32, a command signal / address buffer 31, a memory cell array 33, a demultiplexer 39, a plurality of delay circuits 41 and 43, and A data input / output circuit is provided, and the data input / output circuit includes a data input buffer 35 and a data output buffer 37.

The clock buffer 32 has a first internal clock signal PCLK1 having a predetermined pulse width synchronized with the system clock CLK input from the outside and a second internal having a predetermined pulse width synchronized with the system clock CLK. Output the clock signal PCLK2. The clock buffer 32 may generate a plurality of internal clock signals that are synchronized with the system clock CLK and have different predetermined pulse widths.

The command signal / address buffer 31 outputs CMD / ADD to the memory cell array 33 in synchronization with the first internal clock PCLK1.

The demultiplexer 39 sets the second internal clock PCLK2 to one of the plurality of delay circuits 41 and 43 in response to an external selection control signal SEL input from the outside of the semiconductor memory device 30. Output as an input signal.

The plurality of delay circuits 41 and 43 may have different time delay values in order to delay the second internal PCLK2 by a predetermined time and output the same to the third internal clock PCLK3.

Therefore, the third internal clock PCLK3 used to input and output data is delayed by a predetermined time delay value by one of the delay circuits 41 to 43 in response to the external selection control signal SEL. May be controlled through an external pin of the semiconductor memory device 30. That is, the data delay time can be freely controlled. The data delay time can also be adjusted independently of the system clock (CLK) cycle.

FIG. 7 is a block diagram of a semiconductor memory device in which data delay time according to the sixth embodiment of the present invention can be externally controlled through an external pin of the semiconductor memory device. Referring to FIG. 7, the semiconductor memory device 30 may adjust the third internal clock PCLK3 using the multiplexer 45.

The multiplexer 45 includes a plurality of time delay circuits 41 and 43 and an external selection control signal SEL for time delaying the second internal clock PCLK2 differently in response to the second internal clock PCLK2. ), One of the output signals of the delay elements 41 and 43 is selected and output as the third internal clock PCLK3. Data is input and output in synchronization with the third internal clock PCLK3.

Preferably, the delay circuits 41 and 43 have different time delay values in order to delay the second internal clock PCLK2 for a predetermined time. Therefore, the data delay time may be controlled by the third internal clock PCLK3 selected by the multiplexer 45.

FIG. 9 is a block diagram illustrating a memory module including a semiconductor memory device capable of externally adjusting a data delay time and data output timing according to an embodiment of the present invention.

Referring to FIG. 9, the memory module 60 includes a first bus 62, a second bus 64, and a plurality of semiconductor memory devices 61, 63, 65, and 67 packaged on a printed circuit board.

The first bus 62 includes addresses ADD / command signals CMD / system clock CLK / first system clock CLK1 / second system to a plurality of semiconductor memory devices 61, 63, 65, and 67. FIG. Enter the clock (CLK2). The second bus 64 inputs and outputs data in parallel to the plurality of semiconductor memory devices 61, 63, 65, and 67.

The plurality of semiconductor memory devices 61, 63, 65, 67 are implemented using the semiconductor memory devices 10, 20, 30 of any one embodiment of the semiconductor memory device according to the first to sixth embodiments of the present invention. The data delay time can be adjusted on a memory module external to the semiconductor memory devices 61, 63, 65, and 67.

Referring to FIG. 9, a read command signal generated from a memory controller (not shown) is a semiconductor memory device 63 mounted on the memory module 60 after Δt after the semiconductor memory device 61. 65, a read command is transmitted to the memory module 60 after 2 Δt after the semiconductor memory device 61 and 3 Δt after the semiconductor memory device 61. Since the delay time of the data is controlled by controlling the delay circuit 19 or the external selection control signal SEL which can be configured outside the semiconductor memory devices 10, 20, 30 according to the embodiment of the present invention, Data read out from the semiconductor memory devices 61, 63, 65, and 67 are output to the second bus 64 at the same time.

Therefore, even when the address ADD / command signal CMD arrives at different times in each of the semiconductor memory devices 61, 63, 65, 67, the semiconductor memory devices 61, 63 according to the embodiment of the present invention. , 65 and 67, the data delay time can be adjusted on the memory module outside the semiconductor memory device, so that data can be inputted and outputted without skew, thereby facilitating the design of the memory system.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

As described above, the semiconductor memory device according to the present invention is configured on a memory module external to the semiconductor memory device, and thus, the data delay time can be freely adjusted.

In addition, since the memory module including the semiconductor memory device according to the present invention can set an independent data delay time for each semiconductor memory device, there is an advantage of reducing skew and facilitating the configuration of the memory system.

Claims (22)

A buffer configured to receive an address and a command signal in response to the first internal clock synchronized with the external clock; A data input / output circuit for inputting / outputting data to / from a memory cell of a memory cell array in synchronization with a third internal clock generated by delaying a second internal clock synchronized with the external clock by a delay circuit for a predetermined time; And the delay circuit is connected outside the semiconductor memory device to control the delay time. A buffer configured to receive an address and a command signal in response to the first internal clock synchronized with the first external clock; A data input / output circuit for inputting / outputting data to / from a memory cell of the memory cell array in synchronization with a third internal clock generated by delaying a second internal clock synchronized with the second external clock by a predetermined time through a delay circuit; And the delay circuit is connected outside the semiconductor memory device to control the delay time. A dispensing circuit for dispensing the first internal clock synchronized with the external clock; A buffer configured to receive an address and a command signal in synchronization with an output signal of the division circuit; And A data input / output circuit for inputting / outputting data to / from a memory cell of a memory cell array in synchronization with a third internal clock generated by delaying a second internal clock synchronized with the external clock by a delay circuit for a predetermined time; And the delay circuit is connected outside the semiconductor memory device to control the delay time. The semiconductor memory device of claim 2, wherein a frequency of the second internal clock is higher than a frequency of the first internal clock. 4. The semiconductor memory device of claim 3, wherein the frequency of the output clock of the frequency divider circuit is lower than the frequency of the third internal clock. 4. The semiconductor memory device according to any one of claims 1 to 3, wherein said delay circuit is a transmission line. The semiconductor memory device according to any one of claims 1 to 3, wherein the delay circuit is an RC circuit. A buffer configured to receive an address and a command signal in response to the first internal clock synchronized with the external clock; A delay synchronization loop for generating a third internal clock that is phase locked to a second internal clock that is synchronized with the external clock; A delay circuit for delaying the output signal by a predetermined time in response to the output signal of the delay synchronization loop to feed back to the input of the delay synchronization loop; And A data input / output circuit for inputting / outputting data to / from a memory cell of a memory cell array in synchronization with the third internal clock, And the delay circuit is connected outside the semiconductor memory device to control the delay time. 9. The semiconductor memory device according to claim 8, wherein the delay circuit is a capacitance. A plurality of delay circuits for delaying an input signal differently from each other to generate a first internal clock synchronized with an external clock; A demultiplexer outputting a second internal clock synchronized with the external clock as an input signal of the delay circuits in response to an external control signal; And A data input / output circuit for inputting / outputting data to / from the memory cells of the memory cell array in synchronization with the first internal clock; And the external control signal is controlled outside the semiconductor memory device. A plurality of delay circuits for differently delaying the first internal clock synchronized with the external clock for a predetermined time; A multiplexer which selects one of the output signals of the delay circuits in response to an external control signal and outputs the second internal clock synchronized with the external clock; And A data input / output circuit for inputting / outputting data to / from a memory cell of a memory cell array in synchronization with the second internal clock, And the external control signal is controlled outside the semiconductor memory device. A memory module in which a plurality of semiconductor memory devices packaged on a printed circuit board is mounted, A predetermined first bus for supplying an external clock, an address, and a command signal to the plurality of semiconductor memory devices; And A second bus for inputting and outputting data in parallel to the plurality of semiconductor memory devices, Each of the plurality of semiconductor memory devices, A buffer configured to receive an address and a command signal in response to a first internal clock synchronized with the external clock; A data input / output circuit for inputting / outputting data to / from a memory cell of a memory cell array in synchronization with a third internal clock generated by delaying a second internal clock synchronized with the external clock by a delay circuit for a predetermined time; And the delay circuit is configured on the memory module external to the semiconductor memory device to control the delay. A memory module in which a plurality of semiconductor memory devices packaged on a printed circuit board is mounted, A predetermined first bus for supplying first and second external clock, address and command signals to the plurality of semiconductor memory devices; And A second bus for inputting and outputting data in parallel to the plurality of semiconductor memory devices, Each of the plurality of semiconductor memory devices, A buffer configured to receive an address and a command signal in response to a first internal clock synchronized with the first external clock; And a data input / output circuit for inputting / outputting data to / from a memory cell of a memory cell array in synchronization with a third internal clock generated by delaying a second internal clock synchronized with the second external clock by a predetermined time through a delay circuit. And the delay circuit is configured on the memory module external to the semiconductor memory device to control the delay. A memory module in which a plurality of semiconductor memory devices packaged on a printed circuit board is mounted, A predetermined first bus for supplying an external clock, an address, and a command signal to the plurality of semiconductor memory devices; And A second bus for inputting and outputting data in parallel to the plurality of semiconductor memory devices, Each of the plurality of semiconductor memory devices, A dispensing circuit for dispensing the first internal clock synchronized with the external clock; A buffer configured to receive an address and a command signal in synchronization with an output signal of the division circuit; And A data input / output circuit for inputting / outputting data to / from a memory cell of a memory cell array in synchronization with a third internal clock generated by delaying a second internal clock synchronized with the external clock by a delay circuit for a predetermined time; And the delay circuit is configured on the memory module external to the semiconductor memory device to control the delay. The memory module of claim 13, wherein a frequency of the second internal clock is higher than a frequency of the first internal clock. 15. The memory module of claim 14, wherein the frequency of the output clock of the frequency divider circuit is lower than the frequency of the third internal clock. The memory module according to any one of claims 12 to 14, wherein the delay circuit is a transmission line. The memory module according to any one of claims 12 to 14, wherein the delay circuit is an RC circuit. A memory module in which a plurality of semiconductor memory devices packaged on a printed circuit board is mounted, A predetermined first bus for supplying an external clock, an address, and a command signal to the plurality of semiconductor memory devices; And A second bus for inputting and outputting data in parallel to the plurality of semiconductor memory devices, Each of the plurality of semiconductor memory devices, A buffer configured to receive an address and a command signal in response to a first internal clock synchronized with the external clock; A delay synchronization loop for generating a third internal clock that is phase locked to a second internal clock that is synchronized with the external clock; A delay circuit for delaying the output signal by a predetermined time in response to the output signal of the delay synchronization loop to feed back to the input of the delay synchronization loop; And A data input / output circuit for inputting / outputting data to / from a memory cell of a memory cell array in synchronization with the third internal clock, The delay circuit is configured on an external memory module of the semiconductor memory device to control the delay. 20. The memory module of claim 19, wherein the delay circuit is a capacitance. A memory module in which a plurality of semiconductor memory devices packaged on a printed circuit board is mounted, A predetermined first bus for supplying an external clock, an address, and a command signal to the plurality of semiconductor memory devices; And A second bus for inputting and outputting data in parallel to the plurality of semiconductor memory devices, Each of the plurality of semiconductor memory devices, A plurality of delay circuits for delaying an input signal differently from each other to generate a first internal clock synchronized with the external clock; A demultiplexer outputting a second internal clock synchronized with the external clock as an input signal of the delay circuits in response to an external control signal; And A data input / output circuit for inputting / outputting data to / from the memory cells of the memory cell array in synchronization with the first internal clock; And the external control signal is controlled outside of the semiconductor memory device. A memory module in which a plurality of semiconductor memory devices packaged on a printed circuit board is mounted, A predetermined first bus for supplying an external clock, an address, and a command signal to the plurality of semiconductor memory devices; And A second bus for inputting and outputting data in parallel to the plurality of semiconductor memory devices, Each of the plurality of semiconductor memory devices, A plurality of delay circuits for differently delaying the first internal clock synchronized with the external clock for a predetermined time; A multiplexer which selects one of the output signals of the delay circuits in response to an external control signal and outputs the second internal clock synchronized with the external clock; And A data input / output circuit for inputting / outputting data to / from a memory cell of a memory cell array in synchronization with the second internal clock, And the external control signal is controlled outside of the semiconductor memory device.