KR20020032348A - Seed layer deposition - Google Patents

Abstract

PURPOSE: A method of depositing substantially continuous seed layers is provided to conform to surface geometries in electronic devices, particularly in devices having very small geometries such as 0.5 micron and below. CONSTITUTION: A method for depositing a seed layer includes the steps of: contacting a substrate having a conductive layer and apertures of <=1 mum with an electroless copper plating bath; subjecting the substrate to a low current density for a period of time to initiate plating of copper on the conductive layer; discontinuing the current; and continuing to plate electrolessly to provide a copper seed layer.

Description

Seed layer deposition

The present invention generally relates to the field of seed layers for subsequent metallization. In particular, the present invention relates to a method of depositing a seed layer prior to metallization.

The trend towards smaller microelectronic devices, such as devices with sub-micron geometries, has led to the emergence of devices with multiple metallization layers that handle greater densities. One common metal used to form metal lines on a semiconductor wafer, also referred to as wiring, is aluminum. Aluminum has the advantages of being relatively inexpensive, having low resistivity, and being relatively easy to etch. Aluminum has also been used to form interconnects in vias to connect other metal layers. However, since the size of the via / contact hole is reduced to the sub-micron region, a step coverage problem appears, followed by reliability problems when forming interconnects between different metal layers using aluminum. May cause. This poor step coverage results in high current densities and increases electromigration.

One means of providing an improved interconnect path in the via is to form a fully filled plug using a metal such as tungsten while using aluminum for the metal layer. However, tungsten processes are expensive and complex, tungsten has high resistivity, and tungsten plugs are poorly formed voids and interfaces with wiring layers.

Copper has been proposed as an alternative material for interconnect metallization. Copper has the advantages of improved electrical properties, good electrophoretic properties and lower resistivity than aluminum compared to tungsten. Disadvantages to copper are that etching is more difficult than aluminum and tungsten and tends to migrate (and diffuse quickly through the dielectric layer) to a dielectric layer such as silicon dioxide. To prevent this migration, barrier layers such as titanium nitride, tantalum, tantalum nitride, tantalum silicon nitride, tungsten nitride, and the like must be used prior to the deposition of the copper layer.

Typical techniques for applying a metal layer, such as electrochemical deposition, are uniquely suitable for applying copper to an electrically conductive layer. Thus, a conductive seed layer of the undercoat layer, typically a metal seed layer such as copper, is generally applied to the substrate prior to electrochemical deposition of copper. Such seed layers may be applied by various methods, such as physical vapor deposition ("PVD") and chemical vapor deposition ("CVD"). Typically, the seed layer is thinner than other metal layers, such as between 50 and 1500 angstroms thick. Such metal seed layers, in particular copper seed layers, can suffer from such problems as significant thickness variations or discontinuities in the layers besides metal oxides that are present both on the surface of the seed layer and in the bulk of the layer.

Discontinuities or voids are areas of the seed layer that are incomplete or deficient in the coverage of metal, such as copper. Such discontinuities can result in insufficient blanket deposition of the metal layer, such as depositing the metal in the form of a line of sight. In order for the complete metal layer to be electrochemically deposited on this seed layer, the discontinuities must be filled before or during the deposition of the final metal layer, or voids may occur in the final metal layer. For example, PCT patent application WO 99/47731 (Chen) discloses a method for providing a seed layer by first depositing an ultrathin seed layer and then electrochemically enhancing the ultrathin seed layer to form a final seed layer. Doing. In accordance with this patent application, the two-step process provides a seed layer with reduced portions in the seed layer, which are incomplete or deficient in the coverage of the seed layer.

Physical or chemical vapor deposition is complex and difficult to control. In addition, PVD methods tend to deposit metals in the form of eyes. Electroless deposition tends to be more conformal, unlike PVD or CVD, thus providing better aperture sidewall coverage leading to a more continuous seed layer, which eventually voids upon subsequent electroplating. Formation is reduced.

In electronic devices, there is a need for a method of depositing a substantially continuous seed layer suitable for surface geometry, particularly in devices with very few geometries, such as 0.5 microns or less.

It has surprisingly been found that a substantially continuous seed layer can be deposited in one step according to the invention. This method provides a substantially continuous seed layer suitable for the surface geometry of the substrate, particularly on substrates with apertures of ≦ 1 μm.

In one embodiment, the present invention is directed to contacting a substrate having a conductive layer and an aperture of ≦ 1 μm with an electroless copper plating bath; Treating the substrate at a low current density during the time of initiating the plating of copper on the conductive layer; Stop current; Provided is a method of depositing a seed layer comprising continuing plating with electroless to provide a copper seed layer.

In a second example, the present invention provides a method of contacting an electronic device substrate having a conductive layer and an aperture of ≦ 1 μm with an electroless copper plating bath; Treating the electronic device substrate at low current density during the time of initiating the plating of copper on the conductive layer; Stop current; Provided is a method of fabricating an electronic device comprising continuing plating with electroless to provide a copper seed layer.

In a third example, the present invention is directed to contacting a substrate having a discontinuous seed layer with an electroless copper plating bath; Treating the substrate at a low current density during the time of initiating the plating of copper on the conductive layer; Stop current; Provided is a method of enhancing a discontinuous seed layer disposed on a substrate that comprises continuing to electrolessly plate to provide a substantially continuous seed layer.

The following abbreviations shall have the following meanings unless explicitly indicated otherwise in the text: nm = nanometer; Μm = micron = micrometer; nm = nanometer; ° C = degrees centigrade; g / L = 1 gram per liter; mA / cm ² = milliampere per square centimeter; M = mole; And ppm = 1 million parts.

As used throughout the specification, "feature" refers to, but is not limited to, geometries on a substrate, such as trenches and vias. "Aperture" refers to recessed features, such as vias and trenches. "Small features" means features that are 1 micron or smaller in size. "Very small features" means features that are 1/2 micron or smaller in size. Similarly, "small aperture" refers to an aperture of 1 micron or smaller in size (≤1 μm) and "very small aperture" refers to an aperture of 1/2 micron or smaller in size (≤0.5 μm) do. As used throughout the specification, "plating" refers to metal electroplating unless explicitly stated otherwise in the text. "Deposition" and "plating" are used interchangeably throughout the specification. "Halo" means fluoro, chloro, bromo, and iodo. Similarly, "halide" means fluoride, chloride, bromide and iodide. "Alkyl" includes straight chain, branched and cyclic alkyl groups.

All percentages and ratios are by weight unless otherwise indicated. All ranges are inclusive and combinable.

The present invention contacts a substrate having a conductive layer and an aperture of ≦ 1 μm with an electroless copper plating bath; Treating the substrate at a low current density during the time of initiating the plating of copper on the conductive layer; Stop current; Provided is a method of depositing a seed layer comprising continuing plating with electroless to provide a copper seed layer. The present invention is suitable for depositing seed layers on a variety of substrates, in particular substrates used in the manufacture of electronic devices.

Suitable substrates are those containing conductive layers for subsequent electrodeposition of metals. Particularly suitable substrates are wafers used in the manufacture of integrated circuits and semiconductors, printed circuit board inner and outer layers, flexible circuits and the like. It is preferred that the substrate is a wafer. Examples of substrates include, but are not limited to, substrates containing one or more apertures having a size of ≦ 1 μm, specifically ≦ 0.5 μm, and more specifically ≦ 0.18 μm.

Typical conductive layers include barrier layers, such as barrier layers used in the manufacture of integrated circuits. Such a conductive layer only needs to be sufficiently conductive so that plating can be initiated by the application of a potential to the conductive layer. Suitable barrier rib layers include those containing one or more cobalt, cobalt-tungsten-phosphorus, tungsten, tungsten nitride or titanium nitride.

According to the invention a wide range of electroless copper plating baths can be used. In general, such electroless plating solutions typically contain copper ions, one or more reducing agents and optionally a complexing agent. Typically, the electroless plating solution is aqueous, but also contains one or more organic solvents.

Copper ions are in soluble form, such as copper nitrate, copper sulfate, copper sulfamate, copper sulfonate, copper alkylsulfonate, copper arylsulfonate, copper halide, copper fluoroborate, copper gluconate, copper acetate, copper foil Mate, etc., in an electroless plating bath. The amount of these copper ions depends on the specific electroless bath used. Such amounts are within the ability of one skilled in the art and are sufficient to provide amounts of copper metal (zero valent copper), typically in the range of about 1 to about 5 g / L, and preferably about 2 to about 3 g / L.

A wide range of reducing agents can be used in such electroless baths. Suitable reducing agents are sodium hypophosphite, potassium hypophosphite, sodium borohydride, formaldehyde, dimethylamine borane, trimethylamine borane, methylmorpholino borane, morpholino borane, diisopropylamino borane, L-sodium as Corbate, sodium phosphite, potassium phosphite, tartaric acid, glucose, glycerin, sodium N, N-diethylglycine, sodium formate, potassium formate, titanium trichloride, hydrazine, thiourea, methylthiourea, N-methyl Thiourea, N-ethylthiourea, hydroquinone, divalent copper compounds, and the like, but are not limited to these. Formaldehyde, dimethylamine borane and sodium borohydride are preferred. The amount of such reducing agent in the electroless bath is well known to those skilled in the art and depends on the particular reducing agent chosen and whether the electroless bath is a fast or slow copper electroless plating bath. For example, when formaldehyde is used as the reducing agent, it is typically used in the range of about 1 to about 15 g / L and preferably about 6 to about 12 g / L.

Optionally, the electroless bath may contain one or more complexing agents such as ethylenediamine, ethylenediaminetetraacetic acid ("EDTA"), tetramethylenediamine, citrate salts, tartrate salts such as Rochelle salts, and the like.

Copper electroless plating baths are typically alkaline and preferably highly alkaline. Thus, such electroless baths typically contain one or more bases. Suitable bases include alkali metal hydroxides, ammonium hydroxides, tetra (C ₁ -C ₄ ) alkylammonium hydroxides and the like. Preferred bases include sodium hydroxide, potassium hydroxide, lithium hydroxide and tetramethylammonium hydroxide. This base is added in an amount sufficient to provide the desired alkalinity to the electroless copper plating bath. Typically, such bases are added in an amount sufficient to provide a pH range of about 7.5 to about 14, preferably about 8 to about 13.5, and more preferably about 8.5 to about 13.

Substrates with conductive layers are typically contacted with a copper electroless plating bath by various methods, such as dipping, spraying, spin coating, flood coating, and the like. Upon contact with the electroless copper bath, the substrate is treated to a low current density during the time of initiating copper plating on the conductive layer, after which the current is stopped and the seed layer is electroless plated. Only low current density is needed to initiate plating in an electroless copper bath. Suitable current densities are about 10 mA / cm ² and preferably about 5 mA / cm ² or less. This low current density is typically applied for up to about 30 seconds, and preferably about 10 to about 30 seconds, to initiate plating. Although not easy to understand in theory, it is believed that the application of such low current densities initiates the electrodeposition of copper seed crystals on conductive layers that serve as catalyst sites for electroless copper deposition.

After interrupting the current, the substrate containing the conductive layer typically remains in contact with the electroless plating bath for a time sufficient to deposit the desired copper seed layer. Suitable plating times are typically at least about 0.5 minutes, preferably at least about 1 minute, and more preferably at least about 5 minutes. Other suitable plating times include at least about 20 minutes. There is no practical upper limit to the plating time used. The longer this electroless plating is carried out, the thicker the metal deposit obtained. Those skilled in the art will appreciate that the plating rate may be slowed down as the thickness of the deposit increases. Typically, such electroless plating can be performed at temperatures of about 95 ° C. below room temperature, and preferably from 25 to 80 ° C. These times and temperatures depend on the specific electroless plating bath used.

Once the desired copper seed layer is obtained, the substrate can be taken out of contact with the electroless plating bath and optionally rinsed. The seed layer-containing substrate may then be further plated, such as by contacting the seed layer with an electroplating bath, preferably a copper plating bath, to substantially fill or completely fill the aperture. A particularly suitable electroplating bath is the ULTRAFILL ^™ 2001 EP copper deposition chemistry from Shipley Company, Marlborough, Massachusetts. Copper electroplating baths typically contain one or more sources of copper ions and an electrolyte. Preferably the electrolyte is acidic. The amounts of copper and electrolytes can vary widely and are well known within the skill of those skilled in the art. Such electroplating baths may optionally contain one or more additives, such as halides, accelerators or brighteners, suppressors, levelers, grain refiners, wetting agents, surfactants, and the like. have. The amount of such additives is well known within the ability of those skilled in the art.

In another example, the substrate may be maintained in an electroless copper bath until the desired copper thickness is obtained. In this way, the substrate containing the copper seed layer is not separated, but rather a copper metal layer of the desired thickness is deposited directly on the conductive layer. In the manufacture of integrated circuits, this method is useful because a separate seed layer step can be avoided. Thus, a copper layer of sufficient thickness to substantially or completely fill the aperture in the substrate (wafer) can be deposited directly on the barrier layer.

The present invention is also suitable for improving the discontinuous metal seed layer on the substrate. "Enhancing" a discontinuous metal seed layer means supplementing or expanding the seed layer to substantially fill or, preferably, completely fill this seed layer or seedless seed layer. Accordingly, the present invention also provides for contacting a substrate having a discontinuous seed layer with an electroless copper plating bath; Treating the substrate at a low current density during the time of initiating the plating of copper on the conductive layer; Stop current; A method is provided for improving a discontinuous seed layer disposed on a substrate that includes plating electrolessly to provide a substantially continuous seed layer.

The present invention can be used to enhance seed layers deposited by deposition methods such as CVD or PVD or by other deposition means. Preferably, this seed layer is copper or copper alloy. It is also desirable to place such seed layers on wafers used in the manufacture of integrated circuits.

An advantage of the present invention is that it does not use typical electroless catalysts such as palladium and palladium / tin. A further advantage is that the seed layer obtained is substantially continuous and preferably continuous. That is, the seed layer enhanced and / or deposited according to the present invention covers a surface area of> 95%, preferably> 98%, and more preferably> 99% of the substrate. This seed layer is also uniform due to the conformal electroless deposits.

The seed layer of the present invention may be deposited on a wide variety of substrates, discussed above. The method of the present invention is particularly useful for providing seed layers for subsequent electroless or electrolytic plating of difficult workpieces, such as circuit board substrates with small diameters, high aspect ratio microvias and other apertures. The method of the present invention is also particularly useful for depositing seed layers on integrated circuit devices, such as formed semiconductor devices and the like. The method of the present invention is particularly suitable for providing a substantially continuous seed layer on a substrate having high aspect ratio microvias and trenches, such as 4: 1 or more aspect ratio microvias and trenches.

As discussed above, microvias and trenches of at least an aspect ratio of at least 4: 1, having a diameter of about 200 nm or less, are free of defects (eg, by ion beam testing) on a substantially continuous seed layer of the present invention. No voids or inclusions) can be effectively copper plated. A seed layer on a substrate comprising an aperture of 150 nm or less, or even about 100 nm or less, and having an aspect ratio having a 5: 1, 6: 1, 7: 1, 10: 1 or greater aspect ratio can be deposited using the present invention or Can be effectively improved. The present invention is particularly suitable for depositing and replenishing seed layers on substrates having 0.18 μm and less apertures.

After metallization, ie filling of the apertures, the substrate is preferably chemically-mechanical planarized ("CMP") for wafers. The CMP process can be performed as follows according to the present invention.

The wafer is fixed to a wafer carrier which pushes the wafer against the surface of the movable polishing pad. The polishing pad can be a conventional soft polishing pad or grooved polishing pad. Suitable polishing pads with grooves can be obtained from Rodel, Inc., Newark, Delaware. The polishing pad can be placed on a conventional platen that can rotate the polishing pad. The polishing pad can be mounted on the platen by an adhesive, such as, but not limited to, a double-sided tape having an adhesive on both sides.

The polishing solution or slurry is fed onto a polishing pad. The wafer carriers can be placed in different positions on the polishing pad. The wafer is placed in position by suitable mounting means such as, but not limited to, wafer holder, vacuum or fluid tensioning (such as, but not limited to, fluids such as, but not limited to). Can be mounted. If the mounting means is by vacuum, it is preferable that there is a hollow shaft connected to the wafer carrier. In addition, the hollow shaft could be used to adjust the gas pressure, such as but not limited to air or inert gas, or to initially mount the wafer using a vacuum. Gas or vacuum will flow from the hollow shaft to the carrier. The gas may adhere the wafer to the polishing pad for the desired appearance of the wafer. The vacuum can initially mount the wafer to a location in the wafer carrier. Once the wafer is placed on top of the polishing pad, vacuum can be liberated and gas pressure can be applied to force the wafer out against the polishing pad. Excess or unwanted copper is then removed. The platen and wafer carrier can be rotated separately. Thus, it is possible to rotate the wafer in the same direction as the polishing pad or to rotate the wafer in the opposite direction to the polishing pad at the same or different speeds.

Accordingly, the present invention utilizes an excess amount of semiconductor wafers containing at least one aperture of ≦ 1 μm using a chemical mechanical planarization process comprising contacting the semiconductor wafer with a rotating polishing pad to remove excess material from the semiconductor wafer. Providing a method of removing material; Wherein the aperture is brought into contact with the electroless copper plating bath with a substrate having a conductive layer and an aperture of 1 μm or less; Treating the substrate at a low current density during the time of initiating the plating of copper on the conductive layer; Stop current; It contains a seed layer deposit obtained from continuing plating with electrolessly to provide a copper seed layer.

<Example 1>

Prepare a copper bath containing 2 g / L copper sulfate, 18 g / L tetramethylammonium hydroxide, 3.5 g / L formaldehyde, 40 g / L EDTA and <1 g / L other additives do. The titanium nitride ("TiN") barrier layer is then contacted with a copper bath at a temperature of 50 ° C., containing an anode, on which the wafer substrate is deposited on the substrate by PVD. A voltage was applied to the substrate and the substrate was cathode, producing a current density of 5 mA / cm ^{2 for} 60 seconds, during which time the copper seed layer was deposited on the barrier material. The voltage was then removed and the wafer substrate Is maintained in contact with the copper bath for a time sufficient to deposit a copper seed layer having a thickness of about 5 to 100 nm. The substrate is then removed from the copper bath and rinsed with deionized water.

<Example 2>

The wafer substrate of Example 1 is then annealed by placing the wafer on a hot plate for 60 seconds in an atmosphere of reduced oxygen content. The temperature of the hot plate is 200 ° C. The wafer substrate is then removed from the hot plate and cooled. Once cooled, the wafer substrate is treated with an electrolytic copper plating bath such as that sold by Shipley, under the ULTRAFILL 2001 trademark, to metallize the wafer substrate. The wafer substrate is placed in an electrolytic plating bath for a time sufficient to provide the desired metallized layer. The wafer substrate is then taken out of the electrolytic plating bath, rinsed with deionized water and further processed.

<Example 3>

In water with pH adjusted to 9.0 by addition of tetramethylammonium hydroxide, copper chloride (10 g / L), N-hydroxyethyl ethylenediamine triacetic acid (26 g / L), sodium hypophosphite ( Prepare a copper bath containing 26 g / L). The wafer substrate with the cobalt-tungsten-phosphide partition wall layer is then contacted with a copper bath containing the anode at a temperature of 50 ° C. A voltage is then applied to the substrate, with the substrate serving as the cathode, producing a current density of 5 mA / cm ² for 60 seconds, during which time a copper seed layer is deposited on the barrier layer. The voltage is then removed and the wafer substrate is left in contact with the copper bath for a time sufficient to deposit a copper seed layer having a thickness of about 5 to 100 nm. The substrate is then taken out of the copper bath, rinsed with deionized water and further processed according to the method of Example 2.

<Example 4>

1 liter containing copper sulfate (0.04M), N-hydroxyethyl ethylenediamine triacetic acid (0.05M), sodium hypophosphite (0.34M) in water with pH adjusted to 3 by addition of dilute sulfuric acid Prepare the copper bath. The wafer substrate with the TiN barrier layer is then contacted with a copper bath containing the anode at a temperature of 50 ° C. Thereafter, a voltage was applied to the substrate, and the substrate was used as a cathode to produce a current density of 5 mA / cm ² for 60 seconds, during which time a copper seed layer was deposited on the barrier layer. The voltage is then removed and the wafer substrate is left in contact with the copper bath for a time sufficient to deposit a copper seed layer having a thickness of about 5-100 nm. The substrate is then taken out of the copper bath, rinsed with deionized water and further processed according to the method of Example 2.

The method of depositing a copper seed layer on a substrate with a conductive layer according to the invention is particularly suitable for depositing a copper seed layer on a substrate with small apertures, and preferably with very small apertures.

Claims (27)

A substrate having a conductive layer and an aperture of 1 μm or less is contacted with an electroless copper plating bath; Treating the substrate at a low current density during the time of initiating the plating of copper on the conductive layer; Stop current; And continuing to electroless plating to provide a copper seed layer. The method of claim 1 wherein the conductive layer is a barrier layer. The method of claim 2, wherein the barrier layer comprises cobalt, cobalt-tungsten-phosphorus, tungsten, tungsten nitride or titanium nitride. The method of claim 1, wherein the current density is about 10 mA / cm ² or less. The method of claim 4, wherein the current density is about 5 mA / cm ² or less. The method of claim 1, wherein the time is less than about 30 seconds. The method of claim 6, wherein the time is about 10 to about 30 seconds. The method of claim 1 wherein the aperture is 5 μm or less. The method of claim 1 wherein the substrate is a wafer. Contacting the electronic device substrate with the conductive layer and the aperture of ≦ 1 μm with an electroless copper plating bath; Treating the electronic device substrate at low current density during the time of initiating the plating of copper on the conductive layer; Stop current; Providing a copper seed layer comprising continuing plating with electrolessly to provide a copper seed layer. The method of claim 10, wherein the conductive layer is a partition layer. 12. The method of claim 11 wherein the barrier layer comprises cobalt, cobalt-tungsten-phosphorus, tungsten, tungsten nitride or titanium nitride. The method of claim 10, wherein the current density is about 10 mA / cm ² or less. The method of claim 13, wherein the current density is about 5 mA / cm ² or less. The method of claim 10, wherein the time is less than about 30 seconds. The method of claim 15, wherein the time is about 10 to about 30 seconds. The method of claim 10, wherein the aperture is 5 μm or less. The method of claim 10, wherein the electronic device is an integrated circuit. The method of claim 10, wherein the substrate is a wafer. Contacting the substrate with the discontinuous seed layer with an electroless copper plating bath; Treating the substrate at a low current density during the time of initiating the plating of copper on the conductive layer; Stop current; Continuing to plating electrolessly to provide a substantially continuous seed layer, wherein the discontinuous seed layer disposed on the substrate is enhanced. The method of claim 20, wherein the discontinuous seed layer is copper or a copper alloy. The method of claim 20, wherein the current density is about 10 mA / cm ² or less. The method of claim 22, wherein the current density is no greater than about 5 mA / cm ² . The method of claim 20, wherein the time is less than about 30 seconds. The method of claim 24, wherein the time is about 10 to about 30 seconds. The method of claim 20, wherein the aperture is 5 μm or less. The method of claim 20, wherein the substrate is a wafer.