KR20020030901A - Trench isolation structure and method for fabricating the same - Google Patents

Abstract

PURPOSE: A method for fabricating a trench isolation structure is provided to prevent a dishing phenomenon in a planarization etch process and to improve a characteristic of an isolation layer, by forming the isolation layer through three processes for forming buried layer and two planarization etch processes. CONSTITUTION: The first trench(206a) and the second trench(206b) having a with broader than that of the first trench are formed on a semiconductor substrate(200). The first buried layer(210) filling the first trench is formed on the resultant structure having the first and second trenches. The second buried layer filling the second trench is formed on the first buried layer. The second buried layer is planarization-etched until the first buried layer is exposed. The first buried layer is etched to make the upper surface of the first buried layer lower than the upper surface of the semiconductor substrate so that a recess portion is formed. The third buried layer(215) filling the recess portion is formed on the resultant structure having the recess portion. The third and second buried layers are planarization-etched to form the isolation layer(220a,220b) filling the first and second trenches.

Description

Trench isolation structure and method of manufacturing the same {TRENCH ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a trench isolation structure and a method for manufacturing the same, which can prevent dishing from occurring in a wide trench region.

As the degree of integration of semiconductor devices increases, the depth of trenches increases and the width gradually decreases in forming trench isolation layers that define active regions. As the aspect ratio of the trench increases, a problem occurs in that voids are generated in the trench in the process of filling the trench with an insulating layer.

In order to improve this, a method of filling the trench by filling the lower portion of the trench with an insulating film having excellent gap filling characteristics and further forming an insulating film having excellent insulating characteristics is used. For example, the lower portion of the trench is filled with a polysilicon film or an amorphous silicon film having a small insulating property but excellent gap filling property, and the remaining portion of the trench having a smaller aspect ratio is filled with an oxide film having excellent insulating property. This makes it possible to fill the inside of the trench without voids even when the aspect ratio is large.

Hereinafter, the problems of the prior art will be described with reference to the accompanying drawings.

1A to 1G are cross-sectional views illustrating a trench isolation method according to the prior art.

Referring to FIG. 1A, a pad oxide film 103 and a silicon nitride film 104 are sequentially formed on an entire surface of the semiconductor substrate 100. The pad oxide film 103 serves to relieve stress applied to the semiconductor substrate 100, and the silicon nitride film 104 is used as an etching mask in a subsequent process of forming a trench. The silicon nitride film 104 and the pad oxide film 103 are sequentially patterned to form an etching mask pattern 105 for forming a trench.

Referring to FIG. 1B, the second trench may be relatively wider than the first trench 106a and the first trench 106a by dry etching the semiconductor substrate 100 using the etching mask pattern 105 as an etching mask. Form 106b. An oxide liner 108 is formed to cure the etching damage caused when the trenches are formed in the inner walls of the first and second trenches 106a and 106b.

Referring to FIG. 1C, the first buried film 110 is formed to fill the first trench 106a on the entire surface of the resultant in which the oxide liner 108 is formed. The first buried film 110 is formed of a material having excellent gap filling properties, for example, a polysilicon film. Since the aspect ratios of the first trenches 106a and the second trenches 106b are different, the inside of the first trenches 106a is filled with the first buried film 110, while the inside of the second trenches 106b is formed in the first trench 106a. 1 It is not filled with the buried film (110).

Referring to FIG. 1D, the first buried film 110 is etched such that an upper surface of the first buried film 110 formed in the first trench 106a is lower than an upper surface of the semiconductor substrate 100. Then, the first buried film pattern 110a filling the lower portion of the trench 106a is formed in the first trench 106a, and the first spacer in the form of a spacer is formed only in the sidewall of the trench 106b in the second trench 106b. A buried film pattern 110b is formed.

Referring to FIG. 1E, a second buried film 113 having excellent insulating properties is formed on the resultant on which the first buried film patterns 110a and 110b are formed to fill the first and second trenches 106a and 106b. In this case, the lower portion of the first trench 106a is filled with the first buried film 110a, whereas the first buried film pattern 110b in the form of a spacer is formed inside the second trench 106b, so that the second buried When the film 113 is formed, the upper surface of the second trench 106b region is relatively lower than the first trench 106a region.

Referring to FIG. 1F, the second buried film 113 is planarized etched by a chemical mechanical polishing (CMP) process or the like until the etching mask pattern 105 is exposed. At this time, since the step difference between the regions of the first trench 106a and the second trench 106b is severe, a dishing phenomenon occurs in which the region of the second trench 106b is recessed after the planarization etching.

Referring to FIG. 1G, the etching mask patterns 105 on the semiconductor substrate 100 are removed by wet etching to form device isolation layers 120a and 120b in the first and second trenches 106a and 106b. An isolation layer 120a having an excellent profile is formed inside the first trench 106a, while an isolation layer 120b having an upper surface lower than the semiconductor substrate 100 is formed inside the second trench 106b. .

As described above, when the trench isolation is formed according to the related art, the second trench 106b during the CMP process due to the step difference occurring in the region of the first trench 106a having a narrow width and the second trench 106b having a wide width is formed. Dicing phenomenon occurs when the buried film in the) region is pitted. Therefore, as shown in FIG. 1G, the upper surface of the device isolation film 120b formed in the second trench 106b is lower than the upper surface of the semiconductor substrate 100, which lowers the insulation characteristics of the device isolation film. It causes.

The present invention has been proposed to solve the above-mentioned problems, and an object thereof is to provide a trench device isolation method capable of reducing the step difference between a trench having a wide width and a trench region having a narrow width.

1A to 1G are cross-sectional views illustrating a trench isolation method according to the prior art.

2A to 2H are cross-sectional views illustrating a trench isolation method according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

100, 200: semiconductor substrate 103, 203: pad oxide film

104, 204: etching mask layer 105, 205: etching mask pattern

106a, 206a: first trench 106b, 206b: second trench

108, 208: oxide film liner 110, 210: first buried film

113,213: 2nd buried film 215: 3rd buried film

220a, 220b: device isolation layer

(Configuration)

In order to achieve the above object, the trench isolation method according to the present invention forms a first trench and a second trench having a relatively wider width than the first trench. A first buried film filling the first trench is formed on the entire surface of the resultant product in which the first and second trenches are formed. A second buried film filling the second trench is formed on the first buried film. The second buried film is planarized and etched to expose the first buried film. A portion of the first buried film is etched to form a recessed portion such that the top surface of the first buried film is lower than the top surface of the semiconductor substrate. A third buried film is formed on the entire surface of the resultant in which the recess portion is formed. The third and second buried films are planarized and etched to form device isolation layers filling the first and second trenches.

In order to achieve the above-described object, the trench isolation structure according to the present invention includes a semiconductor substrate, a first trench formed in the semiconductor substrate, and a second trench having a relatively wider width than the first trench. A first buried film formed below the upper surface of the semiconductor substrate, a second buried film formed on the first buried film of the second trench at a predetermined distance from a sidewall of the trench to fill a central portion of the second trench; And a third buried film formed on the first buried film of the first trench to fill the first trench, and formed on the first buried film exposed around the second buried film of the second trench to fill the second trench. It features.

(Example)

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2A to 2H are cross-sectional views illustrating a trench isolation method according to the present invention.

Referring to FIG. 2A, a pad oxide film 203 is formed on the semiconductor substrate 200 to reduce stress applied to the semiconductor substrate 200 by growing a thermal oxide film. An etching mask layer 204 is formed on the pad oxide layer 203 using a material having a high etching selectivity with the semiconductor substrate 200, for example, a silicon nitride layer. The etching mask layer 204 is used as an etching mask in a trench etching process which is performed in a subsequent process, and is used as an etching stop layer during the planarization process for the buried film. The etch mask layer 204 and the pad oxide layer 203 are sequentially patterned so that a predetermined region of the semiconductor substrate 200 is exposed to form an etch mask pattern 205 defining a trench formation region.

Referring to FIG. 2B, dry etching of the exposed semiconductor substrate 200 using the etching mask pattern 205 as an etching mask has a relatively wider width than the first trench 206a and the first trench 206a. The second trench 206b is formed. For example, in the case of a memory device, the first trench 206a is a narrow trench formed in the cell region, and the second trench 206b is a wide trench formed in the peripheral circuit region.

When the semiconductor substrate 200 is dry etched to form the trenches 206a and 206b, etching damage is applied to the semiconductor substrate 100, which causes crystal defects and the like to cause leakage current in the substrate. In order to cure such etching damage, an oxide liner 208, for example, a thermal oxide layer, is formed on the inner walls of the first and second trenches 206a and 206b to a thickness of 50 to 300 kPa.

Preferably, a silicon nitride film (not shown) is formed on the oxide liner 208 as an anti-oxidation film to prevent further oxidation of the inner walls of the trenches 206a and 206b by a subsequent thermal process. In addition, an oxide layer (not shown) may be further formed on the silicon nitride layer as an anti-etching layer for preventing the silicon nitride layer and the oxide liner from being etched in a subsequent etching process.

Referring to FIG. 2C, the first buried film 210 filling the inside of the first trench 206a is formed on the entire surface of the resultant in which the oxide liner 208 is formed. The first buried film 210 may be formed of a trench having a high aspect ratio, that is, a film having excellent gap filling properties so as to fill the inside of the first trench 206a without voids. The first buried film 210 is formed of, for example, any one of a polysilicon film, an amorphous silicon film, and a borophosphosilicate glass (BPSG) film. Then, the first trench 206a is filled with the first buried film 210, while the second trench 206b having a wider width than the first trench 206a is not filled with the first buried film 210. Do not.

A second buried film 212 is formed on the first buried film 210 to fill the second trench 206b in which the first buried film 210 is formed. The second buried film 212 may be formed of an insulating film having excellent planarization characteristics such that the insulating layer 212 has excellent insulation characteristics and may reduce the step difference between the first trenches 106a and the second trenches 106b. The second buried film 212 is formed of, for example, any one of an O ₃ -tetraethylorthosilicate (TEOS) film, a plasma enhanced TEOS (PE-TEOS) film, an undoped silicate glass (USG) film, and a high density plasma (HDP) oxide film. do. As a result, the inside of the first trench 106a is filled with the first buried film 210, and the inside of the second trench 106b is filled with the first buried film 210 and the second buried film 212.

2D and 2E, the second buried film 212 is planarized and etched by a CMP process until the first buried film 210 is exposed. A portion of the exposed first buried film 210 is etched by a dry or wet etching process until the upper surface of the first buried film 210 is lower than the upper surface of the semiconductor substrate 200. Then, the first buried film 210 on the first trench 206a is etched to form a recessed portion 211a, and is exposed between the sidewall of the second trench 206b and the second buried film 212. A portion of the first buried film 210 is etched to form a recessed portion 211b.

Referring to FIG. 2F, a third buried film 215 filling the recess portions 211a and 211b may be formed on the entire surface of the resultant portion in which the recess portions 211a and 211b are formed. It is preferable that the third buried film 215 is formed of an insulating film excellent in insulating properties and planarization properties. The third buried film 215 is formed of, for example, any one of an O ₃ -TEOS film, a PE-TEOS film, a USG film, and an HDP oxide film. In some cases, the film may be formed of the same film as the second buried film 212. At this time, the second buried film 212 is formed in the second trench 206b. When the third buried film 215 is formed, the upper surface of the second trench 206b is formed in the first trench 206a. It is slightly higher than the area. As a result, the step difference between the first trench 206a region and the second trench 206b region is reduced as compared with the conventional art, and the dishing phenomenon is prevented from occurring in the second trench 206b region in the subsequent planarization etching process. Can be.

2G and 2H, the third buried film 215 and the second buried film 212 are planarized and etched by CMP or the like until the etch mask pattern 205 is exposed. The etching mask pattern 205 on the active region is removed to form the device isolation layer 220. Then, an isolation layer 220a in which the first buried film 210 and the third buried film 220 are stacked is formed in the first trench 206a. In addition, a structure in which a second buried film 220 is stacked on the first buried film 208 and a third buried film 215 is formed around the second buried film 220 in the second trench 206b. Device isolation film 220b is formed.

According to the present invention, by forming the device isolation layer through three buried film formation processes and two planarization etching processes, a step difference between a wide trench and a narrow trench region may be reduced. Accordingly, it is possible to prevent dishing in the planarization etching process to improve characteristics of the device isolation layer.

Claims (8)

Forming a first trench on the semiconductor substrate and a second trench having a relatively wider width than the first trench; Forming a first buried film filling the first trench on an entire surface of the resultant product in which the first and second trenches are formed; Forming a second buried film filling the second trench on the first buried film; Planarizing etching the second buried film until the first buried film is exposed; Etching the first buried film to form a recessed portion such that an upper surface of the first buried film is lower than an upper surface of the semiconductor substrate; Forming a third buried film filling the recess portion on the entire surface of the resultant product in which the recess portion is formed; And And forming a device isolation layer filling the first and second trenches by planarizing etching the third and second buried films. The method of claim 1, And the first buried film is formed of a polysilicon film, an amorphous silicon film, or a borophosphosilicate glass (BPSG) film. The method of claim 1, The second buried film may be formed of any one of an O ₃ -tetraethylorthosilicate (TEOS) film, a plasma enhanced-TEOS (PE-TEOS) film, an undoped silicate glass (USG) film, and a high density plasma (HDP) oxide film. Device isolation method. The method of claim 1, The third buried film may be formed of any one of an O ₃ -tetraethylorthosilicate (TEOS) film, a plasma enhanced-TEOS (PE-TEOS) film, an undoped silicate glass (USG) film, and a high density plasma (HDP) oxide film. Device isolation method. The method of claim 1, Forming the first and second trenches, Forming a pad oxide film on the semiconductor substrate; Forming an etch mask layer on the pad oxide layer; Patterning the etch mask layer and the pad oxide layer in order to form an etch mask pattern exposing a predetermined region of the semiconductor substrate; And And etching the predetermined region of the exposed semiconductor substrate by using the etching mask pattern as an etching mask. The method of claim 1, And forming an oxide film and a nitride film in order on the inner wall of the trench after the trench is formed. Semiconductor substrates; A first trench formed in the semiconductor substrate and a second trench having a relatively wider width than the first trench; A first buried film formed below the first and second trenches to have an upper surface lower than an upper surface of the semiconductor substrate; A second buried film formed on the first buried film of the second trench at a predetermined distance from a sidewall of the second trench to fill a central portion of the second trench; And Formed on the first buried film of the first trench to fill the first trench, and formed on the first buried film exposed around the second buried film of the second trench to fill the second trench A trench isolation structure comprising a third buried film. The method of claim 7, wherein The trench device isolation structure of claim 1, further comprising an oxide film and a nitride film sequentially stacked on inner walls of the first and second trenches.