KR20020029713A - Method of fabricating dram devices - Google Patents

Abstract

PURPOSE: A method for fabricating a dynamic random access memory(DRAM) is provided to reduce a burden of an annealing process in forming a polysilicon layer and to decrease interfacial resistance between the polysilicon layers, by simultaneously forming a plug having the same material as a stud when a storage contact of the same as or similar to the level of the stud is formed. CONSTITUTION: A bit line(19) and a bit line contact(17) are formed on a substrate(10) where an interlayer dielectric(13) is stacked on the structure of a metal oxide semiconductor(MOS) transistor. An interlayer dielectric(20) is stacked on the bit line. The interlayer dielectric is selectively etched to form a storage node contact hole and a stud hole. A conductive layer is stacked while the contact hole and the stud hole are formed, so that a contact plug and the stud are simultaneously formed.

Description

DRAM device manufacturing method {METHOD OF FABRICATING DRAM DEVICES}

The present invention relates to a method for manufacturing a DRAM device, and more particularly, to a method for stabilizing a contact resistance at a low state in a cell region while proceeding to a low temperature process in manufacturing a DRAM device.

With the recent trend toward higher integration of devices, the device size of DRAM devices has been reduced, and device layout and wiring have been three-dimensional. Accordingly, contact holes for connecting the upper and lower elements and the wiring in the DRAM device are formed at various depths in the same step. However, due to the high aspect ratio and problems of contact hole etching and filling, there are many difficulties in forming a deep contact hole with a shallow contact hole at the same time.

One way to alleviate these difficulties is to form studs that mediate where they are needed. 1 is a cross-sectional view showing an example in which a stud is used in forming a conventional DRAM device. Referring to FIG. 1, an isolation layer 11 is formed on a substrate 10, and gate patterns 12 and 12 ′ are formed in a cell region and a periphery, respectively, to form a MOS type transistor structure. An interlayer insulating film 13 is formed over the transistor structure. The bit line 19 and the bit line contacts 17 are formed using a damascene process. In the cell region, a SAC pad hole of the storage node contact is formed, and the pad hole is filled with polysilicon to form the storage node contact pad 15. The contact pad 15 and the bit line 19 and the bit line contact 17 may be formed separately when the pad of the bit line contact is not formed, and thus the order of formation may be changed.

An interlayer insulating layer 20 of silicon oxide and a etch stop layer 22 of silicon nitride are formed on the bit line 19. A contact hole is formed in the storage node contact region and polysilicon is filled to form the storage node contact plug 24. The stud 26 is formed at the position of the contact where the bit line 19 and the upper wiring 40 are to be connected to reduce the step difference in forming the contact hole. The studs 26 pattern the interlayer insulating film 20 and the etch stop layer 22 to form stud holes, thinly deposit a titanium / titanium nitride layer as a barrier layer, fill these with CVD tungsten, and cover these etch stop layers. The films are formed by removing them with a planarization etch such as tungsten CMP.

In the cell region in which the storage node is to be formed, the molding layer 28 is stacked with the silicon oxide layer, and the storage node hole is formed to form the polysilicon while the storage node contact plug 24 is exposed. When the polysilicon stacked on the molding layer is removed by planarization etching through CMP or the like, the node is separated to form the storage node 27. Only the molding film 28 remains in the region where the stud 26 is formed. Through the process of forming the HSG 30 in the storage node 27, the dielectric layer 32 is thinly formed and the polysilicon is stacked again to form the plate electrode 34. On the other hand, in the periphery and the core region where the stud 26 is formed, the plate electrode layer is removed, and the insulating film 36 is laminated as a whole. A contact hole is formed in the region of the stud 26 over the insulating film 36, and a wiring layer made of barrier film and CVD tungsten is stacked and patterned to form the wiring contact plug 38 and the wiring 40.

At this time, the stud serves to help the gap fill by reducing the step difference due to the wiring contact hole formation in forming a contact connecting the upper wiring and the bit line, but is formed separately from the storage node contact plug to complicate the process. On the other hand, the pads of the storage node contacts, the contact plugs, and the storage nodes are all formed of polysilicon. When annealing is required to increase conductivity, thermal processing is burdened, and an interface resistance increases at an interface at which each polysilicon layer is connected to each other. There was a problem.

The present invention is to improve the problems as described above in the process using the above stud, the process is simple, DRAM device that can reduce the problem of annealing and the interface resistance between the polysilicon layer due to the polysilicon layer formation It is an object to provide a manufacturing method.

1 is a cross-sectional view showing an example in which a stud is used in forming a conventional DRAM device.

2 to 4 are process cross-sectional views showing each step of the manufacturing process of the DRAM device according to the present invention.

In the DRAM device manufacturing method using a stud for achieving the above object, in manufacturing a COB (Capacitor Over Bit line) DRAM, forming a bit line and a bit line contact, stacking an interlayer insulating film over the bit line, Forming a storage node contact hole and a stud hole, and simultaneously forming a contact plug and a stud by stacking conductive layers in a state where the storage node contact hole and the stud hole are formed.

In the present invention, the conductive layer usually consists of a barrier layer and a metal layer such as CVD tungsten.

In the present invention, it is common to form contact pads filled with polysilicon plugs in the storage node contact region of the cell, in advance of the steps of the present invention. Then, in the state in which the strip node contact plug is formed, a strip node made of polysilicon is formed. The storage node is formed in a cylindrical shape using a molding film to secure the capacitor capacity, and the HSG is generally formed, but is not limited thereto.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

2 to 4 are process cross-sectional views showing each step of the manufacturing process of the DRAM device according to the present invention. Each figure shows a comparison of the areas where studs are formed, usually the periphery and core areas, and the cell areas where storage nodes are formed in the same process step.

Referring to FIG. 2, an isolation layer 11 is first formed on a substrate 10, a gate insulating layer and gate patterns 12 and 12 ′ are formed, and a source / drain is formed to have a MOS transistor structure. The interlayer insulating layer 13 is stacked, and contact pads 15 for storage node contacts are formed in the cell region. The contact pad 15 is generally formed in a self-aligning manner by using a silicon nitride film capping layer covering the gate electrode and a spacer. The contact pad 15 may be formed by etching the interlayer insulating layer 13 in the region where the contact hole is formed by etching, filling the polysilicon layer, and then removing the polysilicon layer remaining above the interlayer insulating layer 13 by the planarization etching. have.

Then, the bit line 19 and the bit line contact 17 are formed. The bit line 19 and the bit line contact 17 may use tungsten metal to increase conductivity. In this case, a bit line contact hole is formed in the interlayer insulating layer 13, and a titanium / titanium nitride layer is formed as a barrier layer. CVD tungsten is deposited and patterned to form plugs and bitlines. In the drawing, when the bit line 19 and the bit line contact 17 are formed by forming a bit line space in the interlayer insulating layer 13 in advance using a dual damascene process, filling the barrier layer and tungsten layer, and planarizing etching. Indicates.

Referring to FIG. 3, the insulating film 20 and the etch stop layer 22 are covered on the substrate 10 on which the bit lines 19 and the contact pads 15 are formed, and the strip node contact plugs 124 and the studs are formed in the cell region. Stud 126 is formed in the region. The contact plugs 124 and the studs 126 form holes in the insulating film 20 and the etch stop layer 22 through respective patterning, or simultaneously fill the holes by stacking the barrier layer and the tungsten layer while the holes are formed. It is made by a method of planar etching such as CMP. Therefore, by filling the holes with the same material at one time, the process step is reduced compared to the conventional case, and the interface resistance between the pad 15 and the polysilicon layer of the contact plug 24 at the storage node contact may have an unnecessary effect. Can be.

Referring to FIG. 4, in order to form a storage node in a cell region, a barrier layer 127 ′ may be formed in a state in which a molding layer 128 is stacked with a silicon oxide layer and a storage node hole is formed to expose a storage node contact plug 124. Polysilicon layers are laminated. The barrier layer 127 ′ is stacked to prevent a problem caused by diffusion of the polysilicon layer and the tungsten forming the storage node contact plug 124. The barrier layer 127 ′ is formed of a conventional titanium / titanium nitride film or a titanium nitride film.

Planar etching is performed through CMP to remove polysilicon deposited on the molding layer 128. Thus, storage node 127 is formed by separation of storage node 127. In the region where the stud 126 is formed, the molding film 128 remains to remove the step. The storage node 127 is completed through a process of forming the HSG 130 in the storage node 127, and a thin dielectric layer 132 is formed on the entire substrate. In addition, polysilicon is stacked to form a plate electrode 134.

Meanwhile, the plate electrode layer is removed in the periphery and the core region where the stud 126 is formed. Then, the insulating film 136 is laminated as a whole. A contact hole subsequent to the stud is formed in the stud region over the insulating layer 136. In addition, the barrier layer and the wiring layer made of CVD tungsten are stacked and patterned to form the wiring contact plug 138 and the wiring 140.

According to the present invention, in the method of manufacturing a DRAM device in which a stud is formed, the process is simplified by simultaneously forming a plug of the same material as the stud when forming a storage contact formed at the same or similar level as the stud, and forming a polysilicon layer. The problem of annealing and interfacial resistance between the polysilicon layers can be reduced.

Claims (6)

In the manufacture of a COB (Capacitor Over Bit line) DRAM device, Forming a bit line and a bit line contact on a substrate including a MOS transistor structure and having an interlayer insulating film stacked over the MOS transistor structure; Stacking an interlayer insulating film over the bit line; Selectively etching the interlayer insulating layer to form a storage node contact hole and a stud hole; And forming a contact plug and a stud at the same time by stacking a conductive layer in a state where the contact hole and the stud hole are formed. The method of claim 1, The conductive layer is a method for manufacturing a DRAM device, characterized in that formed by laminating a barrier layer and a CVD tungsten layer in sequence. The method of claim 1, Planarization etching the conductive layer; Forming a molding for the storage node in the cell area, And forming a storage node layer. The method of claim 3, wherein The storage node film is a method of manufacturing a DRAM device, characterized in that formed by laminating a barrier layer and a polysilicon layer. The method of claim 1, And forming a contact pad in a cell region after forming the interlayer insulating layer and before forming the bit line and the bit line contact. The method of claim 1, Selectively etching the interlayer insulating layer to form a storage node contact hole and a stud hole using a single exposure mask.