KR20020019739A - Anti-fuse and method for fabricating the same - Google Patents

Abstract

PURPOSE: An anti-fuse and a method for fabricating the same are provided to operate stably an anti-fuse by distributing an electric field of a lower portion of an amorphous silicon layer between the first and the second metal layers. CONSTITUTION: An interlayer dielectric(32) is deposited on an upper portion of the first metal layer(31). A photoresist layer is applied on the interlayer dielectric(32). The photoresist layer is patterned selectively by performing an exposure process and a developing process. The first via hole is formed by etching the interlayer dielectric(32) and the first metal layer(31). The photoresist layer is removed. A photoresist layer is applied on a whole surface of the above structure. The photoresist layer is patterned by performing the exposure process and the developing process. The second via hole is formed by etching the interlayer dielectric(32). An amorphous silicon is deposited thereon. An amorphous silicon(34) is formed by performing a lithography process. An anti-fuse is completed by sputtering the second metal layer(35) on the interlayer dielectric(32).

Description

Anti-fuse and its manufacturing method {ANTI-FUSE AND METHOD FOR FABRICATING THE SAME}

The present invention relates to a semiconductor device, and more particularly, to an antifuse in a field programmable gate array (FPGA) and a method of manufacturing the same.

Referring to the accompanying drawings, a method for manufacturing a conventional anti-fuse is as follows.

1A to 1C are cross-sectional views illustrating a method of manufacturing a conventional anti-fuse.

In the conventional method of manufacturing an antifuse, an interlayer insulating film 2 is deposited on the first metal layer 1 and a photosensitive film 3 is applied on the interlayer insulating film 2 as shown in FIG. 1A.

Subsequently, the photoresist film 3 is selectively patterned so that only an area for forming a via hole is removed by an exposure and development process.

1B, via holes are formed by etching the interlayer insulating layer 2 so that the center portion of the first metal layer 1 is exposed using the patterned photoresist 3 as a mask. Thereafter, the photosensitive film 3 is removed.

Next, after the amorphous silicon layer 4 is deposited on the entire surface including the via hole, the amorphous silicon layer 4 is anisotropically etched so as to remain only on the interlayer insulating film 2 in the via hole and adjacent thereto.

Next, as shown in FIG. 1C, the second metal layer 5 is formed on the interlayer insulating film 2 including the amorphous silicon layer 4.

At this time, a high field is applied only to the lower edge portion of the via hole indicated by the dotted line. That is, the electric field is concentrated only at the lower edge portion of the via hole.

The conventional method of manufacturing the anti-fuse as described above has the following problems.

The electric field is concentrated in the lower portion of the amorphous silicon layer provided between the first and second metal layers, which causes the operation of the fuse to be unstable.

The present invention has been made to solve the above problems, in particular, anti-fuse that can be operated stably by dispersing the electric field applied to the lower portion of the amorphous silicon layer provided between the first, second metal layer and its manufacturing method The purpose is to provide.

1A to 1C are cross-sectional views illustrating a method of manufacturing a conventional anti-fuse.

2A to 2E are cross-sectional views illustrating a method of manufacturing the antifuse of the present invention.

Explanation of symbols for the main parts of the drawings

31 first metal layer 32 interlayer insulating film

33: photosensitive film 34: amorphous silicon layer

35: second metal layer

The anti-fuse of the present invention for achieving the above object is an interlayer insulating film having a via hole having a wider width than an etched portion of the first metal layer, the first metal layer over-etched to a predetermined width, the first etched first And a second metal layer formed on the interlayer insulating film including the semiconductor layer, the semiconductor layer formed on the metal layer, the via hole, and the interlayer insulating film adjacent thereto.

The method of manufacturing an anti-fuse according to the present invention having the above structure includes depositing an interlayer insulating film on a first metal layer, forming a first via hole in the interlayer insulating film by overetching an upper region of the first metal layer, Forming a second via hole in the interlayer insulating film so as to have a width wider than that of the first via hole, forming a semiconductor layer on the first and second via holes and the interlayer insulating film adjacent to the first via hole, and forming a semiconductor layer on the entire surface including the semiconductor layer. It characterized by the process of forming a 2 metal layer.

Antifuse is the opposite concept of fuses, which are initially made "OFF" and then turned "ON" by a program. In other words, during the initial production, the antifuse is an insulator having an electrical resistance of several M ohms or more, and has an electrical resistance of several hundred ohms or less by a program, and is in an "ON" state.

The program is made by insulator breaking down when a certain level of voltage is applied between two electrodes, i.e., between the first conductive layer and the second conductive layer.

Field Programmable Gate Array (FPGA) is a kind of semi-custom logic integrated circuit that has short development period and low development cost compared to standard logic IC. That is, by arranging the gates, which are basic logic elements, in parallel as a unit, and forming logic circuits according to the wiring, a circuit of a type required by a user can be made.

In an FPGA, antifuse is formed of amorphous silicon between two electrically separated conductors. The resistance of amorphous silicon is high, so it is normally insulated and selectively applies an electric field to both conductors as needed. Amorphous silicon is melted and the two conducting wires are connected and used as a gate array.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

2A to 2E are cross-sectional views illustrating a method of manufacturing the antifuse of the present invention.

The antifuse according to the present invention in the above-described FPGA has a first metal layer 31 overetched with a constant width in a central area, as shown in FIG. 2E, and the etched width of the first metal layer 31. The interlayer insulating film 32 is formed to have a wider via hole.

In this case, the overetched portion of the first metal layer 31 and the via hole of the interlayer insulating layer 32 have stepped steps.

An amorphous silicon layer 34 is formed on the etched portion of the stepped first metal layer 31, the via hole side of the interlayer insulating layer 32, and the interlayer insulating layer 32 adjacent thereto. That is, the amorphous silicon layer 34 has a stepped shape symmetrically in cross section with respect to the central portion of the etched first metal layer 31.

At this time, the amorphous silicon layer 34 is dispersed in the lower edge of the over-etched first metal layer 31 and the lower edge of the via hole of the interlayer insulating layer 32. This is because the electric field is dispersed in comparison with the electric field concentrated only at the lower edge of the via hole of the interlayer insulating film 32.

A second metal layer 35 is formed on the interlayer insulating film 35 including the amorphous silicon layer 34.

In the method of manufacturing the anti-fuse of the present invention having the above configuration, as shown in FIG. 2A, the interlayer dielectric layer 32 is deposited on the first metal layer 31, and the photoresist layer 33 is deposited on the interlayer dielectric layer 32. Apply.

Subsequently, the photoresist layer 33 is selectively patterned so that only an area for forming the first via hole is removed by an exposure and development process.

As shown in FIG. 2B, the interlayer insulating layer 32 and the first metal layer 31 are etched to form a first via hole using the patterned photoresist 33 as a mask so that the central portion of the first metal layer 31 is excessively etched. .

Next, after the photoresist film 32 is removed, the photoresist film is applied to the entire surface including the first via hole, although not shown in the drawing. After the photoresist film is patterned by an exposure and development process to have a width larger than that of the first via hole, the patterned photoresist film is used as a mask. The interlayer insulating layer 32 is anisotropically etched to form a second via hole having a width larger than that of the first via hole as shown in FIG. 2C.

By this process, a stepped via hole is formed.

As shown in FIG. 2D, after depositing amorphous silicon, a lithography process is performed to remain on the stepped via hole and the interlayer insulating layer 32 adjacent thereto, that is, to remain only in the fuse region. 34).

Next, as shown in FIG. 2E, the second metal layer 35 is sputtered on the interlayer insulating film 32 including the amorphous silicon 34 to complete the fuse.

At this time, the cross section is distributed to four edges of each edge region of the stepped via hole represented by a dotted line, that is, two on one side, and a high field is generated.

The present invention anti-fuse as described above and its manufacturing method has the following effects.

By forming the amorphous silicon of the anti-fuse in a step shape, the electric field of the edge portion can be dispersed, so that the operation of the fuse can be performed stably.

Claims (6)

The first metal layer overetched with a predetermined width at an upper portion, An interlayer insulating film having a via hole having a width wider than that of the etched portion of the first metal layer; A semiconductor layer formed on the etched first metal layer, the via hole, and the interlayer insulating layer adjacent thereto; And a second metal layer formed on the interlayer insulating film including the semiconductor layer. The anti-fuse of claim 1, wherein the semiconductor layer has a stepped shape symmetrical with respect to a center portion of the etched first metal layer. The antifuse of claim 1, wherein the semiconductor layer is formed of an amorphous silicon layer. Depositing an interlayer insulating film on the first metal layer, Forming a first via hole in the interlayer insulating layer by over-etching an upper region of the first metal layer; Forming a second via hole in the interlayer insulating film to have a width wider than that of the first via hole, Forming a semiconductor layer on the first and second via holes and an interlayer insulating film adjacent thereto; Forming a second metal layer on the entire surface including the semiconductor layer. The method of claim 4, wherein the first and second via holes are formed to have a stepped shape. The method of claim 4, wherein the semiconductor layer is formed of an amorphous silicon layer.