KR20020019380A - Delay Locked Loop circuit reducing load of variable delay unit at high frequency operation and locking external clock stably - Google Patents

Abstract

PURPOSE: A delay synchronous circuit for reducing a load of a variable delay portion and a synchronizing stably with an outer clock in a high frequency operating process is provided to reduce a load of an output line of a variable delay portion in a high frequency operating process. CONSTITUTION: A variable delay portion(300) is used instead of a variable delay portion of a delay synchronous circuit. A phase detector and a delay portion controller are used as components of the delay synchronous circuit. The variable delay portion(300) the first group of delay elements(301-304), the second group(305-308), switch transistors(311-318), and a switch(320). The first output line(OL2) is used in a high frequency operating process. The first and the second output lines(OL2,OL3) are used in a low frequency operating process. The first group of delay elements(301-304) are used in the high frequency operating process. The first and the second group of delay elements(301-304)(305-308) are used in the ow frequency operating process. The switch(320) is arranged between the first and the second output lines(OL2,OL3). The switch(320) is controlled by the delay element(304).

Description

Delay locked circuit reduces load of variable delay unit at high frequency operation and locking external clock stably

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a delay synchronization circuit that reduces the load of the variable delay stage and stably synchronizes an external clock during high frequency operation of a delay synchronization circuit.

A synchronous DRAM synchronizes with a clock to input data into a memory cell or to output memory cell data during a valid data window. The clock is input to one pin and distributed to the synchronous DRAM, with the clock reaching a portion relatively far from the input pin can be significantly delayed compared to the clock of the portion adjacent to the input pin. This delay makes it difficult to maintain synchronization between the parts of the synchronous DRAM.

A delay synchronization circuit is used to maintain this synchronization, which generates an internal clock that is synchronized with the phase of the external clock. The delay synchronization circuit operates at almost the same speed as the operation speed of the synchronous DRAM. The delay synchronization circuit must satisfy the case of operating above a predetermined frequency (hereinafter referred to as high frequency operation) and the case of operating below the frequency (hereinafter referred to as low frequency operation).

1 is a diagram illustrating a general delay synchronization circuit 100. The delay synchronization circuit 100 includes a phase detector 110, a delay stage controller 120, and a variable delay unit 130. The phase detector 110 detects a phase difference between the external clock ECLK and the internal clock ICLK. The delay stage controller 120 generates a control signal CNT for determining a delay time of the external clock ECLK input to the variable delay stage 130 in response to the output of the phase detector 110. The variable delay stage 130 generates an internal clock ICLK synchronized with the external clock ECLK in response to the control signal CNT.

2 is a diagram illustrating the variable delay end 130 of FIG. 1. The variable delay stage 130 includes delay elements 201 to 208 and switch transistors 211 to 218. Each of the delay elements 201 to 208 is connected to the switch transistors 211 to 218, and the switch transistors 211 to 218 are connected to the output line OL1 of the variable delay stage 130. The delay elements 201 to 208 delay the external clock ECLK.

On the other hand, the number of delay elements 201 to 208 is related to the operating frequency of the delay synchronization circuit 100 of FIG. The number of delay elements in the high frequency operation is set to be smaller than in the low frequency operation. In the case of low frequency operation, since all the switch transistors 211 to 218 are turned on in response to the control signal CNT, all the delay elements 201 to 208 are connected to the output line OL1, so that the output line OL1 is Have a large load. On the other hand, in the case of the high frequency operation, the parts 205 to 208 of the delay elements 201 to 208 are turned off in response to the control signal CNT and thus are not connected to the output terminal of the variable delay stage 130. OL1 has a relatively small load.

However, in the variable delay stage 130 of FIG. 2, even if the delay elements 205 to 208 are not connected to the output line OL1 for high frequency operation, the variable delay stage 130 is turned off with the line load of the physical length of the output line OL1. The junction load of the switch transistors 215 to 218 may be maintained. Thus, the variable delay stage 130 is not suitable for high frequency operation. Accordingly, jitter is generated in the internal clock ICLK finally generated in the delay synchronization circuits (FIGS. 1 and 100) and the duty characteristic is deteriorated. Thus, there is a problem that the entire synchronous DRAM operating based on this is malfunctioning.

An object of the present invention is to provide a delay synchronization circuit that can reduce the output line load of the variable delay stage during high frequency operation.

Another object of the present invention is to provide a delay synchronization circuit for stably performing connection / disconnection of a switch included in the variable delay stage.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 is a diagram illustrating a general delay synchronization circuit.

FIG. 2 is a diagram illustrating the variable delay end of FIG. 1.

3 is a view showing a variable delay stage according to an embodiment of the present invention.

4 is a diagram illustrating a variable delay stage according to another embodiment of the present invention.

FIG. 5 is a diagram illustrating a configuration of the control circuit of FIG. 4.

6 is a timing diagram illustrating an operation of the control circuit of FIG. 4.

FIG. 7 is a diagram illustrating a configuration of the reset circuit of FIG. 4.

8 is a diagram illustrating a variable delay stage according to another embodiment of the present invention.

9 is a diagram illustrating a configuration of the control circuit of FIG. 8.

In order to achieve the above object, the delay synchronization circuit of the present invention includes a phase detector for detecting a phase difference between an external clock and an internal clock, a delay stage controller for generating a control signal in response to an output of the phase detector, and a response to the control signal. And a variable delay stage for delaying the external clock to generate the internal clock synchronized with the external clock. The variable delay stage includes a first group of delay elements used above a predetermined frequency, a second group of delay elements used together with the first group of delay elements below a predetermined frequency, and the control signal. In response, switch transistors for coupling / disconnecting the delay elements of the first group and the delay elements of the second group to the first output line of the variable delay stage and the second output line of the variable delay stage, respectively; And a switch for connecting / disconnecting the first output line and the second output line in response to a delay use signal indicating use of one of the first group of delay elements.

In order to achieve the above object, the delay synchronization circuit of the present invention includes a phase detector for detecting a phase difference between an external clock and an internal clock, a delay stage controller for generating a control signal in response to an output of the phase detector, and the control signal. And responsive to the external clock in response to the variable delay stage generating the internal clock in synchronization with the external clock. The variable delay stage includes a first group of delay elements used above a predetermined frequency, a second group of delay elements used together with the first group of delay elements below the frequency, and the control signal. In response, switch transistors respectively connecting / disconnecting the delay group of the first group and the delay element of the second group to the first output line of the variable delay stage and the second output line of the variable delay stage; Connection / disconnection of the switch in response to a switch for connecting / disconnecting the first output line and the second output line, and a delay use signal and a reset signal indicating use of one of the first group of delay elements. It includes a control circuit for controlling.

In order to achieve the above object, the delay synchronization circuit of the present invention includes a phase detector for detecting a phase difference between an external clock and an internal clock, a delay stage controller for generating a control signal in response to an output of the phase detector, and the control signal. And responsive to the external clock in response to the variable delay stage for generating the internal clock in synchronization with the external clock. The variable delay stage includes a first group of delay elements used above a predetermined frequency, a second group of delay elements used together with the first group of delay elements below the frequency, and the control signal. In response, switch transistors respectively connecting / disconnecting the delay group of the first group and the delay element of the second group to the first output line of the variable delay stage and the second output line of the variable delay stage; A switch for connecting / disconnecting the first output line and the second output line, and a control circuit for controlling connection / disconnection of the switch in response to delay change signals indicating a change in the number of delay elements in use. do.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements.

3 is a view showing a variable delay stage 300 according to an embodiment of the present invention. The variable delay stage 300 is used in place of the variable delay stage 130 of the delay synchronization circuit 100 of FIG. 1, and the phase detector 110 and the delay stage controller 120 may be configured by the components of the delay synchronization circuit of the present invention. do. The variable delay stage 300 includes a first group of delay elements 301 to 304, a second group of delay elements 305 to 308, switch transistors 311 to 318, and a switch 320. Compared with the variable delay stage 130 of FIG. 1, the variable delay stage 300 further includes a switch 320.

The first output line OL2 is used for the high frequency operation, and the first output line OL2 and the second output line OL3 are used for the low frequency operation.

The first group of delay elements 301-304 are used in high frequency operation, and the second group of delay elements 305-308 are used in low frequency operation together with the first group of delay elements 301, 302, 303, 304. The switch transistors 311 to 318 respectively transmit the delayed external clock ECLK to the first output line OL2 and the second output line in response to the control signal CNT generated by the delay stage controller 120 of FIG. 1. To OL3.

The switch 320 is disposed between the first output line OL2 and the second output line OL3. The switch 320 is controlled by a delay element, for example a delay element 304, disposed just in front of where the switch 320 is located. The delay element 304 corresponds to the last delay element of the first group of delay elements used in the high frequency operation. The delay usage signal DMAX indicative of the use of delay element 304 implies low frequency operation. When the switch 320 is turned on to perform the low frequency operation, the load of the output lines OL2 and OL3 is increased.

On the other hand, the switch 320 may also be controlled by a delay use signal (DMAX) indicating the use of a delay element disposed in front of at least one where the switch 320 is located. In the embodiment of the present invention, it is shown that the switch 320 is controlled by the delay use signal DMAX indicating the use of the delay element 302. When the high frequency operation is performed, a change in the power supply voltage and a temperature change may occur according to the operation of the semiconductor memory device. Therefore, it is necessary to further connect a delay element to the first output line OL2 of the variable delay stage 300, but to have a margin by leaving the delay elements 303 and 304 after the delay element 302. do.

Therefore, when the delay synchronization circuit of the present invention including the variable delay stage 300 performs a high frequency operation, the second output line OL3 to which the switch transistors 315 to 318 are connected is separated and the first output line ( The load on OL2) is reduced. Thus, in the delay synchronization circuit of the present invention, high frequency operation can be performed stably.

On the other hand, when the delay synchronization circuit according to an embodiment of the present invention performs a low frequency operation using one of the first group of delay elements (301 to 304) and the second group of delay elements (305 to 308) Voltage changes and temperature changes due to noise can increase the delay time of the delay device. Then, since the last delay element 304 of the first group of delay elements 301 to 304 repeats on / off, the switch 320 repeatedly turns on / off to increase the discontinuity of the switch. As a result, jitter is generated at the output line OL2 of the variable delay stage 300 and noise noise is reduced.

A delay synchronization circuit according to another embodiment of the present invention for preventing the discontinuity of the switch 320 is described below. The delay synchronization circuit according to another embodiment of the present invention keeps the on state when the switch is turned on, and turns off the switch only by the reset signal.

4 is a diagram illustrating a variable delay stage according to another embodiment of the present invention. The variable delay stage 400 is used in place of the variable delay stage 130 of the delay synchronization circuit 100 of FIG. 1, and the phase detector 110 and the delay stage controller 120 of FIG. Components.

Referring to FIG. 4, the variable delay stage 400 may include a first group of delay elements 401 to 404, a second group of delay elements 405 to 408, switch transistors 411 to 418, and a switch ( 420, a precharging circuit 430, a control circuit 440, and a reset circuit 470. Compared with the variable delay stage 300 of FIG. 3, the variable delay stage 400 further includes a precharging circuit 430, a control circuit 440, and a reset circuit 470. The descriptions of the delay elements 401 to 408 and the switch transistors 411 to 418 are omitted because they are the same as those of FIG. 3.

In the case of high frequency operation, the first output line OL4 is used, and in the case of low frequency operation, the first output line OL4 and the second output line OL5 are used.

The switch 420 connects / disconnects the first output line OL4 of the variable delay stage 400 and the second output line OL5 of the variable delay stage 400 in response to the switch control signal SW1. The switch 420 has a PMOS transistor.

The precharging circuit 430 precharges the potential of the second output line OL5 as the power supply voltage VCC in response to the precharging signal PC1. The precharging circuit 430 includes a PMOS transistor connected to a source voltage VCC.

The control circuit 440 outputs the switch control signal SW1 and the precharge signal PC1 in response to the delay use signal DMAX and the reset signal RS. The delay use signal DMAX is a signal indicating that the delay element 404 uses a predetermined delay time, and the reset signal RS is a signal for controlling the separation of the switch 420. In an embodiment of the present invention, the delay element 402 may generate the delay use signal DMAX.

The reset circuit 470 outputs the reset signal RS in response to the external reset command RS_CMD, the up signal UP, and the down signal DOWN. The external reset command RS_CMD is a signal for controlling the separation of the switch 420 from the outside. The up signal UP is a signal indicating an increase in the number of delay elements in use, and a down signal DOWN is a signal indicating a decrease in the number of delay elements in operation. The up signal UP and the down signal DOWN may be generated from separate control circuits (not shown).

FIG. 5 is a diagram illustrating a configuration of the control circuit of FIG. 4. Referring to FIG. 5, the control circuit 440 includes a latch portion 441 and inverters 443 and 445. The latch portion 441 includes two NOR gates.

The latch unit 441 sets the output terminal NO of the latch unit 441 in response to the delay use signal DMAX, and resets the output terminal NO in response to the reset signal RS. . The inverter 443 inverts the signal of the output terminal NO to generate the precharge signal PC1, and the inverter 445 inverts the precharge signal PC1 to generate the switch control signal SW1.

6 is a timing diagram illustrating an operation of the control circuit of FIG. 4. Referring to FIG. 6, the high frequency operation period and the low frequency operation period are divided and illustrated. When the reset signal RS is activated, the delay use signal DMAX is deactivated. Then, the precharging signal PC1 is activated to perform precharging, the switch control signal SW1 is deactivated so that the switch 420 is turned off, and the high frequency operation is performed. That is, the delay synchronization circuit of the present invention generates an internal clock that is synchronized with an external clock of high frequency.

Thereafter, as the frequency of the external clock ECLK decreases, the delay element 404 of FIG. 4 operates to activate the delay use signal DMAX. Then, the precharging signal PC1 is deactivated to release the precharging, the switch control signal SW1 is activated, the switch 420 is turned on, and the low frequency operation is performed.

Accordingly, the delay synchronization circuit of the present invention including the variable delay stage 400 stably controls the connection / disconnection of the switch by the reset signal RS so that the operation change between the low frequency operation and the high frequency operation can be stably repeated. have.

FIG. 7 is a diagram illustrating a configuration of the reset circuit of FIG. 4. Referring to FIG. 7, the reset circuit 470 includes an up signal detection circuit 471, a down signal detection circuit 473, and a logic sum circuit 475. The up signal detection circuit 471 and the down signal detection circuit 473 include a counter.

The up signal detection circuit 471 counts the number of successive up signals UP, which indicates the number of delay elements, and activates a "high" state when the number of up signals UP is exceeded.

The down signal detection circuit 473 counts the number of consecutive down signals DOWN representing the number of decreases of the delay elements, and activates the "high" state when the number of predetermined down signals DOWN is exceeded.

The logic sum circuit 475 generates a reset signal RS when the external reset command RS_CMD, the output of the up signal detection circuit 471 and the output of the down signal detection circuit 473 are activated to the "high" state.

8 is a diagram illustrating a variable delay stage according to another embodiment of the present invention. The variable delay stage 800 of the present invention includes a first group of delay elements 801 to 804, a second group of delay elements 805 to 808, switch transistors 811 to 818, a switch 820, The precharging circuit 830 and the control circuit 840 are included.

In the case of high frequency operation, the first output line OL6 is used, and in the case of low frequency operation, the first output line OL6 and the second output line OL7 are used.

Since the switch 820 and the precharging circuit 830 are almost the same as those of the switch 420 and the precharging circuit 430 of FIG. 4, description thereof will be omitted. The potential of the second output line OL7 is precharged as the power supply voltage VCC by the precharging circuit 830.

The control circuit 840 precharges the switch control signal SW2 and the second output line OL7 for controlling the connection / disconnection of the switch 820 in response to the up signal UP and the down signal DOWN. The precharging signal PC2 is output. The up signal UP is a signal indicating an increase in the number of delay elements, and the down signal DOWN is a signal indicating a decrease in the number of delay elements. That is, the control circuit 840 detects the frequency change of the external clock ECLK and controls the switch 820 and the precharging circuit 830.

9 is a diagram illustrating a configuration of the control circuit of FIG. 8. 9 shows examples of signal waveforms appearing at the input / output stage of the delay detection circuit 841 and at the output stage of the Schmitt trigger buffer 843. Referring to FIG. 9, the control circuit 840 includes a delay detection circuit 841, a Schmitt trigger buffer 843, and an inverter 845.

The delay detection circuit 841 outputs a variable voltage that is proportional to the number of the up signals UP and inversely proportional to the number of the down signals DOWN. The delay detection circuit 841 includes a charge pump.

The Schmitt trigger buffer 843 outputs more than the first voltage Vm + of the variable voltage as the first voltage Vm +, and outputs less than the second voltage Vm- of the variable voltage as the ground voltage. The variable voltages Vm− to Vm + between the first and second voltages are hysteresis voltages, and the delay change corresponding to the hysteresis voltages is ignored. The first voltage Vm + is set to a threshold voltage indicating a change from high frequency operation to a low frequency operation, and the second voltage Vm− is set to a threshold voltage indicating a change from low frequency operation to a high frequency operation.

The output of the Schmitt trigger buffer 843 becomes the precharge signal PC2, and the output of the Schmitt trigger buffer 843 is inverted by the inverter 845 to become the switching signal SW2.

Referring to the signal diagram appearing at the input / output terminal of the Schmitt trigger buffer 843, the output of the Schmitt trigger buffer 843 is "low" until the time T0 so that the switch 820 is turned off. The second output line OL7 is precharged. At this time, a high frequency operation is performed. The output of the Schmitt trigger buffer 843 becomes a "high" state from the time T0 to the time T1 so that the switch 820 is turned on and the precharging of the second output line OL7 is released. . In this case, low frequency operation is performed. The output of the Schmitt trigger buffer 843 begins to descend to the "low" state at time T1, and high frequency operation is performed.

Therefore, the delay synchronization circuit of the present invention including the variable delay stage 800 can stably perform the connection / disconnection of the switch by ignoring the delay change corresponding to the hysteresis voltage. Therefore, even if the frequency of the external clock is changed between the high frequency and the low frequency, the delay synchronization circuit of the present invention can perform a stable operation at each operating frequency.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

The delay synchronization circuit of the present invention reduces the load on the output line by switching off in the case of high frequency operation, thereby stably performing high frequency operation.

In addition, the delay synchronization circuit of the present invention can stably control the connection / disconnection of the switch to reduce the discontinuity of the switch, the operation change between high frequency operation and low frequency operation can be performed stably.

Claims (17)

A phase detector for detecting a phase difference between the external clock and the internal clock; A delay stage controller configured to generate a control signal in response to the output of the phase detector; And A variable delay stage for delaying the external clock in response to the control signal to generate the internal clock in synchronization with the external clock; The variable delay end A first group of delay elements used above a predetermined frequency; A second group of delay elements used together with the first group of delay elements below a predetermined frequency; A switch for connecting / disconnecting the delay elements of the first group and the delay elements of the second group to the first output line of the variable delay stage and the second output line of the variable delay stage, respectively, in response to the control signal. Transistors; And And a switch for connecting / disconnecting the first output line and the second output line in response to a delay use signal indicating use of one of the delay groups of the first group. The method of claim 1, wherein the delay usage signal is And a signal indicative of the use of said delay element disposed immediately in front of where said switch is located. The method of claim 1, wherein the delay usage signal is And a signal indicative of the use of said delay element disposed at least one in front of said switch. A phase detector for detecting a phase difference between the external clock and the internal clock; A delay stage controller configured to generate a control signal in response to the output of the phase detector; And A variable delay stage for delaying the external clock in response to the control signal to generate the internal clock in synchronization with the external clock; The variable delay end A first group of delay elements used above a predetermined frequency; A second group of delay elements used together with the first group of delay elements below the frequency; In response to the control signal, a switch for connecting / disconnecting the delay elements of the first group and the delay elements of the second group to the first output line of the variable delay stage and the second output line of the variable delay stage, respectively. Transistors; A switch connecting / disconnecting the first output line and the second output line; And And a control circuit for controlling connection / disconnection of the switch in response to a delay use signal and a reset signal indicating use of one of the first group of delay elements. The method of claim 4, wherein the variable delay end And a reset circuit for generating the reset signal in response to an external reset command, an up signal indicating an increase in the number of delay elements, and a down signal indicating a decrease in the number of delay elements. The method of claim 4, wherein the variable delay end And a precharging circuit for precharging the potential of the second output line as a power supply voltage in response to the precharging signal output from the control circuit. The method of claim 4, wherein the control circuit A latch unit configured to set an output terminal in response to the delay use signal, and reset the output terminal in response to the reset signal; And And a buffer for generating a switch control signal for controlling the switch in response to the output of the latch portion. The method of claim 5, wherein the reset circuit An up signal detection circuit that counts the up signal and activates an output when the counted value is equal to or greater than a predetermined count value; A down signal detection circuit that counts the down signal and activates an output when a count value is equal to or greater than a predetermined count value; And And a logic sum circuit for generating the reset signal in response to the external reset command, the output of the up signal detection circuit, and the output of the down signal detection circuit. The method of claim 8, The up signal detecting circuit and the down signal detecting circuit each comprise a counter. The method of claim 6, wherein the precharging circuit A delay synchronization circuit comprising a PMOS transistor. The switch according to any one of claims 4 to 10, wherein the switch is A delay synchronization circuit comprising a PMOS transistor. A phase detector for detecting a phase difference between the external clock and the internal clock; A delay stage controller configured to generate a control signal in response to the output of the phase detector; And A variable delay stage for delaying the external clock in response to the control signal to generate the internal clock in synchronization with the external clock; The variable delay end A first group of delay elements used above a predetermined frequency; A second group of delay elements used together with the first group of delay elements below the frequency; In response to the control signal, a switch for connecting / disconnecting the delay elements of the first group and the delay elements of the second group to the first output line of the variable delay stage and the second output line of the variable delay stage, respectively. Transistors; A switch connecting / disconnecting the first output line and the second output line; And And a control circuit for controlling connection / disconnection of the switch in response to delay change signals indicating a change in the number of delay elements in use. The method of claim 12, wherein the variable delay end And a precharging circuit for precharging the potential of the second output line as a power supply voltage in response to the precharging signal output from the control circuit. The method of claim 12 or 13, wherein the control circuit A delay detection circuit configured to generate a variable voltage in response to an up signal indicating an increase in the number of delay elements among the delay change signals and a down signal indicating a decrease in the number of delay elements among the delay change signals; A Schmitt trigger buffer for generating the precharging signal by outputting the first voltage or more of the variable voltage as the first voltage and outputting the ground voltage less than or equal to the second voltage of the variable voltage; And And an inverter for inverting the precharging signal and generating a switch control signal for controlling the switch. The method of claim 13, wherein the precharging circuit A delay synchronization circuit comprising a PMOS transistor. The method of claim 14, wherein the delay detection circuit A delay synchronization circuit comprising a charge pump. The method of claim 14, wherein the switch A delay synchronization circuit comprising a PMOS transistor.