KR20020018313A - Layout of sub wordline driver in dynamic random access memory - Google Patents

Abstract

PURPOSE: A sub-word line driver layout is provided to be capable of minimizing a circuit area of a sub-word line driver. CONSTITUTION: A sub-word line driver drives word lines of a memory cell array, which includes a plurality of word lines and a plurality of bit lines arranged in a lattice shape, in response to a signal from a row decoder. The sub-word line driver includes the first transistor and the second transistor. The first transistor is connected between the first signal from the row decoder and a node(230B), and is controlled by a power supply voltage. The second transistor is connected between the second signal from the row decoder and a word line, and is controlled by a signal on the first node. An active region of the first transistor and a gate of the second transistor are formed in a different layer from the bit lines(220A, 220B).

Description

LAYOUT OF SUB WORDLINE DRIVER IN DYNAMIC RANDOM ACCESS MEMORY}

The present invention relates to a sub wordline driver (SWD) of a dynamic random access memory (DRAM), and more particularly, to a sub wordline driver layout for reducing a semiconductor chip size. It is about.

The configuration of a conventional DRAM having a sub wordline driver is shown in FIG.

Referring to FIG. 1, the DRAM includes a row decoder 10, a sub word line driver 20, and a memory cell array 30. In FIG. 1, one bit line BL, one word line WL, and one memory cell are displayed on the memory cell array 30, but as is well known, the memory cell array 30 has a lattice shape. A plurality of bit lines and word lines arranged to cross each other and a plurality of memory cells connected to the bit lines and word lines, respectively. One memory cell includes a transistor 32 and a capacitor 34 connected to a bit line BL and a word line WL. The row decoder 10 outputs signals for sequentially selecting the word lines in response to row address signals input from the outside.

The sub word line driver 20 outputs a signal for driving the word line in response to a signal provided from the row decoder 10. The sub word line driver 20 is composed of four NMOS transistors 22-28. The source terminal (active region) of the NMOS transistor 22 and the gate terminal of the NMOS transistor 26 are connected by a first node N1. The first node N1 is precharged by the NMOS transistor 22.

The prior art layout of the sub wordline driver 20 having the configuration as described above is shown in FIG. Referring to FIG. 2, the first node 120C is connected to an active region of the NMOS transistor through a first contact hole 110A and a gate of the NMOS transistor 26 through a second contact hole 110B. Connected with The first node 120C is formed of the same layer as the bit lines 120A and 120B of the memory cell array 30. Metal lines 130 are formed on the bit lines 120A and 120B and the first node 120C to supply power voltages and transmit external signals.

Recently, efforts have been made to miniaturize semiconductor chips. In order to reduce the width A of the semiconductor integrated circuit illustrated in FIG. 2, the widths B and F of the bit lines 120A and 120B and the width D of the first node N1 should be reduced to the minimum. In addition, the space C between the bit line 120A and the first node 120C and the space E between the first node 120C and the bit line 120B should also be minimized.

However, there are limitations in reducing the widths of the bit lines 120A and 120B and the first node 120C, as well as the spaces C and E between the bit lines 120A and 120B and the first node 120C. ) Should also maintain some width.

Therefore, a new sub wordline driver layout is needed to reduce the semiconductor chip size.

Accordingly, an object of the present invention is to solve the above-mentioned problems, and to provide a new sub word line driver layout for reducing a semiconductor chip size.

1 is a circuit diagram showing a configuration of a conventional DRAM having a sub wordline driver;

2 shows a layout of a sub wordline driver according to the prior art; And

3 is a diagram illustrating a layout of a sub wordline driver according to an exemplary embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

10: row decoder 20: sub wordline driver

30: memory cell array

210A, 210B: Contact hole 220A, 220B: Bit line

230B, N1: first node 230B: metal line

According to an aspect of the present invention for achieving the object of the present invention as described above, in response to a signal provided from a row decoder, the memory cell array includes a plurality of bit lines and word lines arranged in a grid form. A sub wordline driver for driving word lines includes a first transistor having a current path formed between the first signal provided from the row decoder and a first node and a gate connected to a power supply voltage, and a second provided from the row decoder. And a second transistor having a current path formed between a signal and the word line and a gate connected to the first node. The first node connecting the active region of the first transistor and the gate of the second transistor is formed on a layer different from the bit line.

In a preferred embodiment, the first node is formed of a metal layer.

(Action)

By such a layout, a sub word line driver capable of minimizing a circuit area of the sub word line driver can be implemented.

(Example)

Hereinafter, an embodiment according to the present invention will be described in detail with reference to FIG. 3.

3 is a diagram illustrating a layout of a sub wordline driver according to an exemplary embodiment of the present invention.

Referring to FIG. 3, the contact hole 210A connects the source (active region) of the NMOS transistor 22 and the first node 230B shown in FIG. 1. The contact hole 210B connects the gate of the NMOS transistor 26 shown in FIG. 1 to the first node 230B.

The first node 230B is formed on a layer different from the bit lines 220A and 220B of the memory cell array 30. In this embodiment, the first node 230B is formed on the same layer as the metal line 230A formed on the bit lines 220A and 220B. The metal line 230A for power supply voltage and external signal transmission is conventionally formed on the contact holes 210A and 220B, but is formed on the left side of the contact holes 210A and 220B in the present invention. However, the metal line 230A and the first node 230B are formed apart from each other at a predetermined interval.

In the related art, there is a limit in reducing the size of a semiconductor chip by forming the bit lines 120A and 120B and the first node 120C in the same layer. Since the lines 220A and 220B and the first node 230B are formed in different layers, there is no need to maintain a space between the bit lines 220A and 220B and the first node 230C. Therefore, according to the present invention, the circuit area of the sub word line driver can be minimized.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to encompass all such modifications and similar constructions.

According to the present invention as described above, since the bit lines and the first node are formed in different layers, there is no need to maintain a space between the bit lines and the first node. Therefore, according to the present invention, the circuit area of the sub word line driver can be minimized.

Claims (2)

In response to a signal provided from a row decoder, in the layout of a sub wordline driver for driving said wordlines of a memory cell array comprising a plurality of bitlines and wordlines arranged in a grid: The sub wordline driver, A first transistor having a gate connected to a power supply voltage and a current path formed between the first signal and the first node provided from the row decoder; A second transistor having a current path formed between the second signal provided from the row decoder and the word line and a gate connected to the first node, And the first node connecting the active region of the first transistor to the gate of the second transistor is formed on a layer different from the bit line. The method of claim 1, And the first node is formed of a metal layer.