KR100229861B1 - Improved semiconductor memory device including memory cells connected to a ground line - Google Patents

Abstract

Memory cell arrays of static random access memory (SRAM) include improved circuitry. The memory cells M51-M58 in one row are connected to the ground line GL1. The memory cells M61-M68 in the other row are connected to the ground line GL2. Each word line WL2, WL3 is alternately connected to two rows of memory cells per column.

When one word line WL2 is activated during a read operation, current flows from the memory cell to the ground line. The sum of the currents flowing through one ground line is reduced, so that the potential of the ground line is prevented from rising, thereby preventing data destruction.

Description

Improved Semiconductor Memory Device Including Memory Cells Connected to a Ground Line

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a memory cell connected to a ground line.

The present invention is particularly applicable to static random access memory (SRAM).

Recently, in accordance with the requirements of high integration and low power consumption of semiconductor memory devices, static random access memories (hereinafter referred to as "SRAM") using thin film transistors (hereinafter referred to as "TFT") have been developed and marketed. .

SRAM using TFTs is published in a paper entitled "A POLYSILICON TRANSISTOR TECHNOLOGY FOR LARGE CAPACITY SRAMs" (1990, International Electron Devices Meeting (IEDM), pp469-472).

Although the present invention is generally applicable to a semiconductor memory having a memory cell connected to a ground line, the following description will be given of an example in which the present invention is applied to an SRAM.

13 is a block diagram of a prior art SRAM.

Referring to FIG. 13, the SRAM 100 includes a memory cell array 1, an X decoder 2, a Y decoder 3, a sense amplifier 5, an output buffer 6, an input buffer 7, and a write circuit. It includes (8).

The memory cell array 1 includes a plurality of memory cells MC arranged in rows and columns.

Each memory cell group 1r, 2r,... Arranged in the horizontal direction in FIG. 13. , Are rows, and each memory cell group 1c, 2c,... Arranged in the vertical direction. , Is a heat.

The X decoder 2 selects a column in the memory cell array 1, and the Y decoder 3 selects a row in the memory cell array 1.

The sense amplifier 5 amplifies the data signal read out from the memory cell MC.

The output buffer 6 outputs the amplified data signal as output data DO, and the input buffer 7 receives input data DI provided from the outside.

The recording circuit 8 amplifies the input data signal and writes the synthesized signal in the desired memory cell MC.

In Fig. 13, line 100 also represents one semiconductor substrate.

In the read operation, the X decoder 2 activates one word line WL in response to an X address signal XA supplied from the outside.

The data signal written in the memory cell MC connected to the activated word line WL appears on the bit lines BLa and BLb.

The Y decoder 3 selects one bit line pair in response to the Y address signal YA provided from the outside.

More specifically, one of the switch circuits in the Y gate circuit 4 conducts in response to an output signal supplied from the Y decoder 3, so that a data signal of one bit line pair is provided to the sense amplifier 5. do.

The provided data signal is amplified by the sense amplifier 5 and then output to the output data DO through the output buffer 6.

In the write operation, input data DI is provided to the write circuit 8 via the input buffer 7. The provided data signal is amplified by the write circuit 8 and then provided to the gate circuit 4.

By the Y decoder 3 conducting one of the switch circuits in the gate circuit 4 in response to the Y address signal YA, an amplified data signal is provided to the corresponding bit line pair.

The X decoder activates one word line WL in response to the X address signal XA, so that the input data DI is written to the designated memory cell.

14 is a circuit diagram using a TFT.

Referring to FIG. 14, the memory cell MC includes the PMOS transistors 105 and 106 constituting the data storage circuit and the NMOS transistors 103 and 104 serving as the access gate transistors with the NMOS transistors 101 and 102. .

The transistors 105 and 106 are formed by the above-described TFT.

The source of the driver transistor 101 is connected to the ground line GL through a direct contact resistor R1 to be described later.

Similarly, the source of the driver transistor 102 is also connected to the ground line GL via a direct contact resistor R2. Gates of the transistors 103 and 104 are connected to a word line WL.

In the write operation, for example, the bit line BLa is at a high level and the bit line BLb is at a low level so that the word line WL is activated.

The transistors 103 and 104 are turned on, so that the nodes N1 and N2 of the data recording circuit are converted to high and low levels, respectively.

In this data writing state, the transistors 102 and 105 are turned on, and the transistors 101 and 106 are turned off.

In the read operation, when the word line WL is activated, the current I flows from the power supply potential Vcc to the ground potential as shown in FIG.

More specifically, the current I flows through the bit line load transistor 111, the access gate transistor 104, and the driver transistor 102 to the ground line GL.

In this current path I, since the direct contact resistance R2 and the wiring resistance r exist, the potential of the ground node N4 of the memory cell MC is raised.

That is, while the word line WL is active, the current I flows through the memory cell MC toward the ground line GL, and as a result, the potential of the ground node N4 rises.

This current I is called a "column current."

Since the column current I is about 10 ³ to 10 ⁶ times larger than the current flowing through the TFTs 105 and 106, the potential rise of the ground nodes N3 and N4 is particularly problematic in the SRAM. .

FIG. 15 is a schematic block diagram of a memory cell array having memory cells shown in FIG. 14.

Referring to FIG. 15, a memory cell array includes memory cells M41 ′ through M78 ′ arranged in rows and columns.

The word lines WL1 to WL4 are connected to the first to fourth rows of memory cells, respectively.

The memory cells M41 'to M48' in the first row and the memory cells M51 'to M58' in the second row are connected to the ground line GL1 through respective direct contact resistors R. As shown in FIG.

Similarly, the memory cells M61 'to M68' of the third row and the memory cells M71 'to M78' of the fourth row are also connected to the ground line GL2.

Each of the ground lines GL1 and GL2 includes a wiring resistance r.

The ground lines GL1 and GL2 are connected to common ground lines GNDLa and GNDLb.

In Fig. 15, the word lines WL1 to WL4 and the ground lines GL1 and GL2 extending in the horizontal direction are formed by a polysilicon layer or a polyside layer on the semiconductor substrate.

In FIG. 15, the ground lines GNDLa and GNDLb lined in the vertical direction are formed by aluminum wiring.

In general, aluminum has a lower resistance compared to polysilicon and polysides.

Thus, in Fig. 15, the vertical ground lines GNDLa and GNDLb are formed by aluminum to reduce the resistance of the ground lines.

Although not shown in Fig. 15, the bit lines are formed by the aluminum wiring in the vertical direction.

FIG. 16 is a layout view in which memory cells M62 'and M63' shown in FIG. 15 are formed on a semiconductor substrate.

In this layout, the transistors 101, 102, 103 and 104 shown in Fig. 14 are shown among the transistors constituting the memory cell M62 '.

The PMOS transistors 105 and 106 formed by the TFT do not appear in the layout diagram shown in FIG.

Referring to FIG. 16, the memory cell M62 ′ may include the first polysilicon layers 214 and 215 constituting the transistors 101 and 102, and the first polysilicon constituting the transistors 103 and 104, respectively. Layer 212 '.

The area AR enclosed by the dotted line represents the active area formed in the semiconductor substrate.

The source of the transistor 101 is connected to the ground line GL2 formed by the second polysilicon layer 230 through a direct contact DC2.

Similarly, the source of transistor 102 is connected to second polysilicon layer 230 via direct contact DC1.

The other memory cells M52 ', M53', and M63 'also have a layout similar to that of the memory cells M62'.

17 is a cross-sectional view of the structure including the direct contact DC2 shown in FIG. 16.

Referring to FIG. 17, a P-type well 251 is formed on an N-type semiconductor substrate 250.

Insulating layers 241 and 242 are formed on the P-type well 251, and first polysilicon layers 215 and 216 are formed on the insulating layers 241 and 242, respectively.

The first polysilicon layers 215 and 216 are insulated by the insulator 240.

The second polysilicon layer (ie, ground line GL2) 230 insulated by the insulator 240 is directly connected to the active region AR1 formed in the P-type well 251.

In the contact portion of the second polysilicon layer 230 and the active region AR1, there is a resistance called "contact resistance".

The direct contact resistors R1 and R2 shown in FIG. 14 and the direct contact resistors R shown in FIG. 15 are caused because the ground wire is formed of polysilicon as described above.

FIG. 18 is a circuit diagram illustrating a current flowing through the ground line GNDLa in the memory cell array shown in FIG. 15.

Referring to FIG. 18, when the word line WL1 is activated, column currents I1 to I5 flow from the memory cells M41 'to M45' to the ground line GL1, respectively.

Each current I1 to I5 flows to ground lines GNDLa and GNDLb (= 0 volts) through corresponding direct contact resistors R and wiring resistors r.

As can be seen in FIG. 18, the closer to the end of the ground line GL1, that is, the closer to the ground line GNDLa, the more the current flowing through the ground line GL1 increases.

Since the ground line GL1 includes the wiring resistance r, the potential changes at each position on the ground line GL1 due to the presence of the currents I1 to I5.

Therefore, as shown by the curve C2 of FIG. 19, the potential VGL1 changes depending on the position on the ground line GL1.

In particular, as the current flowing through the ground line GL1 increases, the potential increases at each position on the ground line GL1.

The potential rise of the ground line GL1 destroys data stored in the memory cell.

In particular, as can be seen from the curve C2 of FIG. 19, since the potential rise is maximum at the center point of the ground line GL1, the memory cell M44 ′ located at the center point of the memory cells M41 ′ to M48 ′ is maximized. M45 ') is particularly susceptible to data destruction.

In addition, there is another problem as follows.

Referring again to FIG. 18, for example, the column current provided from the memory cell M42 ′ may optionally flow into the current I 2 flowing from the right side of the drawing, or from the left side of the current ( I2 ').

In the case where the column current I2 flows from the memory cell M42 ', the potential VN14 of the common connection node N14 of the memory cells M41' and M42 'is expressed by Equation 1 below. It is expressed as

On the other hand, when the column current I2 'flows from the memory cell M42', the potential VN14 'of the node N14 is expressed by the following expression (2).

For example, assuming that each column current I1 to I4 is 200 mA, the direct contact resistance R is 500 Ω, and the wiring resistance r is 20 Ω, in each case, the potential VN14 and (VN14 ') is represented by the following formulas (3) and (4).

As can be seen from the above equations 1 to 4, when the word line WL1 is activated, the potential of the ground node N14 changes according to the data storage state in the memory cell M42 ', and thus the above-mentioned. As can also destroy data.

Changes in the potentials VN14 and VN14 'are indicated by curves C3 and C4 in FIG.

In FIG. 20, the vertical axis indicates potentials, and the horizontal axis indicates positions of nodes N13 and N14.

It is an object of the present invention to provide a semiconductor memory device having a memory cell connected to a ground line, which can prevent destruction of data stored in the memory cell.

Another object of the present invention is to provide a static random access memory device capable of preventing destruction of data stored in a memory cell.

A semiconductor memory device of the present invention includes a semiconductor substrate and a memory cell array having a plurality of memory cells arranged in rows and columns on the substrate.

Each memory cell having a field effect transistor on the substrate is partitioned by first and second ground lines in the column direction.

The semiconductor memory device also has a third ground line formed in the row direction on the substrate and connected to the memory cell and a word line formed in the row direction on the substrate and connected to the memory cell.

A plurality of consecutive memory cell pairs connected to word lines are alternately located in adjacent rows.

In operation, when one word line is activated, current flows from the memory cell connected to the word line through the third ground line.

Since a plurality of consecutive pairs of memory cells connected to one word line are alternately located in a neighboring row, the number of memory cells that allow current to flow through the third ground line when one word line is activated is conventional. Smaller than in the circuit.

Since the flow of current through the third ground line is reduced as compared with the case in the conventional circuit, the potential rise at the third ground line is suppressed.

As a result, data destruction caused by the potential rise of the ground line can be prevented.

Moreover, current from neighboring memory cells in the row direction does not flow through the ground node of the memory cells alternately located in the neighboring rows.

Therefore, the potential rise of the ground line due to the current can be prevented.

In yet another aspect of the present invention, a semiconductor memory device includes a semiconductor substrate and a melisel array having a plurality of memory cells arranged in rows and columns on the substrate.

Each memory cell is partitioned by first and second ground lines in the column direction.

The semiconductor memory device also has a third ground line formed in the row direction on the substrate and connected to the memory cell and a word line formed in the row direction on the substrate and connected to the memory cell.

For consecutive memory cells connected to the word line, those in the odd-numbered column and those in the even-numbered column are alternately positioned in adjacent rows.

In operation, when one word line is activated, current flows from the memory cell connected to the word line through the third ground line.

For successive memory cells connected to one word line, word lines in the odd-numbered column and word lines in the even-numbered column are alternately positioned in adjacent rows.

Therefore, the number of memory cells that allow current to flow through the third ground line when one word line is activated becomes smaller than in the conventional circuit.

Since the flow of current through the third ground line is reduced as compared with the case in the conventional circuit, the potential rise at the third ground line is suppressed.

As a result, data destruction caused by the potential rise of the ground line is prevented.

Moreover, current from neighboring memory cells in the row direction does not flow through the ground node of the memory cells alternately located in the neighboring rows.

Thus, the potential rise of the ground line due to the current can be prevented.

In still another aspect of the present invention, a semiconductor memory device includes a semiconductor substrate and a memory cell array having a plurality of memory cells arranged in rows and columns on the substrate.

Each memory cell is partitioned by first and second ground lines in the column direction.

The semiconductor memory device also has a third ground line formed in the row direction on the substrate and connected to the memory cell and a word line formed in the row direction on the substrate and connected to the memory cell.

A plurality of consecutive memory cell pairs connected to the third ground line are alternately positioned in adjacent rows.

In operation, when one word line is activated, current flows from the memory cell connected to the word line through the third ground line.

Since a plurality of consecutive pairs of memory cells connected to the third ground line are alternately positioned in adjacent rows, the number of memory cells that allow current to flow through the third ground line when one word line is activated is a conventional circuit. Becomes smaller than

Since the flow of current through the third ground line is reduced as compared with the case in the conventional circuit, the potential rise at the third ground line is suppressed.

As a result, the data destruction phenomenon caused by the potential rise of the ground line is prevented.

In still another aspect of the present invention, a semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of ground lines respectively connected to memory cells in corresponding rows in the memory cell array; And a plurality of inclined word lines respectively connected to memory cells corresponding to the diagonal direction in the memory cell array.

In operation, when one inclined word line is activated, current flows from the memory cell to each of the plurality of ground lines.

Therefore, the potential rise of the ground line is suppressed.

Another semiconductor memory device of the present invention comprises a semiconductor cell and a memory cell array having a plurality of memory cells arranged in rows and columns on the substrate.

Each memory cell is partitioned by first and second ground lines in the column direction.

The semiconductor memory device further includes a third ground line formed in the row direction on the substrate and connected to the memory cell, and a word line formed in the row direction between the first and second ground lines on the substrate and connected to the memory cell.

For a continuous memory cell connected to a word line, two consecutive memory cells at the end of the first ground line side in the word line and two consecutive memory cells at the end of the second ground line side of the word line and the first of the word line Two consecutive memory cells at the ends of the ground line side are alternately positioned in adjacent rows.

In operation, when one word line is activated, current flows from the memory cell connected to the word line through the third ground line.

For continuous memory cells connected to one word line, two consecutive memory cells at the ends of the first and second ground lines in the word line are alternately positioned in adjacent rows.

The memory cells at both ends of the word line have a larger potential difference than memory cells having different potential differences at ground nodes across the memory cells.

Therefore, the current flowing from the neighboring memory cell to the memory cell across the word line and the ground node between the memory cell adjacent to the word line in the row direction is reduced as compared with the conventional circuit.

As a result, the potential rise of the ground wire is effectively prevented.

In another aspect of the invention, a semiconductor memory device includes a semiconductor cell and a memory cell array having a plurality of memory cells arranged in rows and columns on the substrate.

Each memory cell is partitioned by first and second ground lines in the column direction.

In addition, the semiconductor device includes first and second word lines formed in a row direction on a substrate and connected to a memory cell, and third ground lines formed in a row direction between the first and second ground lines on a substrate and connected to a memory cell. It includes.

For a continuous memory cell connected to the third ground line, two consecutive memory cells at the end of the first ground line side in the third ground line are alternately positioned in adjacent rows and end of the second ground line side in the third ground line. Two consecutive memory cells in are alternately placed in adjacent rows.

In operation, for two consecutive memory cells connected to a third ground line, each two consecutive memory cells at the ends of the first and second ground lines side of the third ground line are alternately positioned in adjacent rows.

The potential difference between the ground nodes across the memory cells is larger than the other memory cells in the memory cells across the word lines.

Accordingly, the current flowing from the neighboring memory cell to the ground node between the memory cell at both ends of the word line and the memory cell adjacent at both ends of the word line in the row direction is reduced as compared with the conventional circuit.

As a result, the potential rise of the ground wire is effectively prevented.

Advantages, features, aspects, and objects of the present invention will become more apparent from the following detailed description of the invention in conjunction with the accompanying drawings.

1 is a schematic block diagram of a memory cell array in accordance with an embodiment of the present invention;

2 is a schematic diagram illustrating a current flowing through a ground line of the memory cell array shown in FIG. 1;

3 is a graph showing a potential change of the ground node N4 shown in FIG. 2;

4 is a layout view on a semiconductor substrate of the memory cell shown in FIG. 1;

5 is a schematic block diagram of a memory cell array in another embodiment of the present invention;

6 is a schematic block diagram of a memory cell array in another embodiment of the present invention;

7 is a schematic diagram of one memory cell shown in FIG. 6;

8 is a layout view on a semiconductor substrate of the memory cell shown in FIG. 6;

9 is a schematic block diagram of a memory cell array in yet another embodiment of the present invention;

10 is a layout view on a semiconductor substrate of the inclined word line shown in FIG. 9;

11 is a schematic block diagram of a memory cell array in yet another embodiment of the present invention;

12 is a layout view on a semiconductor substrate of the memory cell shown in FIG. 11;

13 is a block diagram of a conventional SRAM;

14 is a schematic diagram of a memory cell using a TFT;

FIG. 15 is a schematic block diagram of a memory cell array having memory cells shown in FIG. 14;

16 is a layout diagram on a semiconductor substrate of the memory cell shown in FIG. 15;

17 is a sectional view of a structure including the direct contact DC2 shown in FIG. 16;

18 is a schematic diagram illustrating current flowing through a ground line in the memory cell array shown in FIG. 15;

19 is a graph showing a change in potential on the ground line shown in FIG. 18;

20 is a graph showing a potential change of the ground node N14 shown in FIG. 18;

<Explanation of symbols for main parts of drawing>

M41 to M78: Memory cells GL1, GL2: Ground wire

GNDLa, GNDLb: Common ground line WL0 to WL5: Word line

R: direct contact resistance r: wiring resistance

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

Referring to FIG. 1, one memory cell array includes memory cells M41 to M78 arranged in rows and columns.

The memory cells M41 to M48 of one row and the memory cells M51 to M58 of another row are directly connected to the ground line GL1 through the contact resistor R. FIG.

Similarly, memory cells M61 to M68 and M71 to M78 are also connected to the ground line GL2.

Ground lines GL1 and GL2 are formed by a polysilicon layer or a polyside layer on a semiconductor substrate.

These ground lines are connected to common ground lines GNDLa and GNDLb formed by aluminum.

Compared with the memory cell array shown in FIG. 15, the word lines WL0 to WL5 are connected to the memory cells in a shape different from that in FIG.

As can be seen in FIG. 1, the word lines WL0 to WL5 form two thermal pairs, and the paired word lines are twisted.

For example, the word line WL2 is connected to the memory cells M51, M62, M53, ....

In a manner complementary to this, the word line WL3 is connected to the memory cells M61, M52, M63, ....

In other words, the word lines WL2 are alternately connected to the memory cells M51 to M58 and M61 to M68 in the second and third rows.

The word line WL3 is alternately connected to the memory cells M51 to M68 in a shape complementary to the word line L2.

More specifically, a row adjacent to a plurality of pairs M51 and M62, M53 and M64, ..., M57 and M68 in consecutive memory cells M51, M62, M53, ..., M68 connected to the word line WL2. Alternately located

Similarly, a plurality of pairs M61 and M52, M63 and M54, ..., M67 and M58 in consecutive memory cells M61, M52, M63, ..., M58 connected to the word line WL3 are adjacent to each other. Alternately located.

The word lines WL0 to WL5 are also formed of polysilicon layers or polyside layers.

In Fig. 1, the word lines paired with the word lines WL0 to WL5 have end portions that are not twisted on the ground line GNDLa, and end portions that are twisted on the ground line GNDLb.

The invention is not limited by the example as in FIG. 1.

The ends of the word lines paired on the ground lines GNDLa and GNDLb may or may not be twisted.

FIG. 2 is a circuit diagram for describing a current flowing through ground lines GL1 and GL2 in the memory cell array shown in FIG. 1.

In FIG. 2, memory cells M51 to M55 and M61 to M65 in the second and third rows in the memory cell array shown in FIG. 1 are shown.

For example, when the word line WL2 is activated, the memory cells M51, M62, M53, M64, M55, ... are accessed.

Therefore, column currents I1 to I5 flow from the memory cells to be accessed to the ground lines GL1 and GL2.

Among these currents I1 to I5, currents I1 and I3 flow through the ground line GL1 to the ground line GNDLa.

The currents I2 and I4 flow through the ground line GL2 to the ground line GNDLa.

The current I5 flows through the ground line GL1 to the ground line GNDLb (not shown).

As can be seen in FIG. 2, when one word line WL2 is activated, current flows through two ground lines GL1 and GL2 from the selected memory cell.

Therefore, the sum of the currents flowing through each of the ground lines GL1 and GL2 is smaller than the sum of the currents flowing through one ground line GL1 shown in FIG.

Therefore, the rise of the potentials of the ground lines GL1 and GL2 is half of the rise of the potential of the ground line GL1 shown in FIG.

Referring again to FIG. 19, curve C1 represents a change in potential on the ground line GL1 shown in FIG. 2.

As can be seen from the curve C2 showing the change in the potential on the ground line GL1, FIG. 18 shows that the potential rise on the ground line GL1 of FIG. 2 is half the potential rise of the ground line of FIG.

In the memory cell array shown in Fig. 1, when the word line WL2 is activated for a read operation, the potential of the ground line GL1 rises smaller than in the memory cell array shown in Fig. 15, and therefore the data caused by the potential rise of the ground line. Destruction is prevented.

In addition, the potential of the ground node N4 of the memory cell M62 is equal to the current (ie, current) when the current (ie, current I2) flows from the right side of the memory cell M62 and from the left side of the memory cell M62. As I2 ') flows, it changes as follows.

When the current I2 shown in FIG. 2 flows out of the memory cell M62, the potential VN4 of the ground node N4 is expressed as follows.

When the current I2 'shown in FIG. 2 flows from the memory cell M62, the potential VN4' of the ground node N4 is expressed as follows.

In the same manner as in the example shown in Fig. 18, assume that each column current I1 to I4 is 200 mA, the direct contact resistance R is 500 Ω, and the wiring resistance r is 20 Ω. , VN4 = 0.124 volts, VN4 '= 0.02 volts.

As can be seen by comparing the values shown in Equations 3 and 4 with these values, the potential rise of the ground node N4 of the memory cell M62 can be reduced.

The change in potential at ground node N4 is shown in FIG. 3.

As described above, when word lines are alternately tangential to memory cells in neighboring rows, a circuit consisting of word lines in which columns and columns are alternately connected flows from neighboring memory cells to ground nodes therebetween. The potential rise of the ground node caused by the current can be prevented very effectively.

FIG. 4 is a layout view in which memory cells M63 and M64 shown in FIG. 1 are formed on a semiconductor substrate.

In order to connect the word lines WL2 and WL3 to the memory cells alternately in rows and columns, the word lines WL2 and WL3 are formed on the semiconductor substrate as shown in FIG.

Referring to FIG. 4, the word line WL2 may include a first polyside layer 211, a second polysilicon layer (or a second polyside layer) 222, and a first polyside layer 213 formed on a semiconductor substrate. ).

The first polyside layer 211 is connected to the second polysilicon layer 222 through the contact hole CH1.

The second polysilicon layer 222 is connected to the first polyside layer 213 through the contact hole CH2.

The word line WL3 includes a second polysilicon layer 221, a first polyside layer 212, and a second polysilicon layer 223 formed on the semiconductor substrate.

The second polysilicon layer 221 is connected to the first polyside layer 212 through the contact hole CH3.

The first polyside layer 212 is connected to the second polyside layer 223 through the contact hole CH4.

In the layout diagram shown in Fig. 4, four transistors 101, 102, 103 and 104 constituting one memory cell (e.g., M63) are shown.

The PMOS transistors 105 and 106 formed by the TFTs are not shown in FIG.

The driver transistor 101 is formed by the first polyside layer 215.

Driver transistor 102 is formed by first polyside layer 214.

The access gate transistors 103 and 104 are formed by the first polyside layer 212.

The region AR represents an activation region formed in the semiconductor substrate.

The ground line GL2 is formed by the second polysilicon layer (or second polyside layer) 230.

The second polysilicon layer 230 is connected to the active region through direct contacts DC1, DC2 and DC3.

Each direct contact DC1 to DC3 has the above-described direct contact resistance R. FIG.

5 is a schematic block diagram showing yet another embodiment of the present invention.

In the memory cell array shown in Fig. 1, each word line in which columns and columns are alternately connected to two rows of memory cells is provided.

On the other hand, in the memory cell array shown in Fig. 5, word lines WL10 to WL15 in which two columns are alternately connected to memory cells in two rows are provided.

More specifically, a plurality of consecutive memory cells connected to the word lines WL10 to WL15 are alternately positioned in adjacent rows.

For clarity, two columns are alternately connected to the memory cells except the memory cells at both ends of each row of the word lines WL10 to WL15.

The word lines WL10 to WL15 are alternately connected to each memory cell at one end of each row and each memory cell adjacent to each row, and each memory cell at the other end of each row and each memory cell adjacent to each row are alternately connected. Are alternately connected to.

In the embodiment shown in FIG. 5, when one word line is activated, the total current flowing from the memory cell to the ground line is reduced by half compared to the circuit shown in FIG. 15, so that the potential rise at the ground line can be prevented. have.

Therefore, even in this embodiment, destruction of data stored in the memory cell is prevented.

In this embodiment, two columns of word lines are alternately connected to memory cells in adjacent rows of memory cells.

Therefore, the potential rise suppression effect of the ground node caused by the current flowing from the neighboring memory cell to the ground node between the memory cells is slightly less than that of the circuit shown in FIG.

However, the effect of suppressing the potential rise at the ground node is greater than when word lines are alternately connected to two or more columns of memory cells.

Moreover, in this embodiment, the following special effects can be obtained.

As described above, the potential increase suppression effect at the ground node can be obtained from the ground line between the memory cells of the portions in which word lines are alternately connected in each row.

Referring to FIG. 19, memory cells (eg, M41 and M48) at each end of the ground lines GL1 and GL2 have the largest potential difference between both ground nodes of the memory cell.

Thus, by reducing the potential difference between the ground nodes of the memory cells at each end of the ground lines GL1 and GL2, the potential of the ground lines GL1 and GL2 is reduced, compared with reducing the potential difference between the ground nodes of the other memory cells. The rise can be effectively suppressed.

Note the memory cells at each end of the ground lines GL1 and GL2. The word lines WL10 to WL15 are memory cells at each end of the ground lines GL1 and GL2 and memory cells adjacent to the ground lines GL1 and GL2. Are alternately connected to.

Therefore, in the circuit of FIG. 5, the word lines WL10 to WL15 are compared with the case where the memory cells at each end of the ground lines GL1 and GL2 are alternately connected to the memory cells adjacent to the ground lines GL1 and GL2. Thus, the potential rise of each of the ground lines GL1 and GL2 can be effectively suppressed.

Figure 6 is a circuit block diagram of a memory cell array, showing yet another embodiment of the present invention.

Referring to FIG. 6, two ground lines GL1a and GL1b are provided in place of one ground line GL1 in the circuit shown in FIG. 15.

Each of the ground lines GL1a and GL1b is alternately connected to the memory cells M61 to M68 and M71 to M78, respectively.

Each memory cell is connected to one corresponding ground line GL1a and GL1b through one contact resistor R. FIG.

The ground lines GL1a and GL1b have a wiring resistance r.

In the embodiment shown in Fig. 6, one word line WL1 or WL2 is connected to each memory cell.

However, as shown in Figs. 7 and 8, in fact, two word lines WL1a and WL1b or WL2a and WL2b are connected to each memory cell.

In order to selectively activate the two word lines, it is necessary to add one bit of the row address signal. However, as described later with reference to the layout of FIG. 8, symmetry is obtained in the layout on the semiconductor substrate of each memory cell.

For example, when one word line WL1b is activated, current flows from the memory cells M61 to M68 to the ground lines GL1a and GL1b through the contact resistor R directly.

Also in this embodiment, since the total of the column currents flowing through the ground lines GL1a and GL1b is reduced by half as compared with the circuit shown in FIG. 15, the respective ground lines GL1a and GL1b The potential rise is reduced by half.

Thus, data destruction stored in the memory cell is prevented.

FIG. 7 is a circuit diagram of the memory cell M61 shown in FIG. 6.

Referring to FIG. 7, the gates of the transistors 103 and 104 are connected to the word lines WL1a and WL1b, respectively.

The sources of the driver transistors 101 and 102 are directly connected to the ground line GL1a through the contact resistor R.

FIG. 8 is a layout diagram showing memory cells M62, M63, M72, and M73 shown in FIG. 6 on a semiconductor substrate.

Referring to FIG. 8, for example, the memory cell M62 includes a driver transistor 101 formed by the first polyside layer 218 and a driver transistor 102 formed by the first polyside layer 219.

The second polysilicon layer (or second polyside layer) 261 constituting the ground line GL1b is connected to the active region, that is, the sources of the transistors 101 and 102 through a direct contact DC4.

The second polysilicon layer 261 is connected to the third polysilicon layer (or third polyside layer) 232 through the contact hole CH5.

The third polysilicon layer 232 is connected to the second polysilicon layer (or second polyside layer) 225 through the contact hole CH6.

The third polysilicon layer 225 is connected to the source of two driver transistors in the memory cell M73 through the direct contact DC5.

The ground line GL1a is also formed on the semiconductor substrate similarly to the ground line GL1b.

Each memory cell shown in Fig. 8 has symmetry in the layout on the semiconductor substrate.

Referring to FIG. 8, the memory cell M62 will be described as an example.

Driver transistors 101 and 102 of the same size are provided symmetrically with respect to contact DC4 directly on the semiconductor substrate.

Word lines WL1a and WL1b of the same size are also provided symmetrically with respect to the contact DC4 directly on the semiconductor substrate.

In this embodiment, the ground lines GL1a and GL1b are alternately connected to the memory cells M61 to M68 and M71 to M78 in two rows.

This is because of the following reasons.

Referring to FIG. 8, for example, the number of word lines in the memory cells M62 and M63 is two (word lines WL1a and WL1b).

On the other hand, the number of ground lines in the memory cells M62 and M63 is one.

Therefore, the alternating connection of the ground lines can be made easier than the alternating connection of the word lines of the memory cells M62 and M63, for example.

Comparing the circuit shown in FIG. 6 with the circuit shown in FIG. 1, the following is found.

In the circuit shown in Fig. 1, word lines are alternately connected to two rows of memory cells.

Even memory cells in the same row are connected to two word lines separately.

Therefore, the actual arrangement of the memory cells shown in Figs. 1 and 4 does not match the arrangement of the memory cells in the memory space.

In contrast, in the circuit shown in Fig. 6, the same row of one word line is connected to all the memory cells.

Therefore, the actual arrangement of the memory cells shown in Figs. 6 and 8 corresponds to the arrangement of the memory cells in the memory space.

In this embodiment, since the ground lines alternately connected to the two rows of memory cells shown in Fig. 6 are not necessary, it is not necessary to provide two layers of ground lines.

Therefore, in this embodiment, the ground wire formed in a further layer is possible, so that the fabrication of the circuit is easy.

9 is a schematic block diagram of a memory cell array illustrating another embodiment of the present invention.

Referring to FIG. 9, the memory cell array includes memory cells M81 to M114 arranged in rows and columns.

Each ground line GL1 to GL4 is connected to a memory cell in a corresponding row, respectively.

In all the embodiments described above, the word lines extend in the row direction, but in the embodiment shown in Fig. 9, the word lines extend obliquely on the semiconductor substrate.

Each inclined word line is connected to memory cells arranged in a diagonal direction in the memory cell array.

For example, the inclined word line WL20 is formed by connecting the local word lines WL21 to WL24 to the second polysilicon wires (or second polyside wires) 226 to 228.

Local word lines WL21 to WL24 are connected to corresponding memory cells M81, M92, M103 and M114, respectively.

In the memory cell array shown in Fig. 9, other inclined word lines are also formed in the inclined direction on the semiconductor substrate in the same shape as the inclined word line WL20.

When the inclined word line WL20 is activated, current flows from the memory cells M81, M92, M103, and M114 to the corresponding ground lines GL1, GL2, GL3, and GL4, respectively.

Also in this embodiment, when one word line (inclined word line) is activated, the current flowing in one ground line is reduced, so that the potential rise at the ground line is prevented, thus preventing the destruction of data stored in the memory cell. do.

In this embodiment, one memory cell is connected to one word line in a plurality of memory cells installed in a row direction and connected to one ground line.

Thus, the current flowing through one ground line is reduced compared to that in the circuit shown in the other embodiments, and as a result, the potential rise in one ground line is suppressed compared to that in the circuit shown in the other embodiments.

FIG. 10 is a layout view showing the inclined word line WL20 shown in FIG. 9 on a semiconductor substrate.

Referring to Fig. 10, each of the local word lines WL21, WL22 and WL23 constituting the inclined word line WL20 is formed by a first polyside layer on a semiconductor substrate.

The local word line WL21 is connected to the local word line WL22 via a second polysilicon layer (or second polyside layer) 226.

This local word line WL22 is connected to the local word line WL23 through the second polysilicon layer 227.

11 is a schematic block diagram illustrating a memory cell array in another embodiment of the present invention.

Referring to FIG. 11, the memory cells M41 to M48 arranged in the first row are connected to the ground line GL10 through direct contact (not shown).

Similarly, the memory cells M51 to M58 arranged in the second row are also connected to the ground line GL20.

The word line WL31 is connected to the odd-numbered memory cell of the memory cells M41 to M48, and the word line WL32 is connected to the even-numbered memory cell.

Similarly, the word line WL33 is connected to the odd-numbered memory cell of the memory cells M51 to M58, and the word line WL34 is connected to the even-numbered memory cell.

Also in this embodiment, when one word line is activated, the amount of current flowing in the memory cells connected to one ground line is reduced, so that the potential rise of the ground line is prevented, and thus data destruction is prevented.

In this embodiment, since two word lines are used to access one row of memory cells, one bit of row address signal is added.

FIG. 12 is a layout diagram showing memory cells M41 and M42 shown in FIG. 11 on a semiconductor substrate.

Referring to FIG. 12, for example, the memory cell M41 includes a driver transistor 101 formed by the first polyside layer 271 and a driver transistor 102 formed by the first polyside layer 272.

The second polysilicon layer (or second polyside layer) 263 constitutes the ground line GL10 and is formed through the direct contact DC1 of the active region AR, that is, the transistors 101 and 102. Is connected to the source.

As described above, in the embodiments shown in FIGS. 1, 5, and 6, when one word line is activated, currents from the memory cells flow through two ground lines.

Therefore, since the current flowing in one ground line is reduced by half compared with the circuit shown in Fig. 15, the potential rise in the ground line can be reduced.

As a result, data destruction caused by the potential rise at the ground line is prevented.

Furthermore, in the embodiment shown in Fig. 9, current flows from the memory cell to the plurality of ground lines when one inclined word line is activated.

Therefore, the potential rise of the ground line is prevented, and data destruction is prevented.

Also in the embodiment shown in Fig. 11, the current flowing from the memory cell to the ground line is reduced by half when one word line is activated, and as a result, data destruction is prevented.

Although the above-described present invention has been described only for the example applied to the SRAM, the present invention is generally applicable to various semiconductor memories having memory cells connected to ground lines.

Although the invention has been described and illustrated in detail, it is to be understood that the same as the examples and illustrated methods, the spirit and scope of the invention are limited only by the claims.

Claims (4)

In a semiconductor memory device including two adjacent memory cells, A semiconductor substrate, A first conductive layer formed on the substrate; First and second access transistors each having a gate formed of the first conductive layer; First and second driver transistors each having an active region formed in the substrate; First and second contact holes formed on the gates of the first and second access transistors and the active regions of the first and second driver transistors, and exposing the gates of the first and second access transistors; An insulating layer having a third contact hole exposing an active region of the first and second driver transistors; A second conductive layer formed on the insulating layer; A second word layer formed of the second conductive layer and connected to a gate of the second access transistor through a first contact hole and a first word line connected to a gate of the first access transistor; Word Line, And a ground line formed of the second conductive layer and connected to an active region of the driver transistor through the third contact hole. In a semiconductor memory device comprising a memory cell, A semiconductor substrate, A first conductive layer formed on the substrate; First and second access transistors each having a gate formed of the first conductive layer; First and second driver transistors each having an active region formed in the substrate; First contact holes formed on the gates of the first and second access transistors and the active regions of the first and second driver transistors, and exposing the gates of the first access transistors and the active regions of the first driver transistors. An insulating layer having a second contact hole exposing the light source; A second conductive layer formed on the insulating layer; A word line formed of the second conductive layer and connected to the gate of the first access transistor through the contact hole, and And a ground line formed of the second conductive layer and connected to an active region of the first driver transistor through the second contact hole. In a semiconductor memory device comprising a memory cell, A semiconductor substrate, A first polysilicon layer formed on the substrate and serving as a gate of an access transistor; A driver transistor having an active region formed on the substrate; An insulating layer formed on the first polysilicon layer and the active region of the driver transistor, the insulating layer having a first contact hole exposing the first polysilicon layer and a second contact hole exposing the active region of the driver transistor; A second polysilicon layer formed on the insulating layer and acting as a word line and connected to the first polysilicon layer through the contact hole; And a ground line formed of the second polysilicon layer and connected to an active region of the driver transistor through the second contact hole. In a static random access memory having a memory cell, A semiconductor substrate, A first polysilicon layer formed on the substrate and serving as a gate of an access transistor; A driver transistor having an active region formed on the substrate; An insulating layer formed on the first polysilicon layer and the active region of the driver transistor, the insulating layer having a first contact hole exposing the first polysilicon layer and a second contact hole exposing the active region of the driver transistor; A second polysilicon layer formed on the insulating layer and functioning as a word line and connected to the first polysilicon layer through the contact hole; and And a ground line formed of the second polysilicon layer and connected to an active region of the driver transistor through the second contact hole.

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