KR20020018311A - Semiconductor memory device having cell capacitors and method of fabricating the same - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor memory device having a cell capacitor is provided to maximize a surface area of a storage electrode and to improve a refresh characteristic of a dynamic random access memory(DRAM) device, by stacking upper and lower capacitors respectively connected to two unit cells adjacent to each other on a plane occupied by the unit cells. CONSTITUTION: A pair of cell transistors sharing a common drain region are formed on a semiconductor substrate(50). A lower interlayer dielectric is formed on the entire surface of the resultant structure having the pair of cell transistors. The lower capacitor covering the region of the pair of cell transistors is formed on the lower interlayer dielectric, connected to one of the pair of cell transistors. The upper capacitor connected to the either of the pair of cell transistors is formed on the lower capacitor.

Description

Semiconductor memory device having a cell capacitor and a method of manufacturing the same {SEMICONDUCTOR MEMORY DEVICE HAVING CELL CAPACITORS AND METHOD OF FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor memory device and a semiconductor memory device manufactured thereby, and more particularly, to a method of manufacturing a semiconductor memory device having a cell capacitor and a semiconductor memory device manufactured thereby.

In general, a semiconductor memory device, particularly a dynamic random access memory (DRAM), is a memory device that stores data in a capacitor of a unit cell. However, as the integration density of DRAM increases, the area of the unit cell is also drastically reduced, thereby reducing the capacitor capacitance. The capacitance of this capacitor, that is, the capacitance, means the storage capacity of data. Accordingly, when the capacitance is small, an error of incorrect reading may occur when the data is to be stored and read again. In order to prevent such a data error, a so-called refresh operation is performed to restore the data after a certain time. Since the refresh operation is affected by the capacitance, increasing the capacitance may be one of the main methods for improving the refresh characteristics.

Two important factors to increase the capacitance include a method of replacing the dielectric between the two electrodes constituting the capacitor with a high dielectric constant material and a method of increasing the opposing area of the two electrodes sandwiching the dielectric. In particular, various methods such as a cylinder structure, a fin structure, or a trench structure have been applied to the structure that increases the latter facing area. In the capacitor, the storage electrode serving as the lower electrode and the plate electrode serving as the upper electrode face each other with the dielectric film interposed therebetween. Increasing the opposing area of these two electrodes increases the capacitance in proportion to the increase in the opposing area. However, due to the rapid high integration, the area of the unit cell is reduced and a new structure capable of increasing the opposing area of the capacitor is required.

Hereinafter, a semiconductor memory device according to the related art will be described with reference to FIG. 1.

Referring to FIG. 1, device isolation layers 3 defining an active region on the semiconductor substrate 1, and a pair of source regions 5 and a drain region 7 are formed in the active region. In addition, there are gate patterns 17 including the gate oxide layer 9, the polysilicon layer pattern 11, the metal silicide layer pattern 13, and the capping insulating layer pattern 15. The gate patterns 17 may be covered with a protective layer, such as a silicon nitride layer 19, and a first interlayer insulating layer 21 and a second interlayer insulating layer 23 may be disposed on the silicon nitride layer 19. The source regions 5 of the active region are connected to the storage electrodes 27 through the storage pad polys 25. A dielectric layer 31 is disposed between the storage electrodes 27 and the plate electrode 29. Since one storage electrode 27 is formed on the one source region 5, there is a limit in maximizing the area of the storage electrode 27.

Accordingly, an object of the present invention is to provide a method of manufacturing a semiconductor memory device having a large capacitance by increasing the opposing areas of two electrodes of a cell capacitor within a limited cell area in manufacturing a semiconductor memory device having a cell capacitor. To provide.

Another object of the present invention is to provide a semiconductor memory device capable of maximizing the capacitance of a cell capacitor.

1 is a cross-sectional view illustrating a problem of a semiconductor memory device according to the prior art.

2 to 4 are cross-sectional views illustrating a method of manufacturing a semiconductor memory device according to the present invention and a semiconductor device manufactured thereby.

In order to achieve the above technical problem, the present invention comprises the steps of forming a pair of cell transistors sharing a common drain region on the semiconductor substrate, and forming a lower interlayer insulating film on the entire surface of the resultant formed the pair of cell transistors; Forming a lower capacitor on the lower interlayer insulating layer, the lower capacitor being connected to any one of the pair of cell transistors and covering the pair of cell transistor regions; Forming an upper capacitor connected with the other one of the cell transistors.

Preferably, the lower capacitor forms one contact hole for patterning the lower interlayer insulating layer to expose a source region of any one of the pair of cell transistors, and on the lower interlayer insulating layer. Forming a first storage node connected to the one cell transistor through a contact hole and covering the pair of cell transistor regions, and sequentially stacking a dielectric film and a first plate electrode on the entire surface of the product on which the first storage node is formed; Form.

In addition, the upper capacitor may form an upper interlayer insulating film on the entire surface of the resultant in which the lower capacitor is formed, and continuously pattern the upper interlayer insulating film, the lower capacitor, and the lower interlayer insulating film to form another one of the pair of cell transistors. Forming another contact hole exposing the source region of the cell transistor of the cell transistor, forming an insulating spacer on the sidewall of the other contact hole, and surrounding the other contact surrounded by the insulating spacer on the upper interlayer insulating layer A second storage node connected to the other cell transistor through the hole and overlapping the first storage node is formed, and a dielectric film and a second plate electrode are sequentially stacked on the entire surface of the resultant product on which the second storage node is formed. do.

In order to achieve the above technical problem, the present invention provides a pair of cell transistors formed on a semiconductor substrate and sharing one common drain region, and covering the region in which the pair of cell transistors are formed, and the pair of cell transistors. And a lower capacitor connected to any one of the cell transistors, and an upper capacitor formed on the lower capacitor to overlap the lower capacitor and connected to the other one of the pair of cell transistors.

Preferably, the lower capacitor includes a first storage node electrically connected to a source region of the one cell transistor, a dielectric film and a first plate electrode sequentially formed on the first storage node. The first storage node is electrically connected to the source region of the one cell transistor through a contact hole penetrating a predetermined region of the lower interlayer insulating layer covering the pair of cell transistors.

In addition, the upper capacitor includes a second storage node electrically connected to a source region of the other cell transistor, and a dielectric layer and a second plate electrode sequentially formed on the second storage node and overlapping the lower capacitor. . Here, the second storage node is connected to the other cell transistor through a predetermined region of the upper interlayer insulating layer interposed between the lower capacitor and the second storage node and another contact hole penetrating through the predetermined region of the lower capacitor. It is electrically connected to the source region of. In addition, the insulating spacer further includes sidewalls of the other contact hole.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 4.

Referring to FIG. 2, an isolation layer 52 defining an active region is formed in a predetermined region of the semiconductor substrate 50. The device isolation film 52 may be formed by a LOCOS or a trench device isolation method, and preferably by a trench device isolation method. A gate oxide film 54, a conductive film, and a capping insulating film are sequentially formed on the entire surface of the resultant device on which the device isolation film 52 is formed. The gate oxide film 54 is preferably formed of a thermal oxide film, and the conductive film is preferably formed of a polyside film which is a composite film of a polysilicon film and a metal silicide film. In addition, the capping insulating film is preferably formed of a silicon nitride film. The capping insulation layer and the polyside layer are successively patterned to form a gate pattern 56 including a polysilicon pattern 56a, a metal silicide pattern 56b, and a capping insulation layer pattern 56c.

The impurity is implanted on the active region using the gate pattern 56 and the device isolation layer 52 as an ion implantation mask to form low concentration impurity regions. Accordingly, three low concentration impurity regions 58 and 60 are formed in each active region. Here, the low concentration impurity regions formed at the center of the active region correspond to the common drain region 58, and the low concentration impurity regions formed on both sides of the common drain region correspond to the source regions 60. As a result, a pair of cell transistors sharing the common drain region 58 is formed in each active region.

The silicon nitride layer 62 and the first interlayer dielectric layer 64 are formed on the entire surface of the resultant in which the drain / source regions 58 and 60 are formed. Preferably, the first interlayer insulating film is formed of a BPSG film. The BPSG film 64 is reflowed to completely fill the space between the gate patterns and to smoothly planarize the surface of the BPSG film 64. A photoresist film is coated on the BPSG film 64, and a photoresist pattern is formed to expose only one source region 60 of the pair of source regions 60 through a photographic process. Subsequently, the BPSG film 64 and the silicon nitride film 62 are continuously anisotropically dry-etched to form contact holes exposing only one source region 60, and at the same time, silicon nitride film spacers on the sidewalls of the gate patterns in the contact holes. To form. Subsequently, the conductive material film and the BPSG film are formed by chemical mechanical polishing using a silicon nitride film 62 covering the gate patterns 56 by forming a conductive material film such as polysilicon on the entire surface of the resultant. (64) is polished until the silicon nitride film 62 is exposed. As a result, a polysilicon contact pad 66 connected to the one source region 60 is formed. The process of forming the polysilicon contact pad 66 may be omitted. Subsequently, the BPSG film 64 is reformed and planarized on the entire surface of the resultant to form a second interlayer insulating film 68. The first and second interlayer insulating films 64 and 68 form a lower interlayer insulating film.

Referring to FIG. 3, a photoresist pattern is formed on the second interlayer insulating layer 68 to expose another source region 60 in which the contact pad 66 is not formed. The second interlayer insulating film 68, the first interlayer insulating film 64, and the silicon nitride film 62 are sequentially anisotropically dry-etched using the photoresist pattern as an etching mask to expose the other source region 60. One contact hole is formed. A conductive material film, eg, a polysilicon film doped with impurities, is formed on the entire surface of the resultant material to a predetermined thickness. The polysilicon layer is patterned to form a first storage electrode 70 covering the one source region 60. The lower capacitor is formed by sequentially forming the dielectric film 74 and the first plate electrode 76 on the entire surface of the resultant product. The first storage electrode 70 is formed to extend to an upper region of the polysilicon contact pad 66 as shown in FIG. 3. As a result, the lower capacitor covers two unit cell regions adjacent to each other, that is, a pair of cell transistor regions, and thus has a larger surface area than a conventional storage electrode.

Referring to FIG. 4, a third interlayer dielectric layer 78, that is, an upper interlayer dielectric layer, is formed on the first plate electrode 76. The third interlayer insulating film 78, the first plate electrode 76, the dielectric film 74, the first storage electrode 70, the second interlayer insulating film 68, and the first interlayer insulating film 64 are sequentially patterned. Another contact hole exposing the contact pad 66 is formed. Subsequently, an insulating spacer 78a is formed on the sidewall of the other contact hole. The third interlayer insulating film 78 may be formed of a material film having an etch selectivity with respect to the insulating spacer 78a. The third interlayer insulating film 78 and the insulating spacer 78a electrically insulate the lower capacitor and the upper capacitor formed in a subsequent process. Doped polysilicon is formed on the entire surface of the resultant and patterned to form a second storage electrode 80 electrically connected to the contact pad 66. In this case, the second storage electrode 80 is formed to overlap the first storage electrode 70. An upper capacitor is formed by forming the dielectric layer 82 and the second plate electrode 84 on the resultant product on which the second storage electrode 80 is formed.

As described above, according to the preferred embodiment of the present invention, the lower capacitor and the upper capacitor connected to the two unit cells are formed by stacking on the plane occupied by two neighboring unit cells. Accordingly, since the surface area of the storage electrode of each capacitor can be maximized, the refresh characteristics of the DRAM device can be improved and the soft error rate can be significantly reduced.

Claims (9)

Forming a pair of cell transistors sharing a common drain region on the semiconductor substrate; Forming a lower interlayer insulating film on an entire surface of the resultant product in which the pair of cell transistors are formed; Forming a lower capacitor connected to any one of the pair of cell transistors on the lower interlayer insulating layer and covering the pair of cell transistor regions; And Forming an upper capacitor superimposed on the lower capacitor and connected to the other one of the pair of cell transistors. The method of claim 1, Forming the lower capacitor Patterning the lower interlayer insulating film to form one contact hole exposing a source region of one of the cell transistors; Forming a first storage node on the lower interlayer insulating layer and connected to the one cell transistor through the one contact hole and covering the pair of cell transistor regions; And And sequentially forming a dielectric film and a first plate electrode on the entire surface of the resultant product on which the first storage node is formed. The method of claim 1, Forming the upper capacitor Forming an upper interlayer insulating film on an entire surface of the resultant product in which the lower capacitor is formed; Successively patterning the upper interlayer insulating layer, the lower capacitor, and the lower interlayer insulating layer to form another contact hole exposing a source region of another one of the pair of cell transistors; Forming insulating spacers on the sidewalls of the other contact hole; Forming a second storage node connected to the other cell transistor and overlapping the first storage node through the other contact hole surrounded by the insulating spacer on the upper interlayer insulating layer; And And sequentially forming a dielectric film and a second plate electrode on the entire surface of the resultant product on which the second storage node is formed. A pair of cell transistors formed on the semiconductor substrate and sharing one common drain region; A lower capacitor covering an area where the pair of cell transistors are formed and connected to any one of the pair of cell transistors; And And an upper capacitor formed on the lower capacitor so as to overlap the lower capacitor and connected to the other one of the pair of cell transistors. The method of claim 4, wherein The lower capacitor A first storage node electrically connected to a source region of the one cell transistor; And And a first film electrode and a dielectric film sequentially formed on the first storage node. The method of claim 5, And the first storage node is electrically connected to a source region of the one cell transistor through a contact hole penetrating a predetermined region of the lower interlayer insulating layer covering the pair of cell transistors. The method of claim 4, wherein The upper capacitor A second storage node electrically connected to the source region of the other cell transistor and overlapping the lower capacitor; And And a second plate electrode and a dielectric film sequentially formed on the second storage node. The method of claim 7, wherein The second storage node may have a source of the other cell transistor through a predetermined region of the upper interlayer insulating layer interposed between the lower capacitor and the second storage node and another contact hole penetrating through the predetermined region of the lower capacitor. And a semiconductor memory device electrically connected to the region. The method of claim 8, And an insulating spacer formed on sidewalls of the other contact hole.