KR20020017813A - Method of manufacturing sram - Google Patents

Abstract

PURPOSE: A fabrication method of an SRAM(Static Random Access Memory) cell is provided to improve a current driving force of cells and to prevent the increase of cell size by increasing cell ratio of the SRAM cell. CONSTITUTION: Gate electrodes(23a,23b) of a transfer and driving transistors(Q1,Q3) are formed on a semiconductor substrate(21). In order to prevent a damage of data when reading of SRAM cells, a cell node(24) as a common junction layer between a source of the transfer transistor(Q1) and a drain of the drive transistor(Q3) is formed by implanting lightly doped dopants using the gate electrodes as a mask. After forming spacers(25a,25b) at both sidewalls of the gate electrodes, source and drain regions(26a,26b) are formed by implanting heavily doped dopants using the gate electrode and the spacers as a mask. A silicide(27) is formed on the surface of the gate electrodes(23a,23b) and the source and drain regions(26a,26b).

Description

Method of manufacturing SRAM {METHOD OF MANUFACTURING SRAM}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device for increasing the safety of cell driving of a static random access memory (SRAM).

In general, SRAM has a smaller memory capacity than DRAM (Dynamic Random Access Memory), but because it operates at a high speed, the memory is medium or small in size, such as a cache memory of a computer that requires a small amount of speed but high speed operation. It is widely used in the field.

The SRAM cell is generally composed of a flip-flop circuit composed of two access transistors, two drive transistors, and two load elements, and memory information includes input and output of the flip-flop. It is preserved as the voltage difference between the terminals, that is, the charge accumulated in the node of the cell.

The above-mentioned charge is always replenished from the constant power supply VCC through the load PMOS transistor or load resistor, which is the load element, so that a refresh function is not required like DRAM.

FIG. 1 is an equivalent circuit diagram of a typical SRAM cell, in which high load resistors R1 and R2 are connected as load elements, word lines W / L are connected to gates, and bit lines or bit lines are connected to drains. The drain terminal is connected to the cell transistors N1 and N2 in which (/ BIT) are connected to one side of the transfer transistors Q1 and Q2 and one side of the high load resistors R1 and R2 and the source terminal of the transfer transistors Q1 and Q2 in common. These are connected and the drain terminal is composed of a drive transistor (Q3, Q4) cross-connected to each other at the gate. A power supply voltage VCC is applied to the other side of the high load resistor, and a ground power supply VSS is applied to the source terminal of the driving transistors Q3 and Q4.

FIG. 2 is a cross-sectional view illustrating a transfer transistor Q1 and a driving transistor Q3 of a typical SRAM cell. The drain 16a of the transfer transistor Q1 is connected to the bit line BIT and the source 16b is driven. Is connected to the drain 16c of the transistor Q3, the drain 16c of the driving transistor Q3 is connected to the source 16b of the transfer transistor Q1 and the source 16d is connected to the ground power supply VSS. do. Here, the source 16c of the transfer transistor Q1 and the drain 16c of the driving transistor Q3 are commonly connected to the cell node N1.

As shown in FIG. 2, after the gate oxide film 12 is formed on the semiconductor substrate 11, the gates of the transfer transistor Q1 and the driving transistor Q3 are spaced apart from each other on the gate oxide film 12. Electrodes 13a and 13b are formed. Subsequently, a low concentration impurity layer, that is, a lightly doped drain (LDD) region 14a and 14b is formed on the semiconductor substrate 11 by using a low concentration impurity ion implantation using the gate electrodes 13a and 13b as a mask. Spacers 15a and 15b are formed in contact with the sidewalls of the electrodes 13a and 13b.

Subsequently, a high concentration impurity layer in contact with the LDD regions 14a and 14b, that is, a source / drain 16a, 16b, 16c, is implanted with high concentration impurity ions using the gate electrodes 13a and 13b and the spacers 15a and 15b as masks. , 16d). Here, the source / drain 16b or 16c to which the transmission transistor Q1 and the driving transistor Q3 are commonly connected among the source / drain is a cell node.

In the general SRAM cell configured as described above, in order to store data in the cell, the inverted relations are driven to the bit line (BIT) and the bit line (/ BIT), and then 1 to the word line (W / L). When the transfer transistors Q1 and Q2 are turned on by turning on the transfer transistors Q1 and Q2, the bit line BIT and the sub-bit line (B) are applied to the cell node which is the drain of the driving transistors Q3 and Q4. / BIT) value is stored.

In order to read the data of the cell, precharge the bit line (BIT) and the bit line (/ BIT) with the same voltage, and then apply 1 to the word line (W / L) to store the data in the cell node. The value changes the positive bit line and the sub bit line to different potentials. In general, a small potential change is amplified using a sense amplifier (SA) that senses the potential change to increase the operation speed.

On the other hand, when using the high load resistors (R1, R2) as the load element as described above, the access transistor (Q1, Q2) and the driving transistor due to the lack of current supply capacity of the high load resistors (R1, R2) during the read operation The data retention of the cell should be possible with only (Q3, Q4). To do this, the current value of the driving transistor (Q3 or Q4) must be much larger than the current value of the transmission transistor (Q1 or Q2). Has a value.

In recent years, as the degree of integration of memory devices increases, the cell size becomes smaller, making it difficult to increase the cell ratio. On the contrary, when the ratio of the current value is increased, the cell size is also increased, thereby increasing the unit cost of the device.

The present invention has been made to solve the problems of the prior art, an object of the present invention is to provide a method for manufacturing a semiconductor device suitable for increasing the driving stability of the cell without increasing the cell size.

1 is an equivalent circuit diagram of a typical SRAM cell;

2 is a view schematically showing a manufacturing method of an SRAM cell according to the prior art;

3A-3D illustrate a method of fabricating an SRAM cell in accordance with an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

21 semiconductor substrate 22 gate oxide film

23a: gate electrode of transfer transistor 23b: gate electrode of drive transistor

24: cell node 25a, 25b: spacer

26a, 26b: high concentration source / drain 27: salicide

Q1: Transmission transistor Q3: Driving transistor

According to an aspect of the present invention, a method of manufacturing an SRAM includes a transfer transistor, a driving transistor, and a load element, and stores data in a cell node in which a source terminal of the transfer transistor and a drain terminal of the driving transistor are commonly joined. The method of claim 1, further comprising: forming a gate electrode of the transfer transistor and the driving transistor at predetermined intervals on a semiconductor substrate; Forming a low concentration source / drain and the cell node on the semiconductor substrate by implanting low concentration impurity ions using the gate electrode as a mask; Forming a spacer in contact with both side walls of the gate electrode such that the gate electrode on the cell node is connected to each other; And a fourth step of forming a high concentration source / drain connected to the low concentration source / drain by high concentration impurity ion implantation using the spacer and the gate electrode as a mask.

Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3A to 3D illustrate a method of manufacturing an SRAM cell according to an exemplary embodiment of the present invention, in which an equivalent circuit of the SRAM cell according to the exemplary embodiment of the present invention is the same as a conventional technology.

As shown in FIG. 3A, an isolation layer (not shown) for isolation between devices is formed on the semiconductor substrate 21, and a gate oxide film 22 is formed on the semiconductor substrate 21. On the oxide film 22, polysilicon for gate electrodes is formed. The polysilicon is selectively etched to form the gate electrode 23a of the transfer transistor Q1 and the gate electrode 23b of the driving transistor Q3. At this time, the distance d between the transfer transistor Q1 and the drive transistor Q3 is not more than twice the thickness of the spacer oxide film formed subsequently.

As shown in FIG. 3B, the LDD regions 24a and 24b and the common junction layer of the transfer transistor and the driving transistor are formed on the semiconductor substrate 21 by implanting low concentration impurity ions using the gate electrodes 23a and 23b as masks. Phosphorus cell nodes 24 are simultaneously formed, and ions implanted with ions are phosphorus (P) or arsenic (As) and their concentration is 1 × 10 ¹³ / cm ^{2 to} 8 × 10 ¹³ / cm ² .

Subsequently, after forming a spacer oxide film on the entire surface including the gate electrodes 23a and 23b, the spacer oxide film is anisotropically etched to form spacers 25a and 25b in contact with both sidewalls of the gate electrodes 23a and 23b. . In this case, the spacer oxide film is formed to be more than twice the interval between the transfer transistor Q1 and the driving transistor Q3 to fill the gap between the two transistors, and the spacers 25a and 25b are formed on the gate electrodes 23a and 23b. It is formed only on the sidewalls, and the insulating film is not completely removed between the two transistors, which is not performed during the subsequent ion implantation process.

As shown in FIGS. 3C and 3D, a high concentration of impurity ion implantation using the spacers 25a and 25b and the gate electrodes 23a and 23b as a mask is performed to contact the LDD regions 24a and 24b. / Drains 26a and 26b are formed, and the high concentration of impurities implanted with ions is made of arsenic (As), and the concentration of arsenic is 1 × 10 ¹⁵ / cm ^{2 to} 8 × 10 ¹⁵ / cm ² . At this time, since the spacers 25a and 25b are connected to each other between the two transistors, ion implantation is not performed and only the cell node 24 which is a low concentration impurity layer is formed.

Here, the ion implantation of the high concentration impurity uses two methods, a vertical ion implantation and a tilt implantation, both of which are implanted between the transfer transistor Q1 and the driving transistor Q3. However, since the ion implantation with the inclination goes deeper into the channel of the transistor, the current value of the transistor becomes larger.

3C shows a salicide 27 on the top surface of the gate electrodes 23a and 23b and the surface of the source / drain 26a and 26b after the vertical ion implantation is performed to further lower the resistance on the source / drain side. 3D shows the top surfaces of the gate electrodes 23a and 23b and the source / drains 26a and 26b in order to lower the resistance on the source / drain 26a and 26b side after the gradient ion implantation is performed. The salicide 27 was formed in the surface of this.

The salicide 27 is a metal alloy formed only on the semiconductor substrate 21 or polysilicon gate electrodes 23a and 23b exposed to the surface, and is an insulating film between the transfer transistor Q1 and the driving transistor Q3. Since the spacers 25a and 25b are connected, no salicide is formed.

As described above, according to the exemplary embodiment of the present invention, as a method of increasing the cell ratio so that the data of the cell is not damaged during the read operation of the SRAM cell, the source of the transfer transistor Q1 and the drain of the driving transistor Q3 are in contact with each other. Since a high concentration of impurity ions are not implanted and no salicide is formed in the cell node 24, which is a bonding layer, the current value of the transfer transistor Q1 is decreased, and the resistance of the drain of the driving transistor Q3 is increased, but the source ( The current value increases by lowering the resistance by forming a high concentration of impurity ion implantation and salicide 27 in 26b).

In other words, when the resistance on the source / drain side is increased, the resistance of the source 26b of the driving transistor Q3 is lowered, in particular, in order to improve the current driving capability of the transistor which is more affected by the source side and decreases.

As described above, an embodiment of the present invention configures the cell transistors asymmetrically to secure stable operation characteristics of the cell without increasing the cell size, thereby limiting ion implantation between the transfer transistor and the driving transistor, thereby driving the current of the transfer transistor. The cell ratio can be increased by maintaining or further increasing the current driving capability of the driving transistor while weakening the capability.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

The method of manufacturing a semiconductor device of the present invention as described above increases the resistance of the junction layer between the transfer transistor and the drive transistor, decreases the source side resistance of the drive transistor, and increases the cell ratio of the SRAM cell. By preventing damages, it is possible to secure stable cell operating characteristics, and by asymmetrically configuring cell transistors, there is an effect of preventing increase in cell size.

Claims (6)

A method of manufacturing an SRAM including a transfer transistor, a driving transistor, and a load element, and storing data in a cell node in which a source terminal of the transfer transistor and a drain terminal of the driving transistor are commonly joined. Forming a gate electrode of the transfer transistor and the driving transistor at a predetermined interval on a semiconductor substrate; Forming a low concentration source / drain and the cell node on the semiconductor substrate by implanting low concentration impurity ions using the gate electrode as a mask; Forming a spacer in contact with both side walls of the gate electrode such that the gate electrode on the cell node is connected to each other; And A fourth step of forming a high concentration source / drain connected to the low concentration source / drain by implanting high concentration impurity ions using the spacer and the gate electrode as a mask; Method for producing a cell, characterized in that comprises a. The method of claim 1, The third step, Forming an insulating film for a spacer on the resultant of the second step; And Anisotropically etching the spacer insulating film to form a spacer in contact with both sidewalls of the gate electrode Method for producing a cell, characterized in that comprises a. The method of claim 1, In the third step, And a thickness of the spacers connected to each other is greater than a distance between the gate electrodes. The method of claim 1, In the third step, The spacer is a cell manufacturing method, characterized in that formed in the form of being buried between the gate electrode on the cell node. The method of claim 1, In the fourth step, The high concentration source / drain may be formed using any one of vertical ion implantation or gradient ion implantation. The method of claim 1, After the fifth step, Forming a salicide film on the gate electrode and the top surface of the high concentration source / drain.