KR20020017760A - Mask of semiconductor device and method for manufacturing thereof - Google Patents

Abstract

PURPOSE: A mask of a semiconductor device is provided to efficiently protect a mask from contaminant and to repair the mask, by preventing contamination from particles generated when the mask is fabricated or used. CONSTITUTION: A wafer(21) has a plurality of window regions(25). The first and second regions(26a,26b) of an upper membrane are formed on the wafer, having the first and second thicknesses. At least one of the first and second regions corresponds to the window region. A scattering layer(23a) of the third thickness is formed on the second region of the upper membrane, having the same height as the first region of the upper membrane. A lower membrane layer is formed on the lower surface of the wafer.

Description

Mask of semiconductor element and manufacturing method therefor {MASK OF SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THEREOF}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to mask fabrication, and more particularly, to a mask of a semiconductor device and a method for manufacturing the mask, which protect the mask from contaminants such as particles generated during fabrication and use of the mask used in the SCALPEL technology and efficiently repair the mask will be.

One of the important factors in the semiconductor manufacturing process is to increase the number of dies per wafer by increasing the density of active devices provided on a single semiconductor die.

Ultra-Large Integrated Circuits (VLSIs) have evolved into Ultra-Large Integrated Circuits (ULSI), with thousands or hundreds of millions of active elements and devices located on a single integrated circuit (IC) die.

This density is obtained by presently manufacturing devices with the smallest physical device size (ie, critical size (CD)) on the order of 0.18 microns.

It is desirable to further reduce the critical sizes (CDs) of active devices and other devices on semiconductor dies to more than 0.18 microns in order to continuously improve this density and continue to improve device speed without significantly increasing die size. Do.

Hereinafter, a reticle of a semiconductor device of the prior art will be described with reference to the accompanying drawings.

1 is a block diagram showing the principle of the general SCALPEL technology.

Lithography techniques are commonly used in the formation of multilevel circuits on semiconductor dies of 0.18 microns or more.

Current lithography techniques use i-line (365 nanometers) and deep ultraviolet (DUV, 248 nanometers) energy sources to produce micron device sizes of 0.25 to 0.18.

By reducing the wavelength of energy used in these lithography techniques, smaller active elements and transistors are realized by creating smaller threshold sizes (CDs).

Thus, smaller wavelength, higher energy sources, including deep ultraviolet (DUV) (193 nanometers) and extreme ultraviolet (EUV) (approximately 11.0 to 13.4 nanometers) and X-ray sources, have many Research is ongoing.

One of the other lithographic techniques, an electron-beam lithography projection system, scans a beam at extremely high speed across a masked surface to produce an image on a semiconductor device.

Electro-optic can be inserted into the E-beam transmission path providing a means of good image reduction. One particular type of projection electron beam lithography is known as scattering (SCALPEL) with angle limitation in electron-beam lithography projection.

SCALTEL (SCattering with Angular Limitation in Projection Electron beam Lithorgraphy) is described as follows.

As shown in FIG. 1, the mask 10 having the patterned scattering layer 11 is formed on the membrane film 12, and the electron beam E-beam through the mask 10 is as shown by the arrow of FIG. 1. Projected.

In particular, the patterned scattering layer 11 comprises a material having a higher atomic number than the atomic number of the membrane film 12.

The scattering effect of the electron beam is characterized by the fact that the electron beams passing through the scattering layer 11 between the membrane film 12 and the lens 13 are the parts of the E-beam passing through the film material not lying on the scattering layer 11. In comparison, they tend to expand significantly.

The electron beam passes through the mask 10 and is focused through an electron focus system represented by the lens 13. The electron beam (E-beam) passes through a back focal plane aperture 14.

The focal plane filter 14 has an opening to allow electron beams that are not scattered by the scattering layer 11 of the mask 10 to pass through.

That is, beams scattered above the finite critical angle do not pass through the focal plane filter 14 while all beams having a scattering angle less than or equal to the finite critical angle are passed by the focal plane filter 14.

The portion of the electron beam that passes through the focal plane filter 14 is then projected onto the semiconductor wafer 15 having a resistive layer and a plurality of dies formed on the semiconductor wafer.

The SCALPEL technology solves the productivity problem, which is the biggest drawback of electron lithography with a resolution of 0.10 µm or less, and the mask is manufactured at a magnification of X4.

Such a structure of the mask of the prior art has the following problems.

When contamination sources such as particles generated during fabrication or use of masks are present in curved portions between scattering layers, mask repair becomes difficult.

The present invention is to solve such a problem of the mask of the prior art SCALPEL technology, to protect the mask from contaminants such as particles generated during the fabrication and use of the mask used in the SCALPEL technology and to efficiently repair the mask. It is an object of the present invention to provide a mask of a semiconductor device and a manufacturing method thereof.

1 is a block diagram showing the principle of the general SCALPEL technology

2A to 2G are cross-sectional views for manufacturing a mask of a semiconductor device according to the present invention.

-Explanation of symbols for the main parts of the drawing-

21. Wafer 22a. Material layer for forming upper membrane

22b. Material layer for lower membrane formation 23. Material layer for scattering layer formation

23a. Scattering Layer 24. Shield

25. Window Area 26a. Upper membrane first area

26b. Upper Membrane Second Area 27. Lower Membrane Film

According to an aspect of the present invention, a mask of a semiconductor device may include: a wafer having a plurality of window regions; at least one region having a first and second thicknesses different from each other and corresponding to the window regions; An upper membrane first region and an upper membrane second region formed on the upper membrane; a scattering layer having a third thickness on the upper membrane second region and having the same height as the upper membrane first region; formed on the lower surface of the wafer Characterized in that it comprises a lower membrane film, the method of manufacturing a mask of a semiconductor device according to the present invention comprises the steps of forming a material layer for forming an upper membrane and a material layer for forming a lower membrane on the upper and lower portions of the wafer; The membrane of the first thickness is selectively removed by selectively removing the membrane forming material layer. Defining a first region and an upper membrane second region having a second thickness; forming a scattering layer forming material layer on the first and second upper membrane regions and planarizing to form a scattering layer on the upper membrane second region Forming a protective film on the entire surface including the scattering layer, and etching the lower and lower membrane forming material layers of the wafer to define a window region; removing the protective film and performing a repair process. It is characterized by.

Hereinafter, a mask of a semiconductor device and a method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings.

2A to 2G are cross-sectional views for manufacturing a mask of a semiconductor device according to the present invention.

The present invention is to repair the contamination such as particles generated during the manufacture or use of the mask in a structure that eliminates the bending between the scattering layer in an easier way.

The structure has a wafer 21 having a plurality of window regions 25 formed in a hole shape, and has a first and second thicknesses different from each other on top of the wafer 21 and at least corresponding to the window regions 25. The upper membrane first region 26a and the upper membrane second region 26b formed by including one or more regions, and the upper membrane first region 26a having a third thickness on the upper membrane second region 26b. ) And a scattering layer 23a formed at the same height as that of the wafer) and a lower membrane film 27 formed on the lower surface of the wafer 21.

Here, the first thickness and the second thickness + third thickness are the same.

The upper and lower membranes are made of nitride film Si ₃ N ₄ , and the scattering layer 23a is made of tungsten (W).

The scattering layer 23a is configured to correspond to at least one window area 25.

The manufacturing process of the mask of the semiconductor element which concerns on this invention which has such a structure is as follows.

First, as shown in FIG. 2A, Si ₃ N ₄ or the like is deposited on both sides of the wafer 21, that is, the upper and lower portions, by a low pressure chemical vapor deposition (LPCVD) process to form an upper membrane forming material layer 22a and a lower membrane. The forming material layer 22b is formed.

Here, as the material layer for forming the membrane, SiC, BC, BN, etc. may be used in addition to Si ₃ N ₄ .

Subsequently, as shown in FIG. 2B, a photoresist (not shown) is coated on the front surface and selectively patterned, and then the exposed upper membrane forming material layer 22a is removed by using a predetermined thickness. An upper membrane first region 26a and an upper membrane second region 26b of a second thickness, where first thickness-second thickness = third thickness, are defined.

As shown in FIG. 2C, the material layer 23 for forming the scattering layer is formed by depositing W, Au, or Pt on the upper membrane first region 26a and the upper membrane second region 26b.

Subsequently, as shown in FIG. 2D, the scattering layer forming material layer 23 is planarized by a chemical mechanical polishing (CMP) process to form the scattering layer 23a.

Here, the scattering layer 23a is formed to have a third thickness so that the uppermost layers formed on the wafer 21 are all planarized.

As shown in FIG. 2E, Cr or the like is deposited on the scattering layer 23a to form a protective film 24.

The protective film 24 is used as a protective layer in an etching process for defining a subsequent window area.

Subsequently, as shown in FIG. 2F, the lower (back) and lower membrane forming material layers 22b of the wafer are etched using a KOH solution to define the window region 25.

The lower membrane film 27 is formed at the time of defining the window region 25.

As shown in FIG. 2G, the Cr layer used as the protective film is removed at the window region 25 definition, and the inspection and repair processes are performed to complete the mask fabrication process.

Such a mask of a semiconductor device and a manufacturing method thereof according to the present invention has the following effects.

There is no bending between the scattering layers to prevent contamination from particles that occur during fabrication or use of the mask.

In addition, there is an effect that the repair process can be efficiently carried out when the mask is contaminated.

Claims (6)

A wafer having a plurality of window regions; An upper membrane first region and an upper membrane second region having different first and second thicknesses on the wafer and including at least one region corresponding to the window region; A scattering layer having a third thickness on the upper membrane second region and formed at the same height as the upper membrane first region; And a lower membrane film formed on the lower surface of the wafer. The mask of claim 1, wherein the scattering layer is configured to correspond to at least one window area. Forming an upper membrane forming material layer and a lower membrane forming material layer on top and bottom of the wafer; Selectively removing a thickness of the upper membrane forming material layer to define an upper membrane first region having a first thickness and an upper membrane second region having a second thickness; Forming a scattering layer forming material layer on the upper membrane first and second regions and planarizing to form a scattering layer on the upper membrane second region; Forming a passivation layer on the entire surface including the scattering layer and defining a window region by etching the lower and lower membrane forming material layers of the wafer; Removing the protective film and performing a repair process. The method of manufacturing a mask of a semiconductor device according to claim 3, wherein during the step of forming the scattering layer, the scattering layer and the upper membrane first region are planarized to have the same height. The method of claim 3, wherein the material layer for forming a membrane is formed by depositing any one of Si ₃ N ₄ , SiC, BC, and BN by an LPCVD process. The method of claim 3, wherein the scattering layer forming material layer is formed by depositing either W, Au, or Pt.