KR20020017752A - The structure of thyristor-sram and method for manufacturing the same - Google Patents

Abstract

PURPOSE: A thyristor-type static random access memory(TSRAM) is provided to control an on/off operation of a thyristor through an operation of a drain of an access transistor and a PN diode of a P well, by forming a vertical thyristor by an epitaxial growth method. CONSTITUTION: The P well(23) is isolated in a row direction of a semiconductor substrate(22). A word line(25) is formed on the P well. An n-type source/drain region is formed in the P well under the word line. The thyristor of a vertical structure is epitaxially grown on a connection portion of the n-type source region and the P well to induce a diode operation of the P well.

Description

Thyristor type SRAM and method for manufacturing thereof {TH STRUCTURE OF THYRISTOR-SRAM AND METHOD FOR MANUFACTURING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a memory device, and more particularly, to a method for manufacturing a high speed thyristor type SRAM cell.

In general, memory devices include DRAM, SRAM, flash memory, etc. The dual DRAM has a small cell size but low speed and high power consumption due to standby current due to characteristics of refresh.

In addition, SRAM has a high speed and excellent standby characteristics, but has a problem in that a manufacturing cost increases due to a large cell size, and a flash memory has a small cell size and excellent standby characteristics, but a fast write operation is impossible.

In order to solve the shortcomings of these memory devices, a thyristor type SRAM cell has been proposed (A Novel Thyristor-based SRAM Cell (T-RAM) for High-speed, Low voltage, Giga-scale Memories, Farid Nemati and James D. Plummer) , 1999 IEEE).

Typically, an SRAM cell consists of a flip-flop circuit consisting of two access transistors, two drive transistors, and two load elements, and memory information includes input and output of the flip-flop. It is preserved as the voltage difference between the terminals, that is, the charge accumulated in the node of the cell.

1 is an equivalent circuit diagram of a conventional Dyster SRAM (TSRAM) cell, and FIG. 2 is a device cross-sectional view of the Dyster SRAM cell.

As shown in FIG. 1, the thyristor SRAM (hereinafter referred to as T-RAM) is a bistable element, which is a vertical thyristor 10 and an access transistor including a surrounding MOS gate. It is composed of a Planar NMOS (11), the source of the NMOS 11 is connected to the bit line (BL), the drain is connected to the lowermost layer of the thyristor 10 and the gate is the first word line (WL1) Is connected to.

As shown in FIG. 2, a pillar-shaped P-shaped silicon pillar 12a formed by etching the P-type silicon substrate 12 is formed, and a cap oxide film is formed on the P-type silicon pillar 12a. Arsenic is implanted and diffused to form the N + region 13 which is the lowest layer of the thyristors.

Subsequently, a gate oxide layer (not shown) and polysilicon are sequentially formed, and then the polysilicon is anisotropically etched to form a first wordline 14 and a second wordline 15 having sidewalls.

Subsequently, the source region 16 and the drain region 17 are formed by impurity ion implantation using the first and second word lines 14 and 15 as masks, and the N-type impurities and P are formed in the P-type silicon pillar 12a. The N-type region 18 / P + region 19 is formed by sequentially ion implanting the impurity.

As described above, impurities are ion-implanted into the silicon pillars formed by etching the P-type silicon substrate 12 in the form of pillars, thereby forming a thyristors having a vertical structure of P + / N / P / N +, and turning on the thyristors. In order to control the on / off, a vertical NMOS is additionally formed using the second word line 15 as a gate electrode.

However, the above-described TSAM of the prior art is unstable in the process of etching the silicon substrate 12 in the form of a pillar, and there is a problem in forming a stable access transistor on the etched silicon substrate.

In addition, it is difficult to adjust the doping profile of P + / N / P / N + to have a stable die thruster characteristics, the holding current (I _h ) by the voltage applied to the second word line according to the pillar thickness and There is a problem that the forward breakover voltage (V _FB ) is changed.

In addition, it is difficult to define the second word line vertically, the alignment of the layer to overcome the pillar height of 1 μm is not easy, and the first word line / second word line / bit line may be used to realize high-speed write / read time. Accurate synchronization of the signal is required, and in particular, there is a difficulty in minimizing the rise and fall times of the signal.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and simplifies the process of forming additional transistors for controlling the on / off of the thyristors during TSRAM formation, and the pillar-shaped thyristors formed by etching silicon substrates. It is an object of the present invention to provide a thyristor-type SRAM suitable for preventing unstable operation and a manufacturing method thereof.

1 is an equivalent circuit diagram of a thyristor-type SRAM according to the prior art;

2 is a structural cross-sectional view of a diester type SRAM according to the prior art;

3 is an equivalent circuit diagram of a thyristor-type SRAM according to an embodiment of the present invention;

4 is a structural cross-sectional view of a die thruster type SRAM according to an embodiment of the present invention;

FIG. 5 is a block diagram illustrating an arrangement of the thyristor-type SRAMs of FIG. 4;

6A and 6B illustrate a method for separating the P well of FIG. 4;

7A to 7D illustrate a method of manufacturing a thyristor type SRAM according to an embodiment of the present invention.

* Explanation of symbols for the main parts of the drawings

20: Thyristor 21: NMOS

22: semiconductor substrate 23: P well

24 gate oxide 25 word line

26: LDD area 27: spacer

28: source 29: drain

30: first interlayer insulating film 31: P-type silicon pillar

32: N-type impurity layer 33: P + impurity layer

34 VCC line 35 Second interlayer insulating film

36: bit line

The thyristor type SRAM cell of the present invention for achieving the above object is a P well isolated in a column direction on the semiconductor substrate; A word line formed on the P well; An N-type source / drain region formed in the P well below the word line; And a vertical thyristor epitaxially grown over the connection portion between the N-type source region and the P well to cause diode operation of the N-type drain region and the P well. A method of fabricating a thyristor type SRAM cell of the method comprises the steps of: forming P wells isolated from each other in a column direction; Forming an access transistor on said P well; Forming an interlayer insulating film on the entire surface including the existor transistor; Selectively etching the interlayer insulating layer to expose the source region and the P well of the exciter transistor simultaneously; Forming a P-type silicon pillar by epitaxial growth on the exposed portion; Doping N-type impurities into the P-type silicon pillar to form an N-type region; And forming a P-type region in direct contact with the N-type region by doping the P-type impurity into the P-type silicon pillar.

Hereinafter, the most preferred embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art can easily implement the technical idea of the present invention. .

3 is an equivalent circuit diagram of a TSRAM according to an embodiment of the present invention, and FIG. 4 is a structural cross-sectional view of a TSRAM according to an embodiment of the present invention.

As shown in FIG. 3, a TSRAM according to an embodiment of the present invention will be described. The vertical thyristor 20 and one NMOS 21 which are an excistor are included, and the thyristor 20 is formed. One side of the VCC voltage is applied, the other side is connected to the source of the NMOS 21, the drain of the NMOS 21 is connected to the bit line and the gate is connected to the word line (WL).

As shown in FIG. 4, in the TSRAM according to the exemplary embodiment of the present invention, a P well 23 is formed on a semiconductor substrate 22, and a word line 25 is formed on the P well 23. NMOS sources / drains 28 and 29 are formed in the P wells 23 on both sides of the word line 25. In addition, the source 28 and the P well 23 are commonly overlapped with each other to form a thyristors having a P + / N / P / N + (28, 31, 32, 33) structure.

In the above TSRAM, the diester 20 has a stacked structure of P + / N / P / N + (28, 31, 32, 33), and the N + impurity layer 28, which is the lowest layer of the diester 20, is an NMOS. It is connected to the source 28 of (21) in common, but is connected by overlapping a predetermined width. The gate of the NMOS 21 is a word line (WL) 24 and the drain 29 of the NMOS 21 is connected to a bit line 36.

The TSRAM of the present invention as described above adjusts the ON / OFF state of the thyristor 20 by a method of injecting electrons (e) into the drain 29 of the NMOS 21 which is an excistor.

At this time, in forming the P wells 23, the P wells P1, P2, P3, P4,..., Each other in order to prevent interference between the cells in the row and column directions. Separately, the bias can be adjusted individually (see FIG. 5).

6A and 6B illustrate a method of separating the respective column P wells P1, P2, P3, P4, ... to prevent interference between subsequent row and column cells. It is a diagram showing.

As shown in FIG. 6A, the SOI wafer 41 having the oxide film formed on the silicon substrate is etched by a shallow trench isolation (STI) to form a trench, and a high density plasma oxide film (High) is formed on the entire surface including the trench. Density Plasma Oxide (42) is formed, and then the high-density plasma oxide film 42 is chemically mechanically polished to form a device isolation film embedded in the trench, thereby forming a well strip and forming P wells separated from each other. P1, P2, P3, P4, ...) are formed.

As shown in FIG. 6B, each P well P1, P2, P3, P4, between the N wells 44 spaced at regular intervals by applying a conventional triple well forming method on the N + buried layer 43. ...)

As described above, in the TSRAM according to the exemplary embodiment of the present invention, when a voltage of −0.6 V is applied to the bit line 36, electrons are injected from the drain 29, and the injected electrons are injected from the P well 23. Diffusion penetrates into the N region 32 of the thyristor to turn on the thyristor. At this time, the P wells of the column cells other than the selected cell apply a voltage of −0.6 V or less, and thus electrons are not injected even if −0.6 V is applied to the bit line 36. Therefore, electrons can be injected only in selected cells, and only one cell can be read / write.

The off of the thyristor is controlled by applying VCC to the bit line 36 and VCC to the word line 25.

7A to 7D illustrate a method of manufacturing a TSRAM according to an embodiment of the present invention.

As shown in FIG. 7A, an isolated P well is formed by applying an STI process on an SOI wafer, or an N well or P well is formed on a buried layer to form an isolated P well. In the present invention, a method of forming an NMOS and a thyristor on a P well 23 is shown.

An existor transistor is formed on the P well 23. A gate oxide film 24 is formed on the P well 23 by applying a conventional technique, and then a word made of polysilicon is formed on the gate oxide film 24. A line 25 is formed, and the LDD region 26 is formed using the word line as a mask. After the spacers 27 are formed in contact with both sidewalls of the word line 25, a source contacting the LDD region 26 by impurity ion implantation using the word lines 25 and the spacers 27 as a mask. / Drains 28 and 29 are formed.

Subsequently, after the first interlayer insulating film 30 is formed on the entire surface including the exciter transistor, the first interlayer insulating film 30 is selectively etched so that the source 28 and the P well 23 are commonly connected. Expose the part. Here, the portion of the first interlayer insulating layer 30 that is etched to expose the source 28 by a predetermined width is a portion that will form a pillar of the subsequent thyristor, and the source 28 which is an active region to enable the diffusion path of the subsequent electrons. And P well 23 are etched in common.

As shown in FIG. 7B, after forming a silicon pillar for the diester by epitaxial growth in the exposed source region 28 and the P well 23, a P-type dopant of boron (B) or indium (In) is formed. P-doped silicon pillars 31 are formed in-situ by doping. At this time, the P-type dopant is doped to a concentration of 1 × 10 ¹⁵ ~ 1 × 10 ¹⁹ cm ^-3 .

As shown in FIG. 7C, an N-type impurity of either phosphorus (P) or arsenic (As) is ion-implanted into the P-type silicon pillar 31 to form an N-type impurity layer 32. P-type impurities of either boron or BF ₂ are ion-implanted to form the P + impurity layer 33, thereby forming a thyristors having a P + / N / P / N + structure. In other words, the N + type source 28 of the existor transistor is vertically connected to the lower side of the epitaxially grown P + / N / P.

As shown in FIG. 7D, a metal is formed on the entire surface including the P + impurity layer 33 and then selectively patterned to form a VCC line 34 connected to the P + impurity layer 33.

Subsequently, a second interlayer insulating film 35 is formed on the entire surface including the VCC line 34, and then the second interlayer insulating film 35 and the first interlayer insulating film 30 are selectively etched simultaneously to drain NMOS. ) Forms a bit line contact hole. Subsequently, a metal is formed on the entire surface including the bit line contact hole, and then selectively patterned to form the bit line 36.

As described above, the TSRAM of the present invention has a static characteristic of retaining data as long as power is supplied, and a cell area as small as that of a door DRAM composed of one transistor and a vertical diester is possible.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the TSRAM of the present invention and its manufacturing method form epitaxial growth by means of epitaxial growth, so that the drain of the existor transistor and the PN of the P well do not require additional NMOS to control the on / off of the die Lister. Diode operation controls the on / off of the thyristor, resulting in a stable TSRAM cell.

Claims (13)

In the SRAM cell, A P well isolated in a thermal direction from the semiconductor substrate; A word line formed on the P well; An N-type source / drain region formed in the P well below the word line; And Vertical thyristors that are epitaxially grown over the connection portions of the N-type source region and the P well to cause diode operation of the N-type drain region and the P well. The thyristor-type SRAM comprising a. The method of claim 1, The P well is a thyristor-type SRAM, characterized in that formed on the SOI wafer using the STI process. The method of claim 1, The P well is a thyristor-type SRAM, characterized in that having a triple well structure. The method of claim 1, The thyristor is a P region doped with an epitaxially grown silicon pillar, a P region doped with a P type dopant, an N region doped with an N type dopant in the P region, and a P + vertically connected with a P type dopant in the N region. And a region P, wherein the region P is connected to the N-type source region. The method of claim 1, And the N-type drain region is connected to a bit line. The method of claim 1, The die thyristor of the vertical structure is connected to the VCC line. In the manufacturing method of the SRAM cell, Forming P wells isolated from each other in a thermal direction; Forming an access transistor on said P well; Forming an interlayer insulating film on the entire surface including the existor transistor; Selectively etching the interlayer insulating layer to expose the source region and the P well of the exciter transistor simultaneously; Forming a P-type silicon pillar by epitaxial growth on the exposed portion; Doping N-type impurities into the P-type silicon pillar to form an N-type region; And Doping a P-type impurity into the P-type silicon pillar to form a P-type region that is in direct contact with the N-type region Method for producing a thyristor-type SRAM comprising a. The method of claim 7, wherein Forming the P well is, Forming a trench in the SOI wafer using a device isolation process; Forming a high density plasma oxide film on the entire surface including the trench; And Performing a chemical mechanical polishing process to form P wells isolated from each other by high density plasma oxide embedded in the trench; Method for producing a thyristor-type SRAM comprising a. The method of claim 7, wherein Forming the P well, Forming an N + impurity layer embedded in the silicon substrate; Alternately forming N wells and P wells on the N + impurity layer to form the isolated P wells Method for producing a thyristor-type SRAM comprising a. The method of claim 7, wherein Forming the P-type silicon pillar, Forming an epitaxial silicon layer on the exposed N-type source region and the P well and doping the P-type impurity in situ to form the P-type silicon pillar Method for producing a thyristor-type SRAM comprising a. The method of claim 10, Said P-type impurity uses a boron or indium having a concentration of 1 × 10 ^{15 to} 1 × 10 ¹⁹ cm ^-3 . The method of claim 7, wherein In the forming of the N-type region, The N-type impurity is a method for producing a thyristo type SRAM, characterized in that using the phosphorus or arsenic. The method of claim 7, wherein In the forming of the P-type region, The p-type impurity is a method for producing a thyristor type SRAM, characterized in that using boron or BF ₂ .