KR20020016123A - Protection Circuit of CCD - Google Patents

Abstract

PURPOSE: A protection circuit of a charge coupled device(CCD) is provided to maintain a low level potential of a p well region, not by applying a protection voltage through an external pin, but by applying the protection voltage from the inside of the protection circuit. CONSTITUTION: One end of the first capacitor is connected to a clock signal terminal. A cathode terminal of a diode(8) is connected to the other end of the first capacitor(6). The gate and one terminal of a metal-oxide-semiconductor(MOS) transistor(7) are connected in common to the cathode terminal of the diode, and the other end of the MOS transistor is connected to the ground terminal. The second capacitor(9) is connected between the anode terminal of the diode and the ground terminal.

Description

CDC Protection Circuits {Protection Circuit of CCD}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a CCD image pickup device, and more particularly to a protection bias circuit of a CD to which a protection voltage Vp can be applied internally.

A CCD image pickup device is a semiconductor device having an 'eye of eye' function and is a kind of solid state image pickup device that converts an image signal into an electric signal. In particular, when scanning and reading an image signal, it is output as a time-series signal using charge coupling, and thus it is called a CCD (Charge Coupled Device) image sensor and is generally referred to as a CCD. Strictly speaking, however, CCDs refer to all devices that use charge coupling, and are used in signal processing, memory, as well as image sensors.

CCDs can be broadly divided into light-receiving sites, channel sites that carry charges, and detectors that detect the amount of signal charge and convert it into voltage.

Hereinafter, a protection circuit of a conventional CCD will be described with reference to the accompanying drawings.

1 is a structural cross-sectional view showing a protection circuit of a CCD according to the prior art.

The CCD has VCCD for vertical charge transfer and HCCD for horizontal charge transfer. Typically, a clock having three levels of 15V, 0V, and -9V is used as the clock for driving the VCCD. In order to prevent a current path from being formed, a protection circuit for applying a protection voltage Vp of -9V from the outside is provided.

In the conventional CCD structure, as shown in FIG. 1, a P-well 2 is formed in a semiconductor substrate 1, and an impurity region is formed at a predetermined interval in the surface of the P-well 2 region. Phosphorus first, second and third impurity regions 3, 4 and 5 are formed.

The first impurity region 3 is doped with n + impurity and connected to the Vclock terminal, and the second impurity region 4 is doped with n + impurity and connected to the ground terminal, and the third impurity region 5 is The p + impurity is doped and connected to the protection voltage (Vp) terminal.

In this case, the protection voltage Vp is a voltage applied from the outside to set the potential of the P-well 2 to a low level of the Vclock signal.

At this time, since the Vclock signal uses a clock having three levels of 15V, 0V, and -9V, the externally applied protection voltage Vp uses the same -9V voltage as the low level value of the Vclock voltage signal.

In the operation of the protection circuit configured as described above, the potential of the P-well 2 is set to -9V by applying a voltage of -9V, which is the protection voltage Vp, to the third impurity region 5, which is a p + doping region.

At this time, if the potential of the P-well 2 is set to -9V, which is the low level voltage of Vclock, a current path to the substrate is not formed even when the Vclock operates at a low level (-9V). .

However, since the protection circuit of the CCD according to the related art has to apply a protection voltage Vp of -9V through an external pin, the number of pins increases and the package size also increases.

The present invention has been made to solve the above problems, and an object thereof is to provide a protection circuit of a CCD for applying a protection voltage therein.

1 is a structural cross-sectional view showing a protection circuit of a CCD according to the prior art.

2 is a circuit diagram showing an equivalent circuit of a protection circuit of a CCD according to the present invention.

3 is a cross-sectional view of a structure implementing an equivalent circuit of a protection circuit of a CCD according to the present invention.

4A-4C are Vclock voltage waveform diagrams varying at each node.

Explanation of symbols for the main parts of drawings

6: first capacitor 7: MOS transistor

8: diode 9: second capacitor

A protection circuit of a CCD according to the present invention for achieving the above object includes a first capacitor having one end connected to a clock signal terminal, a diode having a cathode end connected to the other end of the first capacitor, and A gate and one end of the diode are commonly connected to the cathode of the diode, and the other end of the MOS transistor is connected to the ground terminal, and a second capacitor is connected between the anode terminal and the ground terminal of the diode.

Hereinafter, a protection circuit of a CCD according to the present invention will be described in detail with reference to the accompanying drawings.

2 is an equivalent circuit diagram showing a protection circuit of a CCD according to the present invention.

First, as shown in FIG. 2, the protection circuit of the CCD according to the present invention is connected to the Vclock terminal to lower the potential of the Vclock signal by a predetermined voltage, and one of the first capacitors 6 A diode 8 having a stage and a cathode terminal connected thereto, a MOS transistor 7 having a gate and one stage connected to the cathode terminal of the diode 8 in common and the other stage connected to a ground terminal, and the diode The second capacitor 9 is connected between the anode end and the ground end of (8).

At this time, the MOS transistor 7 has a gate terminal and one end connected in common between the first capacitor 6 and the diode 8 (node a), so that the Vclock signal changed through the first capacitor 6. It is turned on or off depending on the voltage, which is turned on when the voltage Va is positive based on the ground voltage, and turned off when the voltage is negative.

Therefore, a diode may be formed in place of the MOS transistor 7 between one end of the first capacitor 6 and the ground end, or elements that may serve as switching in accordance with the change of the Vclock signal may be configured instead. .

4 is a structural cross-sectional view of a protection circuit of a CCD in accordance with the present invention, which implements the equivalent circuit shown in FIG.

Here, the elements shown in the equivalent circuit of FIG. 3 use the same reference numerals, and the individual elements are formed by the known process of forming common elements although only the formation position and the connection structure are indicated.

As shown in FIG. 4, first, second, and third impurities in which a P-well 11 is formed in the semiconductor substrate 10 and doped with n + impurities at regular intervals in the surface of the P-well 11 are formed. Regions 12, 13 and 14 are formed.

The first capacitor 6 is formed between the first impurity region 12 and the second impurity region 13, and the MOS transistor 7 is formed between the second impurity region 13 and the third impurity region 14. ) Is formed, a diode 8 is formed between the second impurity region 13 and the P-well 11, and a second capacitor is formed between the third impurity region 14 and the P-well 11. (9) is formed.

Here, the diode 8 has a cathode terminal connected to the second impurity region 13 and an anode terminal connected to the P-well 11.

The first impurity region 12 and the first capacitor 6 are commonly connected to the Vclock terminal, the gate and the second impurity region 13 of the MOS transistor 7 are connected to each other, and the third impurity region. 14 is grounded.

Next, the operation of the protection circuit of the CCD configured as described above is as follows.

4A to 4C are waveform diagrams illustrating waveforms in which Vclock voltage waveforms change at each node through a protection circuit.

FIG. 4A is a voltage waveform diagram of Vclock as a clock signal for driving a VCCD, FIG. 4B is a voltage waveform diagram of Vclock through a first capacitor, and FIG. 4C is a voltage of a protection voltage Vp finally applied to a P-well. It is a waveform diagram.

First, when the Vclock voltage shown in FIG. 4A passes through the first capacitor 6, the signal shown in FIG. 4B may be obtained.

At this time, the voltage of the node a is arbitrarily called Va.

According to the voltage value Va passed through the first capacitor 6, the MOS capacitor 7 and the diode 8 are turned on or turned off so that the second capacitor 9 repeatedly charges / discharges and thus the constant DC voltage value. Is supplied to the P-well 11.

First, in FIG. 4B, the MOS transistor 7 is turned off and the diode 8 is turned on and the second capacitor 9 is charged with a Va value in a section (section I) in which the voltage Va is smaller than the ground voltage (0 V). As shown in FIG. 4C, the same voltage as Va in FIG. 4B is shown, which is supplied to the P-well 11.

Next, in the period (section II) in which the voltage Va is greater than the ground voltage (0 V), the MOS transistor 7 is turned on and the diode 8 is turned off so that the first capacitor 6 and the second capacitor 9 are turned off. Are connected in series, the voltage across the second capacitor 9 is added to the voltage across the first capacitor 6, resulting in the voltage Vp as shown in section II of FIG. 4C, and this voltage is the P-well 11. Is supplied.

That is, the potential of the P-well 11 corresponds to the protection voltage Vp which appears as a DC component gradually changing as shown in FIG. 4C by the second capacitor 9 repeatedly charging and discharging due to the leakage current according to the change of the Vclock voltage. Generate.

As a result, a substantially constant protection voltage Vp, such as a low level level of the Vclock signal passing through the first capacitor, is applied to the P-well 11 to apply the protection voltage Vp to the P-well 11 separately from the outside. There is no need to do it.

As described above, the CCD protection circuit according to the present invention has the following effects.

Through an external pin, the potential of the P-well region can be maintained at the low level of Vclock without applying a protection voltage.

Claims (2)

A first capacitor having one end connected to a clock signal terminal; A diode having a cathode terminal connected to the other end of the first capacitor; A MOS transistor having a gate and one end connected to the cathode terminal of the diode in common and the other end connected to a ground terminal; And a second capacitor connected between the anode terminal and the ground terminal of the diode. The method of claim 1, And the MOS transistor is turned on when a positive voltage is applied to a gate terminal, and is turned off when a negative voltage is applied.