KR20020015889A - Circuit for setting system information - Google Patents

Abstract

PURPOSE: A circuit for setting system information is provided to automatically set system information to a north bridge controller. CONSTITUTION: A register(110) stores system information data. Multiplexers(112-118) respond to selection signals and successively output the system information data stored in the register(110) to an FID(Frequency Identification) bus. A programmable logic device(120) outputs the selection signals and provides the system information data inputted from the multiplexers(112-118) through the FID to a north bridge controller(200) through a TIG(TTL Integrated Glue logic) bus.

Description

System information setting circuit {CIRCUIT FOR SETTING SYSTEM INFORMATION}

The present invention relates to a system information setting circuit of a system having an alpha CPU (ALPHA Central Processing Unit), and more specifically, to automatically north of system information such as CPU type, operation speed, cache memory type, size, etc. A system information setting circuit for setting in a bridge controller (north bridge controller).

1 is a block diagram showing a conventional system information setting circuit.

Referring to FIG. 1, a conventional system information setting circuit 10 includes first and second switch arrays 12 and 14 and first and second buffers 16 and 18. Each of the first and second switch arrays 12, 14 is comprised of eight dual in-line package (DIP) switches, for example. In addition, the first and second switch arrays may be configured with jumpers. The switches configured in the first and second switch arrays 12 and 14 set system information such as a type of a central processing unit (CPU), an operation speed, a type of a cache memory, an operation speed, a size, and the like. Used.

Data set in the first and second switch arrays 12 and 14 is stored in a register of the north bridge controller 20 through the first and second buffers 16 and 18 and the TIG bus.

The north bridge controller 20 controls data and address transfer between the alpha CPU 30 and a PCI bus (not shown). System information stored in a register of the north bridge controller 20. The data is passed to the basic input / output system (BIOS) and used for system configuration.

In the conventional system information setting circuit as described above, when the CPU or the cache memory is replaced with a new one, the user must reconfigure the switch according to the changed contents. This is very inconvenient. Moreover, if the user does not set the dip switch on / off correctly, the whole system may malfunction or not operate at all.

Accordingly, an object of the present invention is to provide a system information setting circuit for automatically setting system information to a north bridge controller, which has been proposed to solve the above-mentioned problems.

1 is a block diagram showing a conventional system information setting circuit;

2 is a block diagram showing a system information data setting circuit according to a preferred embodiment of the present invention; And

FIG. 3 is a timing diagram illustrating an operation of the system information setting circuit shown in FIG. 2.

* Description of the symbols for the main parts of the drawings *

100: system information setting circuit 110: register

112-118: Multiplexer 120: Programmable Logic Device

200: North Bridge Controller 300: Alpha CPU

According to a feature of the present invention for achieving the object of the present invention as described above, a system information setting circuit for setting system information in a north bridge controller comprises: a register for storing system information data and in response to a selection signal, Output means for sequentially outputting system information data stored in the register to a first data bus, and outputting the selection signal, and inputting system information data input from an output means through the first data bus via a second data bus; And a programmable logic device providing the north bridge controller.

In a preferred embodiment, the system information data stored in the register includes a type of processor, a clock speed, and a type, size, and operation speed of a cache memory included in the system.

At this time, the output means sequentially outputs the system information data stored in the register for each type in response to the selection signal.

In a preferred embodiment, the first data bus is a frequency identification bus (FID) bus and the second data bus is a TTL integrated glue logic (TIG) bus.

(Action)

Such a device can implement a system information setting circuit for automatically setting the information of the alpha CPU and the cache memory to the north bridge controller.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 2 to 3.

2 is a block diagram showing a system information data setting circuit according to a preferred embodiment of the present invention.

Referring to FIG. 2, the system information setting circuit 100 stores a system 110 that stores system information data and a system stored in the register 112 in response to selection signals FID_SEL [1: 0]. Multiplexers 112-118 for sequentially outputting information data to a frequency identification (FID) bus, and the selection signals FID_SEL [1: 0], and output the multiplexers 112-112 through the FID bus. A programmable logic device 120 for providing system information data input from 118 to the north bridge controller 200 via a TTL integrated glue logic (TIG) bus.

The register 110 stores a speed and a type of an alpha central processing unit 300, a speed, a size, and a type of a cache memory (not shown). In this embodiment, the speed and type of the alpha CPU 300 and the speed of the cache memory are 4-bit data (CPU_INF [3: 0], CPU_INF [7: 4], CACHE_INF [0: 3]). The size and type of the cache memory are stored in the register 110 as 2-bit data CACHE_INF [4: 5] and CACHE_INF [6: 7], respectively.

The multiplexers 112-118 sequentially output system information data stored in the register 110 in response to the selection signals FID_SEL [1: 0] provided from the programmable logic device 120. Table 1 shows data FID_DATA [3: 0] output from the multiplexers 112, 114, 116, and 188 according to the state of the selection signals FID_SEL [1: 0]. have.

TABLE 1

The programmable logic device 120 outputs system information data FID_DATA [3: 0] input through the FID bus to the TIG bus (CPU_INFO and CACHE_INFO). The north bridge controller 200 stores CPU information data (CPU_INFO) and cache memory information data (CACHE_INFO) input through the TIG bus in a built-in register. Data stored in a register in the north bridge controller 200 is transmitted to the alpha CPU 300, stored in the register 30, and transferred to a basic input / output system (BIOS) for use in system configuration.

FIG. 3 is a timing diagram illustrating an operation of the system information setting circuit shown in FIG. 2.

As shown in FIG. 3, when the selection signals FID_SEL [1: 0] are generated, the system information data stored in the register 110 is input to the programmable logic device 120 through the FID bus, thereby providing CPU information data ( CPU_INFO and cache memory information data CACHE_INFO are converted and automatically input to the north bridge controller 200 via the TIG bus.

According to the system information setting circuit as described above, the system information is automatically set so that the user does not need to manually set the system information to the jumper or the switch.

While the invention has been described using exemplary preferred embodiments, it will be understood that the scope of the invention is not limited to the disclosed embodiments. Rather, the scope of the present invention is intended to include all of the various modifications and similar configurations. Accordingly, the claims should be construed as broadly as possible to encompass all such modifications and similar constructions.

According to the present invention as described above, information of the alpha CPU and the cache memory is automatically set in the north bridge controller. Therefore, the user does not need to manually set the system information on the jumper or the switch, which is very convenient and can prevent the system from malfunctioning.

Claims (5)

In the system information setting circuit for setting system information to the north bridge controller: A register for storing system information data; Output means for sequentially outputting system information data stored in the register to a first data bus in response to selection signals; And a programmable logic device for outputting said selection signals and for providing system information data input from an output means via said first data bus to said north bridge controller via a second data bus. . The method of claim 1, The system information data stored in the register is And a type, a size, and an operating speed of a processor, a clock speed, and a cache memory included in the system. The method of claim 2, The output means, And a multiplexer for sequentially outputting the system information data stored in the register for each type in response to the selection signal. The method of claim 1, And the first data bus is a frequency identification (FID) bus. The method of claim 1, And the second data bus is a TTL integrated glue logic (TIG) bus.