KR20020014643A - Ball grid array package for providing constant internal voltage via PCB substrate wring - Google Patents

Abstract

PURPOSE: A ball grid array package is provided to achieve a high integrated chip without increasing the size of the chip, by supplying constant power to the chip through the wire of the substrate. CONSTITUTION: A ball grid array package comprises a substrate(40) having an aperture(49); a plurality of pads attached at the upper surface of the substrate; a semiconductor chip(30) attached at the lower surface of the substrate, and which includes a plurality of bonding pads(35); and a connection member(41) for interconnecting at least one bonding pad and at least one pad attached at the upper surface of the substrate, through the aperture formed at the substrate. The bonding pad is electrically connected to the other bonding pad through wires(43,45) of the substrate.

Description

Ball grid array package provides constant internal voltage via PCB wiring to provide constant internal voltage via PCB substrate wring

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chip scale ball grid array (BGA) package, in particular a substrate of a printed circuit board (PCB) on a BGA package. The present invention relates to a BGA package in which an auxiliary wiring is formed on a substrate to supply a constant power to a chip.

As the degree of integration of semiconductor integrated circuit devices increases, the number of input / output pins increases, thereby miniaturizing semiconductor devices. One of the semiconductor packages developed according to these requirements is the BGA package.

Compared to the plastic package using the lead frame, the BGA package can significantly reduce the mounting area when the BGA package is mounted on the main board, and has excellent electrical characteristics.

The difference between the plastic package and the BGA package is that the electrical connection between the semiconductor chip and the main substrate is made of a circuit board formed by external connection terminals such as circuit wiring and solder balls instead of the lead frame.

Since the external connection terminals can be freely formed on the opposite side of the circuit board to which the semiconductor chip is attached, the mounting area is much smaller than that of the plastic package.

1 shows a conventional wiring method of a power line inside a chip. Referring to FIG. 1, the semiconductor chip 10 includes an internal power supply line 16, a bonding pad 15, and banks 11, 12, 13, and 14 as a memory chip. The internal power supply line 16 has a voltage in each of the banks 11, 12, 13, and 14, that is, a back bias voltage such as a word line driving voltage Vpp, a bit line driving voltage Vbl, and a substrate. Supply (Vbb).

In the trend of higher integration of semiconductor devices, transistors entering memory cells or peripheral circuits become smaller, while the current consumed by each transistor does not decrease, so the power width of the line supplying the voltage increases relatively. do.

That is, the voltage Vpp driving the word line (hereinafter, referred to as 'Vpp') may vary depending on the position of the enabled word line, and the dip of the voltage Vpp driving the word line. ) Is not the same in all parts of the chip, conventionally, the resistance (R) is reduced by increasing the power width of the line supplying the Vpp voltage to eliminate the Vpp level difference. However, when the width of the line for supplying the voltage increases, the size of the chip also increases, thereby increasing the production cost.

On the other hand, the smaller the power width of the line supplying the voltage, the smaller the chip size, but the chip operation due to the different power levels of the internal power sources in the areas A / B and C / D. There is a problem that adversely affects.

2 is a plan view of a conventional ball grid array package. Referring to FIG. 2, the BGA package includes a semiconductor chip 10 having a plurality of bonding pads 15 arranged therein, an opening 29 and a bonding pad 15 formed to expose the bonding pads 15 to the outside. The substrate 20 includes a lower surface adhered to the semiconductor chip 10 and a plurality of substrate pads 22.

In the BGA package, a problem that adversely affects chip operation due to a change in the power level of the area A / B and the area C / D due to a decrease in the power width of the line supplying the voltage There was a problem that could not be compensated.

Therefore, a technical problem to be achieved by the present invention is to provide a BGA package that constantly supplies auxiliary power to the chip by forming auxiliary wirings on the PCB substrate on the BGA package.

In order to more fully understand the drawings used in the detailed description of the invention, a brief description of each drawing is provided.

1 shows a conventional wiring method of a power line inside a chip.

2 is a plan view of a conventional ball grid array package.

3 is a view illustrating a wiring method of an internal power supply inside a chip according to an embodiment of the present invention.

4 is a plan view of a ball grid array package according to an embodiment of the present invention.

5 illustrates the connection relationship between the internal power supply inside the chip and the wiring of the substrate.

In order to achieve the above technical problem, a substrate having an opening, a plurality of pads attached to an upper surface of the substrate, a semiconductor chip adhered to a lower surface of the substrate, and having a plurality of bonding pads, and the bonding pad through the opening. Connection means for connecting at least one of the bonding pads and at least one of the pads, wherein at least one of the bonding pads is connected to at least another one of the bonding pads through wiring of the substrate. Provided is a BGA package, which is electrically connected to the bonding pads. The BGA package may further include a filler filled in the opening to protect the bonding pads and the connection means.

Preferably, the at least one bonding pad and the at least one other bonding pad have an IVC (or Vpp, Vbb, Vbl) pad.

The connecting means between the bonding pads may use wire bonding or beam lead, and solder balls are not connected to the connecting means.

In order to achieve the above technical problem, the BGA package includes an internal wiring inside a chip which commonly connects a bonding pad and internal power supplies of the chip, and a substrate wiring of a substrate connected to the bonding pad. It is characterized by greater than the resistance of the substrate wiring.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings which illustrate preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. For each figure, like reference numerals denote like elements.

In general, as the memory becomes larger and more integrated, the internal voltage converter supplies a constant voltage regardless of the external power source to satisfy the AC power supply and DC power supply parameters without degrading chip characteristics in the reliability and wide voltage range of the product. internal voltage converter (hereinafter referred to as 'IVC') is used.

In a memory device having an IVC, characteristics such as a decrease in operating speed and a decrease in low voltage margin may occur due to a decrease in an internal operating voltage generated by current consumption due to the operation of the memory device in a low voltage region.

The BGA package according to the present invention has an internal power source made from an external power source supplied from the outside of the semiconductor device through the auxiliary wirings 43 and 45, that is, the voltage IVC and the word line driving voltage Vpp by IVC. ), The bit line driving voltage Vbl, and the back bias voltage Vbb of the substrate and the like are kept constant.

3 shows a wiring method of an internal power supply of the semiconductor memory chip 30 according to an embodiment of the present invention. Referring to FIG. 3, the semiconductor chip 30 is a memory chip, and includes a plurality of banks 31, 32, 33, and 34, and an internal power supply IVC for each of the banks 31, 32, 33, and 34. , A line (36A and 36B) and bonding pads (35, 37A, 37B, 39A and 39B) having a constant width to supply Vpp, Vbl or Vbb.

Referring to FIG. 3, the line 36A for supplying the internal power supply (IVC, Vpp, Vbl or Vbb) to bank 32 and the line 36A for supplying the internal power supply (IVC, Vpp, Vbl or Vbb) to bank 31 are Although connected to each other, the line 36A for supplying the internal power supply (IVC, Vpp, Vbl or Vbb) to the bank 32 and the line 36A for supplying the internal power supply (IVC, Vpp, Vbl or Vbb) to the bank 32 are mutually It may be separated.

In addition, the line 36B for supplying the internal power supply (IVC, Vpp, Vbl or Vbb) to the bank 33 and the line 36B for supplying the internal power supply (IVC, Vpp, Vbl or Vbb) to the bank 34 are connected to each other. In addition, the line 36B for supplying the internal power supply (IVC, Vpp, Vbl or Vbb) to the bank 33 and the line 36B for supplying the internal power supply (IVC, Vpp, Vbl or Vbb) to the bank 34 may be separated from each other. .

In addition, all of the banks 31, 32, 33, and 34 may be supplied with internal power through one line 36A or 36B.

Each of the banks 31, 32, 33, and 34 includes memory cells for storing data and peripheral circuits (not shown) for inputting and outputting data of the memory cells.

The line 36A or 36B supplies internal power supplies (IVC, Vpp, Vbl, Vbb, etc.) required to drive the respective banks 31, 32, 33 and 34. The bonding pads 35, 37A, 37B, 39A, and 39B are generally arranged in a line at the center portion of the semiconductor chip 10, and the bonding pads 35, 37A, 37B, 39A, and 39B are the semiconductor. It is a means for inputting / outputting an internal power supply or a predetermined signal to the chip 10.

Bonding pads 37A, 37B, 39A and 39B according to an embodiment of the present invention are connected to a predetermined portion of the line 36A or 36B. Bonding pads 37A and 37B are for supplying internal power (IVC, Vpp, Vbl, Vbb, etc.) to banks 32 and 31, and bonding pads 39A and 39B are for supplying internal power to banks 33 and 34. It is to.

Although the case where the line 36A or 36B is an internal power supply line has been described, the line 36A or 36B may be a signal line for transmitting a predetermined signal. Each of the bonding pads 37A and 39A is in electrical contact with the bonding pads 37B and 39B by a BGA package described below.

4 is a plan view of a ball grid array package according to an embodiment of the present invention. Referring to FIG. 4, FIG. 4 shows a substrate 40 having a semiconductor chip size having an opening 49 coupled to the semiconductor chip 30 of FIG. 3.

The semiconductor chip 30 is adhered to the lower surface of the substrate 40 by non-conductive adhesive means such as an adhesive or an adhesive tape.

The plurality of bonding pads 35 (hereinafter referred to as 'first group bonding pads') on the semiconductor chip 30 are mounted on the upper surface of the substrate 40 through the openings 49 of the substrate 40. The pads 42 are electrically connected through the connecting means 41. The connecting means 41 may be wire bonding or beam lead.

The plurality of pads 42 have an external connection terminal (not shown) to be electrically and mechanically connected to an external device (not shown). The external connection terminal may be a solder ball and other conventional external connection terminals. Can be used.

The other bonding pads 37A, 37B, 39A, and 39B (hereinafter referred to as 'second group bonding pads') on the semiconductor chip 30 are electrically connected to each other through the wirings 43 and 45 of the substrate, but are externally connected. There is no terminal. The wires 43 and 45 of the substrate may use wire bonding or beam leads.

In addition, the opening 49 is filled with a non-conductive material to protect the bonding pads 35, 37A, 37B, 39A, 39B and the connecting means 41, or the wiring 43, 45 of the substrate from the external environment. May be encapsulation.

In particular, in the BGA package according to the present invention, 37A of the bonding pad and another bonding pad 37B are electrically connected to each other through the wiring 45 of the substrate 40. The substrate of the BGA package may be a single substrate or a multilayer substrate. 4 illustrates a single substrate for convenience of description.

In addition, the bonding pads 39A and the other bonding pads 39B are electrically connected to each other through the wiring 43 of the substrate 40.

The first group bonding pads 35 are connected to the solder balls in the BGA package step, and the second group bonding pads 37A and 37B or 39A and 39B are connected to the auxiliary wirings 43 and 45 of the substrate in the BGA step. do.

Therefore, since the internal power sources (IVC, Vpp, Vbl, and Vbb) can be simultaneously input through the second group bonding pads 37A and 37B or 39A and 39B, the peripheral device that consumes power in the semiconductor chip 30 is used. The influence of the dip of the internal power source on the position is considerably reduced. Thus, the second group bonding pads are IVC pads, Vpp pads, Vbb pads and Vbl pads.

5 illustrates in detail the connection relationship between the internal power supply inside the chip and the wiring of the substrate according to the present invention. Hereinafter, for convenience of description, Vpp is described as an example among internal power sources (IVC, Vpp, Vbl, Vbb, etc.).

Referring to FIG. 5, assuming that there is one Vpp generator for each bank 31, 32, 33, and 34, the level of each Vpp has various factors for each bank 31, 32, 33, and 34. Depends).

Internal wiring Rint is connected between the Vpp generators 501, 503, 505, and 507 in the chip to eliminate the level difference between the Vpps of the respective banks. Since the width of the internal wiring Rint cannot grow sufficiently due to the chip area, the resistance of the internal wiring Rint is large.

Due to the large resistance, it takes a long time for the voltage Vpp level generated in the Vpp generators 501, 503, 505, and 507 to remain constant. Therefore, in the BGA package according to an embodiment of the present invention, auxiliary wirings Raux, 43 and 45 may be formed on the substrate 40 of the BGA package to maintain the Vpp voltage level within a short time when a voltage difference occurs.

In this case, the resistance of the internal wiring Rint between the Vpp generators 501, 503, 505, and 507 is preferably larger than the resistance of the auxiliary wirings Raux, 43, 45.

Therefore, the internal power sources (IVC, Vpp, VBl. Vbb, etc.) can be made constant through the bonding pads 37A, 37B, 39A, 39B and the auxiliary wirings 43, 45.

Since the BGA package according to the present invention can reduce the width of the power line 36A or 36B, it is possible to stably maintain the level of the power supply voltage in the semiconductor chip without increasing the size of the semiconductor chip. Therefore, the reduction of the semiconductor chip size increases the number of net dies per wafer, thereby reducing the production cost of the semiconductor chip.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

According to the BGA package according to the present invention, the internal power supply of the chip is constantly supplied through the auxiliary wiring of the substrate, thereby increasing the size of the chip and increasing the chip density and speed.

Claims (16)

A substrate having an opening; A plurality of pads attached to an upper surface of the substrate; A semiconductor chip bonded to a lower surface of the substrate and having a plurality of bonding pads; Connection means for connecting at least one of the bonding pads and at least one of the pads through the opening; At least one bonding pad of the bonding pads is electrically connected to at least another bonding pad of the bonding pads through wires of the substrate. The BGA package of claim 1, wherein the at least one bonding pad and the at least one other bonding pad are IVC pads. The BGA package of claim 1, wherein the at least one bonding pad and the at least one other bonding pad are Vpp pads. The BGA package of claim 1, wherein the at least one bonding pad and the at least one other bonding pad are Vbb pads. The BGA package of claim 1, wherein the at least one bonding pad and the at least one other bonding pad are Vbl pads. The BGA package according to claim 1, wherein said connecting means is wire bonding or beam lead. The method of claim 1, wherein the plurality of bonding pads, A first group having a plurality of bonding pads; A second group having a plurality of bonding pads, And the first group is connected to the solder balls in the BGA package, and the second group is connected to the wiring of the substrate of the BGA package. 8. The BGA package according to claim 7, wherein the second group of bonding pads is an IVC pad. 8. The BGA package according to claim 7, wherein the second group of bonding pads are Vpp pads. 8. The BGA package of claim 7, wherein the second group of bonding pads are Vbb pads. 8. The BGA package according to claim 7, wherein the second pad bonding pad is a Vbl pad. In the BGA package, Internal wiring inside the chip to connect the bonding pads and the internal power sources of the chip in common; And A substrate wiring of a substrate connected with the bonding pads, The BGA package, characterized in that the resistance of the internal wiring is greater than the resistance of the substrate wiring. 13. The BGA package according to claim 12, wherein the internal power supplies are IVC power supplies. 13. The BGA package according to claim 12, wherein the internal power supplies are Vpp power supplies. 13. The BGA package according to claim 12, wherein the internal power supplies are Vbl power supplies. 13. The BGA package according to claim 12, wherein the internal power sources are Vbb power sources.