KR20020010801A - Parallel test circuit - Google Patents

Abstract

PURPOSE: A parallel test circuit is provided, which reduces the number of IO(Input/Output) pins into a half by transferring two data reduction results to one IO pin. CONSTITUTION: The parallel test circuit includes a plurality of array blocks(1,2,3,4) storing data, and comparators(5-8) comparing data applied from the plurality of array blocks and then outputting them. A control part(10) decodes a data signal applied from the comparator and then outputs the decoded data signal. And an IO(Input/Output) driving part(20) outputs one test signal having a plurality of levels according to a control signal applied from the control part. The parallel test circuit judges pass or fail of the plurality of array blocks by the plurality of levels.

Description

Parallel test circuit

The present invention relates to a parallel test circuit, and in particular, to parallelize the reduced number of IO pins required for the test by transferring the abbreviated data output from two independent array blocks to one IO output stage during parallel test. Relates to a test circuit.

Generally, a test device is installed inside most DRAM devices in order to reduce test time. In such a semiconductor memory, a memory chip is produced to cover a cell's pass or fail. Test cell by cell.

The conventional test mode will be described with reference to FIG. 1. In the normal operation, data read / write from the selected array blocks 1 to 4 is performed. Therefore, as shown in the switch open / closed state of FIG. 1, four data output from one selected array block 1 are transferred to four output stages 9.

However, this conventional test mode not only takes a long test time but also leads to an increase in test cost. Therefore, the parallel test mode was used to reduce the test time.

The parallel test mode described above will be described with reference to FIG. 2.

Referring to FIG. 2, the conventional parallel test mode simplifies control logic by comparing and outputting data output from each array block 1 to 4 through exclusive NOR gates 5 to 8. That is, after the same data is written to a plurality of cells, when the same data is read using an exclusive NOR logic circuit during reading, a signal of "1" is output through the IO output terminal 9. As a result, a good judgment can be made. In addition, when any other data is read, a bad process is performed by outputting a signal of "0" through the IO output terminal 9.

Looking at the operation process, in parallel test mode, all array blocks (1 ~ 4) are enabled in order to shorten the test time at the time of writing, and write data of "1" through IO pin at the same time. Then, the data output from the array blocks 1 to 4 are compared and output to the exclusive NO-gates 5 to 8 in the read operation. At this time, if the data are the same, the high level is output through the IO output stage 9, and if a failure occurs in the array blocks 1 to 4 and any other data comes out, the low level is output through the IO output stage 9. Output to determine pass or fail.

However, when the parallel test mode is applied to a memory product, the number of array blocks increases as the total memory is subdivided to reduce the signal line load that increases as the density increases, thus increasing the number of IO pins required in the parallel test mode. There is this.

The present invention has been made to solve the above problems, and in contrast to allocating one IO pin per data reduction output result to reduce the number of IO pins used in parallel test mode, two data reduction results are generated. The purpose is to provide a parallel test circuit that allows the number of IO pins to be cut in half by transferring them to IO pins.

1 is a configuration diagram related to a conventional test circuit,

2 is a configuration diagram relating to another conventional test circuit;

3 is a block diagram of a parallel test circuit according to the present invention;

4 is a circuit diagram of a control unit according to the present invention;

5 is a circuit diagram of an IO driver according to the present invention.

<Description of Symbols for Main Parts of Drawings>

1 ~ 4: Array Block 5 ~ 8: Exclusive Noah Gate

10: control unit 11, 12, 16, 17: inverter

13 ~ 15: NAND Gate 20: IO driver

21,22: NMOS transistor 23: PMOS transistor

30: IO output stage

The parallel test circuit of the present invention for achieving the above object, in the parallel test circuit, a plurality of array blocks for storing data, a comparator for comparing and outputting data applied from the plurality of array blocks, and is applied from the comparator A control unit for decoding a data signal and outputting a control signal, and an IO driver for outputting a test signal having a plurality of levels in accordance with a control signal applied from the control unit, the path / of the plurality of array blocks by a plurality of levels It is characterized by determining whether to fail.

Hereinafter, with reference to the accompanying drawings will be described in detail an embodiment of the present invention.

3 shows a block diagram of a parallel test circuit according to the present invention.

Referring to FIG. 3, the present invention provides an array of exclusive blocks No. 5 through 8 and an exclusive Noa gate 5 through 8 comparing the data output from each of the array blocks 1 through 4 with the array blocks 1 through 4. The control unit 10 receives the comparatively output data from the control unit 10 and outputs a control data signal, and the IO driving unit 20 outputs the IO driving data using the control data output from the control unit 10.

First, data read from the two array blocks 1 and 2 are applied to the exclusive NOR gates 5 and 6, respectively. The exclusive NOR gates 5 and 6 compare the input data and output a logic high level “1” signal when the data stored in the memory cells of the array blocks 1 and 2 are the same and the output data match. In addition, when the data stored in each of the memory cells of the array blocks 1 and 2 are different from each other and the output data do not match, the reduced data is applied to the controller 10 by outputting a logic low level “0” signal. Therefore, the device is recognized as a pass only when the signal of 'logic high' level is output as the final output signal, and processed as a fail when the signal of 'logic low' level is output.

4 shows a circuit diagram of a control unit according to the present invention.

Referring to FIG. 4, the control unit 10 inputs through each of the data input terminals IN1 and IN2 and the data input terminals IN1 and IN2 for receiving the comparatively output data from the exclusive NOR gates 5 and 6. And a first inverter 11 and a second inverter 11, 12 for inverting the 1 or 0 data. The first NAND gate 13 receives the data inverted from the first inverter 11 and the second data applied from the data input terminal IN2, and inverts the result of the logical AND operation. In addition, the fourth inverter 17 inverts the data output from the first NAND gate 13 and outputs a third control signal to the C input terminal of the IO driver 20.

The second NAND gate 13 receives the data inverted from the second inverter 12 and the first data applied from the data input terminal IN1 and outputs the result by performing an inverse AND operation. In addition, the third inverter 16 inverts the data output from the second NAND gate 13 to output one control signal to the A input terminal of the IO driver 20.

In addition, the third NAND gate 13 receives the first data and the second data applied from the data input terminals IN1 and IN2 and performs an inverse AND operation on the second data to the B input terminal of the IO driver 20. Output the signal.

5 is a circuit diagram of an IO driver according to the present invention.

Referring to FIG. 5, the IO driver 20 has A, B, and C input terminals for receiving control data from the controller 10, an input terminal A and a gate terminal, and a power supply voltage Vcc through the drain terminal thereof. The source terminal is connected to the first NMOS transistor 21 for pull-up connected to the IO output terminal (IO), the input terminal B and the gate terminal are connected, and receives the power supply voltage (VCC) through the source terminal. The PMOS transistor 23 connected to the IO output terminal IO and the drain terminal of the second NMOS transistor 22, the input terminal C and the gate terminal are connected, the source terminal thereof is connected to the ground terminal VSS, and the PMOS transistor 23 ) And a second NMOS transistor 22 for pull-down in which a drain terminal thereof is commonly connected.

On the other hand, the control logic of the control unit 10 for receiving data from the exclusive Noah gates 5 to 8 and outputting control data to the A, B and C terminals of the IO driver 20 is as follows.

TABLE 1

IN1 IN2 A B C IO # One One 0 0 0 VCC One 0 One One 0 VCC-Vth 0 One 0 One One VSS 0 0 0 One 0 Hi-Z

As shown in Table 1, output data &quot; 1 &quot; of the first array block 1 and output data " 1 " of the second array block 2 are connected through the data input terminals IN1 and IN2 of the controller 10. When input, the controller 10 outputs data of 0, 0, 0 to the input terminals A, B, and C of the IO driver 20, respectively. In this case, the IO driver 20 outputs the VCC level to the IO output terminal 30. Therefore, when the VCC level is detected at the IO output terminal 30, since the data of 1 and 1 are output from the first array block 1 and the second array block 2, it is determined that both blocks are paths. .

When the output data "1" of the first array block 1 and the output data "0" of the second array block 2 are input through the data input terminals IN1 and IN2 of the control unit 10, the control unit ( 10) outputs data of 1, 1, 0 to the input terminals A, B, and C of the IO driver 20, respectively. In this case, the IO driver 20 outputs the VCC-Vth level to the IO output terminal 30. Accordingly, when the VCC-Vth level is detected by the IO output terminal 30, 1,0 data are output from the first array block 1 and the second array block 2, so that the first array block 1 It is this pass and it is determined that the second array block 2 is a failure.

Further, when the output data "0" of the first array block 1 and the output data "1" of the second array block 2 are input through the data input terminals IN1 and IN2 of the control unit 10, the control unit ( 10) outputs data of 0, 1, 1 to the input terminals A, B, and C of the IO driver 20, respectively. In this case, the IO driver 20 outputs the VSS level to the IO output terminal 30. Therefore, when the VSS level is detected at the IO output terminal 30, since the data of 0 and 1 are output from the first array block 1 and the second array block 2, the first array block 1 is failed. Then, it is determined that the second array block 2 is a pass.

Finally, when the output data "0" of the first array block 1 and the output data "0" of the second array block 2 are input through the data input terminals IN1 and IN2 of the control unit 10, the control unit 10 outputs data of 0, 1, 0 to the input terminals A, B, and C of the IO driver 20, respectively. In this case, the IO driver 20 outputs the Hi-Z level to the IO output terminal 30. Therefore, when the Hi-Z level is detected at the IO output terminal 30, since 0, 0 data is output from the first array block 1 and the second array block 2, it is determined that both blocks are failing. Done.

As described above, the operation of the parallel test circuit of the present invention will be described.

First, if all data output from the first array block 1 match, the first exclusive NOR gate 5 outputs the path 1 signal to the controller 10. If any of the data output from the second array block 2 does not match, the second exclusive NOR gate 6 outputs a fail 0 signal to the controller 10. At this time, the controller 10 receives a signal of 1,0 through the data input terminal IN1.IN2, respectively.

The signal of 1 input through the first data input terminal IN1 is input to the first inverter 11 and inverted. The inverted data is input to the first NAND gate 15, and the first NAND gate 15 inverts the data inverted from the first inverter 11 and the second data input from the second input terminal IN2. The result is a logical AND operation. In addition, the data output from the first NAND gate 15 is applied to the fourth inverter 17 and inverted again to output a signal of "0" to the C input terminal of the IO driver 20.

The zero signal input through the second data input terminal IN2 is input to the second inverter 12 and inverted. The inverted data is input to the second NAND gate 13, and the second NAND gate 13 inverts the data inverted from the second inverter 12 and the first data input from the first input terminal IN1. The result is a logical AND operation. In addition, the data output from the second NAND gate 13 is applied to the third inverter 16 and inverted again to output a signal of "1" to the A input terminal of the IO driver 20.

In addition, the third NAND gate 14 receives a signal of 1,0 applied from the first and second data input terminals IN1 and IN2 and performs an inverse AND operation on the B input terminal of the IO driver 20 to perform " 1 " Signal will be output.

Meanwhile, the A, B, and C terminals of the IO driver 20 receive signals of 1, 1, 0 through the output terminal of the controller 10. At this time, the first NMOS transistor 21 is turned on by receiving a "1" signal through the A terminal connected to the gate terminal thereof. The PMOS transistor 23 is turned off by receiving a '1' signal through the B terminal connected to the gate terminal. In addition, the second NMOS transistor 22 is turned off by receiving a '0' signal through the C terminal connected to the gate terminal. Accordingly, the VCC voltage is applied through the first NMOS transistor 21 to pass through the Vth (threshold voltage) drop, and as a result, the VCC-Vth level is transferred to the IO output terminal IO. As a result, when the VCC-Vth level is detected at the IO output terminal 30, it can be inferred that 1,0 data is applied to the data input terminals IN1 and IN2, so that the second array block 2 is determined to be a failure. You can do it.

When the data input terminal IN1.IN2 of the controller 10 receives the signals 1,1 from the exclusive Noah gates 5 and 6 through the above-described operation process, the controller 10 is an IO driver ( Outputs 0, 0, 0 signals to terminals A, B, and C of 20), respectively. Therefore, the IO driver 20 transmits the VCC level to the IO output terminal IO. As a result, when the VCC level is detected at the IO output terminal 30, it can be inferred that 1,1 data is applied to the data input terminals IN1 and IN2. Therefore, the first array block 1 and the second array block 2 are inferred. ) It is possible to determine that all passes.

In addition, when the data input terminal IN1.IN2 of the control unit 10 receives the 0,1 signal from the exclusive Noah gates 5 and 6 through the above-described operation process, the control unit 10 is the IO driver 20. 0, 1, 1 signals are output to the A, B, and C terminals. Therefore, the IO driver 20 transmits the VSS level to the IO output terminal IO. As a result, when the VSS level is detected at the IO output terminal 30, it can be inferred that 0, 1 data is applied to the data input terminals IN1 and IN2, so that the first array block 1 can be determined to be a fail. Will be.

Finally, when the data input terminal IN1.IN2 of the control unit 10 receives a signal of 0,0 from the exclusive Noah gates 5 and 6 through the above-described operation process, the control unit 10 generates an IO driver ( The signals 0, 1, and 0 are output to terminals A, B, and C of 20), respectively. Therefore, the IO driver 20 transmits the Hi-Z (high impedance) level to the IO output terminal IO. As a result, when the Hi-Z level is detected at the IO output terminal 30, it can be inferred that 0, 0 data is applied to the data input terminals IN1 and IN2. Thus, the first array block 1 and the second array block are inferred. It is possible to judge that (2) is all a failure.

As described above, the parallel test circuit according to the present invention can reduce the number of IO pins used in parallel test by half, and in particular, the higher the memory density, the greater the effect of reducing the test cost.

Claims (3)

In a parallel test circuit, A plurality of array blocks for storing data; A comparator for comparing and outputting data applied from the plurality of array blocks; A controller for decoding a data signal applied from the comparator and outputting a control signal; And Including an IO driver for outputting a test signal having a plurality of levels in accordance with the control signal applied from the controller, And determining whether the plurality of array blocks pass / fail based on the plurality of levels. The method of claim 1, wherein the control unit A first inverter receiving the first data signal applied from the comparator and inversely converting the first data signal; A first NAND gate receiving an inversely transformed signal from the first inverter, receiving a second data signal applied from the comparator, and performing inverse AND operation on the two data; A fourth inverter configured to receive a signal output from the first NAND gate and inversely convert the signal to output a third control signal; A second inverter which receives a second data signal applied from the comparator and inversely converts it; A second NAND gate receiving an inversely converted signal from the second inverter, receiving a first data signal applied from the comparator, and performing inverse AND operation on the two data; A third inverter receiving the signal output from the second NAND gate and performing inverse conversion to output a first control signal; And And a third NAND gate configured to receive the first data and the second data applied from the comparator and perform an inverse AND operation and output a second control signal. The method of claim 2, wherein the IO driver A first NMOS transistor for receiving a first control signal applied from the third inverter as a gate terminal, a drain terminal thereof being connected to a power supply voltage, and a source terminal thereof being connected to an IO output terminal; A PMOS transistor receiving a second control signal applied from the third NAND gate as a gate terminal, a source terminal thereof being connected to a power supply voltage, and a drain terminal thereof being connected to an IO output terminal; And A third control signal applied from the fourth inverter as a gate terminal, a source terminal of which is connected to a ground voltage, and a drain terminal of which has a second NMOS transistor connected to an IO output terminal; Test circuit.