KR20020005874A - data output driver of a semiconductor memory device - Google Patents

Abstract

PURPOSE: A data output driver of a semiconductor memory device is provided, which can compensate for a voltage drop due to a leakage component generated at a gate of a pull-up transistor of the data output driver. CONSTITUTION: A node(a) is precharged to a voltage(IVC-Vt) by subtracting a threshold voltage(Vt) of an NMOS transistor(N1) from an internal power supply voltage(IVC). If data(DB) of low level is inputted, output data(DQ) of low level are generated. If data of high level is inputted, an inverter(I1) generates a low level signal, and an inverter(I2) generates a high level signal. Thus, an NMOS transistor(N2) is turned off and a PMOS transistor(P1) is turned on, and a voltage of the node(a) is pumped to a voltage(2IVC-Vt) by a pumping operation of a capacitor(C1). Thus, the voltage of the node(a) is transferred to a node(b). Under the state that a node(c) is precharged to a voltage(V(d)-Vt), if an oscillation voltage(OSC) is transitted from a high level to a low level, an output signal of a NAND gate(NA1) becomes a high level and thus the node(c) has a voltage(V(d)+IVC-Vt). Thus, a voltage(V(d)+IVC-2Vt) is transmitted to the node(d).

Description

Data output driver of a semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data output driver of a semiconductor memory device, and more particularly, to a data output of a semiconductor memory device capable of preventing the level drop of "high" level output data by eliminating the drop of the gate voltage of the pull-up transistor of the data output driver. It's about the driver.

The data output driver of a conventional semiconductor memory device includes a pull-up NMOS transistor and a pull-down NMOS transistor connected in series between an external power supply voltage and a ground voltage. Since a NMOS transistor is used as a pull-up transistor, a level compensation circuit is used to compensate the gate voltage of the NMOS transistor.

The level compensation circuit of the data output driver of the conventional semiconductor memory device compensates that the gate voltage of the pull-up NMOS transistor is lowered by the leakage component by using an internal power supply voltage.

The level compensation circuit of the data output driver of the conventional semiconductor memory device has no problem even if the level is compensated using the internal power supply voltage. However, as the level of the internal power supply voltage is lowered, the level of the gate voltage of the pull-up NMOS transistor of the data output driver cannot be sufficiently compensated.

That is, since the level compensation circuit is configured to compensate for the gate voltage level of the pull-up NMOS transistor of the data output driver by using a low internal power supply voltage, the leakage component generated at the gate of the pull-up NMOS transistor can not be sufficiently compensated. There was a problem that was missing.

An object of the present invention relates to a data output driver of a semiconductor memory device capable of compensating for a voltage drop caused by a leakage component generated at a gate of a pull-up transistor of a data output driver.

The data output driver of the semiconductor memory device of the present invention for achieving the above object comprises a first precharge means for precharging a first node, pumping the first node in response to data of a first state and First pumping means for outputting a precharged voltage of the node to a second node, reset means for resetting the second node in response to the data in a second state, connected to a high voltage and connected to a voltage of the second node Second precharge means for precharging the third node in response, pumping the third node in response to a combination of the voltage and the oscillation voltage of the second node and by the pumped voltage Second pumping means for pumping a voltage, a pull-up transistor for pulling up output data in response to the voltage of the second node, and the output data in response to the second state data It characterized in that it includes the pull-down transistor for pull-down.

1 is a circuit diagram of an embodiment of a level compensation circuit and a driver in a conventional semiconductor memory device.

FIG. 2 is a graph illustrating a change in voltage over time t of the node d and the output data DQ of the data output driver of the semiconductor memory device shown in FIG. 1.

Fig. 3 is a circuit diagram of an embodiment of a level compensation circuit and a driver in the semiconductor memory device of the present invention.

FIG. 4 is a graph showing a change in voltage over time t of the node d and the output data DQ of the data output driver of the semiconductor memory device shown in FIG. 3.

Hereinafter, a data output driver of a conventional semiconductor memory device will be described with reference to the accompanying drawings before describing the data output driver of the semiconductor memory device of the present invention.

Fig. 1 is a circuit diagram of a level compensation circuit and a driver of a conventional semiconductor memory device, and is composed of a first level compensation circuit 10, a second level compensation circuit 12, and a driver 14.

The first level compensation circuit 10 includes a pumping circuit 10-1 consisting of inverters I 1 and I 2 and a capacitor C 1, a precharge circuit 10-2 consisting of an NMOS transistor and a PMOS transistor P1, And a reset circuit 10-3 composed of an NMOS transistor N2. The second level compensation circuit 12 is a precharge circuit 12-2 including a pumping circuit 12-1 composed of a NAND gate NA1 and a capacitor C2 and NMOS transistors N3, N4, and N5. The driver 14 is composed of NMOS transistors N6 and N7.

The operation of the circuit shown in FIG. 1 will now be described.

The node a is precharged from the internal power supply voltage IVC to the voltage IVC-Vt minus the threshold voltage Vt of the NMOS transistor N1.

When the data DB of the "low" level is input, the inverter I1 generates a signal of the "high" level. Accordingly, the NMOS transistor N7 is turned on to generate the "low" level output data DQ. do. Inverter I2 generates a signal of the "low" level.

On the other hand, when the data DB of the "high" level is input, the inverter I1 generates a signal of "low" level, and the inverter I2 generates a signal of "high" level. Accordingly, the NMOS transistor N2 is turned off, the PMOS transistor P1 is turned on, and a pumping operation by the capacitor C1 is performed to pump the voltage of the node a to the voltage 2IVC-Vt. Thus, the voltage at node a is transferred to node b. That is, the voltage 2IVC-Vt is transmitted to the node b. The voltage of the node d is equal to the voltage of the node b, and thus, the NMOS transistor N3 is turned on and the voltage IVC-Vt is transmitted to the node c. Since the voltage 2IVC-Vt applied to the gate of the NMOS transistor N3 is larger than the internal power supply voltage IVC, the voltage drop by the NMOS transistor N3 does not occur.

When the node c is precharged with the voltage IVC-Vt, when the oscillating voltage OSC oscillating with a constant period transitions from the "high" level to the "low" level, the output of the NAND gate NA1 is output. The signal becomes " high " level and the pumping operation by the capacitor C2 is performed so that the node c becomes the voltage 2IVC-Vt. Therefore, the voltage 2IVC-2Vt is transmitted to the node d. This voltage is continuously maintained by the oscillating voltage OSC while a periodic pumping operation is performed so that the voltage of the node b maintains the "high" level.

FIG. 2 is a graph showing a change in voltage over time t of the node d and the output data DQ of the data output driver of the semiconductor memory device shown in FIG. 1, and from the graph of FIG. As this elapses, the level of the node d gradually decreases, and as the level of the node d gradually decreases, the level of the output data DQ also gradually decreases.

The data output driver of the conventional semiconductor memory device as described above pumps the gate voltage of the pull-up NMOS transistor N6 to the voltage (2IVC-2Vt) level by a level compensation circuit, but the gate of the pull-up NMOS transistor N6. There is a problem in that the output data DQ of the external power supply voltage EVC level cannot be generated because it is not sufficient to compensate for the leakage current generated in the circuit.

This is because the voltage applied to the gate of the pull-up NMOS transistor N6 is lowered as the internal power supply voltage of the semiconductor memory device is lowered.

Fig. 3 is a circuit diagram of the level compensation circuit and the driver of the semiconductor memory device of the present invention, and has the same configuration as that of the conventional semiconductor memory device shown in Fig. 1. However, the high voltage VPP is applied to the precharge circuit 22-2 instead of the internal power supply voltage IVC.

In Fig. 3, the sign and number of the other blocks are the same as the sign and number of the blocks shown in Fig. 1, 12 is indicated by 22, 12-1 by 22-1, 12-2 by 22-2. Each was marked.

The operation of the circuit shown in Fig. 3 is as follows.

The node a is precharged from the internal power supply voltage IVC to the voltage IVC-Vt minus the threshold voltage Vt of the NMOS transistor N1.

When data "low" level DB is input, output data DQ of "low" level is generated.

On the other hand, when the data DB of the "high" level is input, the inverter I1 generates a signal of "low" level, and the inverter I2 generates a signal of "high" level. Accordingly, the NMOS transistor N2 is turned off, the PMOS transistor P1 is turned on, and a pumping operation by the capacitor C1 is performed to pump the voltage of the node a to the voltage 2IVC-Vt. Thus, the voltage at node a is transferred to node b. That is, the voltage 2IVC-Vt is transmitted to the node b. The voltage at node d is the same as the voltage at node b, so that NMOS transistor N3 is turned on to node c with voltages V (d) -Vt, where voltage V (d )) Refers to the voltage of node d)) is transmitted.

When the node c is precharged with the voltage V (d) -Vt, when the oscillation voltage OSC oscillating with a constant period transitions from the "high" level to the "low" level, the NAND gate NA1 ) Output signal becomes " high " level to perform the pumping operation by the capacitor C2 so that the node c becomes the voltage V (d) + IVC-Vt. Therefore, the voltage V (d) + IVC-2Vt is transmitted to the node d. This voltage is continuously maintained by the oscillating voltage OSC while a periodic pumping operation is performed so that the voltage of the node b maintains the "high" level.

FIG. 4 is a graph showing a change in voltage over time t of the node d and the output data DQ of the data output driver of the semiconductor memory device shown in FIG. 3. As time passes, it can be seen that the level of the node d is kept constant, and the level of the output data DQ is also kept constant.

The data output driver of the semiconductor memory device of the present invention compensates for the leakage current generated at the gate of the pull-up NMOS transistor by using the high voltage (VPP) as the power supply voltage of the precharge circuit, thereby raising the "high" level of the output data to a constant level. I can keep it.

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

The data output driver of the semiconductor memory device of the present invention compensates the voltage drop caused by the leakage component generated at the gate of the pull-up NMOS transistor so that the output data can maintain a constant "high" level.

Therefore, the reliability of the semiconductor memory device can be improved by applying the data output driver of the present invention.

Claims (3)

First precharge means for precharging the first node; First pumping means for pumping the first node in response to data in a first state and outputting a precharged voltage of the first node to a second node; Reset means for resetting the second node in response to the data in a second state; Second precharge means connected to a high voltage for precharging a third node in response to a voltage of the second node; Second pumping means for pumping the third node and pumping the voltage of the second node by the pumped voltage in response to a signal combining the voltage of the second node and the oscillation voltage; A pull-up transistor for pulling up output data in response to a voltage of the second node; And And a pull-down transistor for pulling down the output data in response to the second state data. The method of claim 1, wherein the pull-up transistor And a first NMOS transistor having a drain to which an external power supply voltage is applied and a gate to which the voltage of the second node is applied. The method of claim 1, wherein the second precharge means A second NMOS transistor having a drain to which the high voltage is applied and a gate to which the voltage of the second node is applied; A third NMOS transistor having a drain connected to a source of the second NMOS transistor and a gate to which the high voltage is applied; And And a fourth NMOS transistor having a source of the third NMOS transistor, a gate and a drain commonly connected to the third node, and a source connected to the second node.