KR20020002997A - Method for forming a dual gate of a semiconductor device - Google Patents
Method for forming a dual gate of a semiconductor device Download PDFInfo
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- KR20020002997A KR20020002997A KR1020000037378A KR20000037378A KR20020002997A KR 20020002997 A KR20020002997 A KR 20020002997A KR 1020000037378 A KR1020000037378 A KR 1020000037378A KR 20000037378 A KR20000037378 A KR 20000037378A KR 20020002997 A KR20020002997 A KR 20020002997A
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- forming
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 230000009977 dual effect Effects 0.000 title 1
- 238000005468 ion implantation Methods 0.000 claims abstract description 24
- 239000002019 doping agent Substances 0.000 claims abstract description 18
- 229910052732 germanium Inorganic materials 0.000 claims abstract description 11
- 229910052751 metal Inorganic materials 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 229910021332 silicide Inorganic materials 0.000 claims abstract description 8
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 6
- -1 germanium ions Chemical class 0.000 claims abstract description 5
- 150000002500 ions Chemical group 0.000 claims description 21
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 13
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 8
- 229910052796 boron Inorganic materials 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 8
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 3
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 3
- 238000000151 deposition Methods 0.000 claims description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 2
- 239000000203 mixture Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 abstract 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 1
- 239000011800 void material Substances 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 6
- 238000010438 heat treatment Methods 0.000 description 5
- 230000004913 activation Effects 0.000 description 3
- 230000006866 deterioration Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
- H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
- H01L21/32155—Doping polycristalline - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
- H01L29/4933—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
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- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Electrodes Of Semiconductors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
본 발명은 반도체 소자의 이중 게이트의 형성 방법에 관한 것으로, 특히 게이트의 공핍을 방지하고, 후속 열처리에도 도펀트들의 확산을 최소화하여 확산에 의한 게이트 산화막의 열화 및 임계전압, 변동, 단채널 효과를 방지하는 등 전기적 특성을 향상시킬 수 있는 반도체 소자의 이중 게이트의 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming a double gate of a semiconductor device, and in particular, to prevent gate depletion and to minimize diffusion of dopants in subsequent heat treatment, thereby preventing deterioration of gate oxide film due to diffusion and threshold voltage, fluctuation, and short channel effect. The present invention relates to a method of forming a double gate of a semiconductor device capable of improving electrical characteristics.
종래의 반도체 소자의 이중 게이트의 형성 방법에 관해 설명하면 다음과 같다.Hereinafter, a method of forming a double gate of a conventional semiconductor device will be described.
먼저, 기판위에 게이트 산화막을 형성하고 그위에 비정질 실리콘이나 도핑되지 않은 폴리-실리콘을 형성한다.First, a gate oxide film is formed on a substrate and amorphous silicon or undoped poly-silicon is formed thereon.
그리고, 폴리 게이트 도우핑을 위해 이온 주입을 실시하는데, p+ 폴리의 경우, 보론 또는 BF2를, p+ 폴리의 경우에는, 인(P) 또는 비소(As) 로 이온 주입한다.In addition, ion implantation is performed for poly gate doping, and in the case of p + poly, boron or BF 2 is implanted into phosphorus (P) or arsenic (As).
게이트의 저항을 낮추기 위해 금속 또는 금속-실리사이드, 금속-니트라이드를 형성하고, 마스크 산화막을 증착한후, 포토/식각 곤정을 실시하여 이중 게이트를 패터닝한다.In order to lower the resistance of the gate, a metal, metal-silicide, metal-nitride is formed, a mask oxide film is deposited, and photo / etching is performed to pattern the double gate.
그후, 후속 열처리에 의해 게이트에 이온 주입된 도펀트들을 활성화하게 된다.Subsequent heat treatment then activates the dopants implanted into the gate.
이때, p+ 폴리 게이트의 경우, 이온 주입된 보론은 후속 열처리에 의해 게이트 산화막이나 실리콘의 채널 영역으로 확산하여 게이트 산화막의 열화 및 임계전압, 변동, 단채널 효과 등을 유발하게 되고, n+ 폴리 게이트의 경우에는, 게이트산화막에 가까운 폴리-실리콘 영역에서의 인(P) 농도의 감소로 인해 게이트의 공핍을 유발하는 문제점을 가지고 있다.In this case, in the case of p + poly gate, the ion implanted boron diffuses into the gate oxide layer or the channel region of the silicon by subsequent heat treatment, causing deterioration of the gate oxide layer, threshold voltage, variation, and short channel effect. In this case, the phosphorus (P) concentration in the poly-silicon region close to the gate oxide film causes a problem of depletion of the gate.
본 발명은 상기 문제점을 해소하기 위해 안출된 것으로, 게이트의 공핍을 방지하고, 후속 열처리에도 도펀트들의 확산을 최소화하여 확산에 의한 게이트 산화막의 열화 및 임계전압, 변동, 단채널 효과를 방지하는 등 전기적 특성을 향상시킬 수 있는 반도체 소자의 이중 게이트의 형성 방법을 제공함에 그 목적이 있다.The present invention has been made to solve the above problems, to prevent the depletion of the gate, and to minimize the diffusion of the dopants in subsequent heat treatment to prevent degradation of the gate oxide film due to diffusion and threshold voltage, fluctuation, short channel effect, etc. It is an object of the present invention to provide a method for forming a double gate of a semiconductor device capable of improving characteristics.
도 1은 종래의 반도체 소자의 이중 게이트의 형성 방법의 공정 순서를 나타낸 순서도.1 is a flowchart showing a process procedure of a method for forming a double gate of a conventional semiconductor device.
도 2(a)-도 2(e) 는 본 발명의 반도체 소자의 이중 게이트의 형성 방법의 공정 순서를 나타낸 단면도.2 (a) to 2 (e) are cross-sectional views showing a process sequence of a method for forming a double gate of a semiconductor device of the present invention.
도 3은 본 발명의 반도체 소자의 이중 게이트의 형성 방법의 공정 순서를 나타낸 순서도.3 is a flowchart showing a process sequence of a method of forming a double gate of a semiconductor device of the present invention.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
1 : 반도체 기판 2 : 소자 분리막1: semiconductor substrate 2: device isolation film
3 : 게이트 산화막 4 : 비정질 실리콘3: gate oxide film 4: amorphous silicon
5 : 게르마늄 이온 주입 6 : 폴리 게이트 이온 주입5: germanium ion implantation 6: poly gate ion implantation
7 : 레이저 열공정 9 : 마스크 산화막7: laser thermal process 9: mask oxide film
8 : 금속 또는 금속-실리사이드, 금속-니트라이드8: metal or metal-silicide, metal-nitride
상기 목적을 달성하기 위한 본 발명의 반도체 소자의 이중 게이트의 형성 방법은 반도체 기판위에 소자 분리막을 형성하는 단계, 게이트 산화막을 형성시킨후, 비정질 실리콘이나 도우핑되지 않은 폴리-실리콘을 형성하는 단계, 게르마늄 이온을 주입하는 단계, 폴리 도우핑을 위한 이온 주입을 실시하는 단계, 레이저 열 공정을 실시하는 단계, 금속 또는 금속-실리사이드, 금속-니트라이드를 형성하고, 마스크 산화막을 증착한후, 포토/식각 공정을 실시하여 게이트 전극을 패터닝하는 단계를 포함한다.The method of forming a double gate of a semiconductor device of the present invention for achieving the above object comprises the steps of forming a device isolation film on a semiconductor substrate, after forming a gate oxide film, to form amorphous silicon or undoped poly-silicon, Implanting germanium ions, performing ion implantation for poly doping, performing a laser thermal process, forming a metal or metal-silicide, metal-nitride, depositing a mask oxide film, and then Patterning the gate electrode by performing an etching process.
이하, 본 발명의 바람직한 실시예를 첨부 도면들을 참조하여 상세히 설명한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
먼저, 레이저 열 공정(Laser Thermal Process, 이하 LTP 라함)에 관해 간략하게 설명하면 다음과 같다.First, the laser thermal process (hereinafter referred to as LTP) will be briefly described.
레이저 열 공정은 308 nm XeCl 엑사이머 레이저를 사용하여 수 ns 동안 가열하는데, 노출된 실리콘층이 용융된후 다시 수 ns 동안 재결정화시키는 어닐링 공정이다.The laser thermal process is heated for several ns using a 308 nm XeCl excimer laser, an annealing process in which the exposed silicon layer is melted and then recrystallized for several ns.
LTP 를 진행하기 전에 게르마늄이나 실리콘과 같은 중이온으로 먼저 이온 주입하게 되면, LTP 하려는 실리콘층이 비정질화되기 때문에, 실리콘의 용융 온도를 낮출 수 있고, 또한, 폴리 도우핑을 위해 이온 주입된 도펀트들이 이 비정질된 영역에서만 활성화가 국한된다.If the ion is first implanted with heavy ions such as germanium or silicon before proceeding with LTP, the silicon layer to be LTP becomes amorphous, so that the melting temperature of the silicon can be lowered and the dopants implanted for poly doping Activation is limited only in the amorphous region.
그리고, LTP 는 실리콘을 용융시켰다가 다시 재결정화되는 공정이므로, 이온 주입된 도펀트들이 고체 가용성이 아닌 액체 가용성으로 용해되므로 활성화되는 효과는 기존의 약 10 배 이상이며, 한번 LTP 받은 도펀트들은 후속 열처리에 의해서도 더 이상 확산하지 않는 특성을 보인다.In addition, since LTP is a process in which silicon is melted and recrystallized again, ion implanted dopants are dissolved in liquid solubility rather than solid solubility, and thus the activation effect is about 10 times or more. It also shows the characteristics that do not diffuse anymore.
도 2(a)-도 2(e) 는 본 발명의 반도체 소자의 이중 게이트의 형성 방법의 공정 순서를 나타낸 단면도이다.2 (a) to 2 (e) are cross-sectional views showing the procedure of the method of forming the double gate of the semiconductor device of the present invention.
도 3은 본 발명의 반도체 소자의 이중 게이트의 형성 방법의 공정 순서를 나타낸 순서도이다.3 is a flowchart showing a process procedure of a method of forming a double gate of a semiconductor device of the present invention.
도 3에 도시된 바대로, 본 발명의 반도체 소자의 이중 게이트의 형성 방법은 반도체 기판(1)위에 소자 분리막(2)을 형성하는 단계(S100), 게이트 산화막(3)을 형성시킨후, 비정질 실리콘(4)이나 도우핑되지 않은 폴리-실리콘을 형성하는 단계( S200), 게르마늄 이온을 주입하는 단계(S300), 폴리 도우핑을 위한 이온 주입을 실시하는 단계(S400), 레이저 열 공정을 실시하는 단계(S500), 금속 또는 금속-실리사이드, 금속-니트라이드를 형성하고, 마스크 산화막(9)을 증착한후, 포토/식각 공정을 실시하여 게이트 전극을 패터닝하는 단계(S600)를 포함한다.As shown in FIG. 3, in the method of forming a double gate of a semiconductor device of the present invention, forming the device isolation film 2 on the semiconductor substrate 1 (S100), after forming the gate oxide film 3, is amorphous. Forming silicon (4) or undoped poly-silicon (S200), implanting germanium ions (S300), performing ion implantation for polydoping (S400), and performing a laser thermal process And forming a metal or metal-silicide and metal-nitride, depositing a mask oxide layer 9, and performing a photo / etch process to pattern the gate electrode (S600).
부연 설명하면 다음과 같다.Further explanation is as follows.
상기 게이트 전극으로서 비정질 실리콘(4)이나 도우핑되지 않은 폴리-실리콘을 사용하며, LPCVD 로 300∼2000 Å 의 두께로 형성하며, 게르마늄의 이온 주입을 실시하여 후속 LTP 후 실리콘-게르마늄을 형성하고, 게르마늄의 이온 주입은 기형성된 실리콘 영역이 충분히 비정질화 될 정도의 조건으로 이온 주입하며, 상기 조건으로는 에너지는 5∼100 keV 이고, 주입량은 1×1015∼5×1016이온/cm2이다.Amorphous silicon (4) or undoped poly-silicon is used as the gate electrode, and is formed to a thickness of 300 to 2000 kPa by LPCVD, and ion implantation of germanium is performed to form silicon-germanium after subsequent LTP. Germanium ion implantation is ion implanted under conditions such that the preformed silicon region is sufficiently amorphous, wherein the energy is 5 to 100 keV and the implantation amount is 1 × 10 15 to 5 × 10 16 ions / cm 2 . .
그리고, 폴리 도우핑을 위한 이온 주입시, p+ 폴리 게이트의 이온 주입의 경우, 도펀트로는 보론이나 BF2이나 이들을 혼합하여 사용하며, 상기 도펀트로서 보론을 사용할때, 1∼10 keV 의 에너지에서 주입량은 1×1015∼1×1016이온/cm2으로 이온 주입하고, 상기 도펀트로서 BF2를 사용할때, 5∼50 keV 의 에너지에서 주입량은 1×1015∼1×1016이온/cm2으로 이온 주입한다.In the case of ion implantation for poly doping, in case of ion implantation of p + poly gate, boron or BF 2 or a mixture thereof is used as a dopant, and when boron is used as the dopant, the amount of implantation is performed at an energy of 1 to 10 keV. Silver is ion implanted at 1 × 10 15 to 1 × 10 16 ions / cm 2 , and when BF 2 is used as the dopant, the implantation amount is 1 × 10 15 to 1 × 10 16 ions / cm 2 at an energy of 5-50 keV. Ion implant.
또한, 상기 도펀트로서 BF2+ B 혼합 이온 주입시에는, 5∼50 keV 의 에너지에서 주입량은 1×1015∼1×1016이온/cm2으로 BF2를 1차로 이온 주입하고, 5∼50 keV 의 에너지에서 주입량은 1×1015∼1×1016이온/cm2으로 보론을 2차로 이온 주입하고, 폴리 도우핑을 위한 이온 주입시, n+ 폴리 게이트의 이온 주입의 경우, 3∼30 keV 의 에너지에서 주입량은 1×1015∼1×1016이온/cm2으로 인을 이온 주입한다.Further, as the dopant, BF 2 + B mixed at the time of ion implantation, in a dose of 5 to 50 keV energy is 1 × 10 15 ~1 × 10 16 ions / cm 2 by ion implantation car 1, and a 5 to 50 BF 2 At the keV energy, the implantation amount is 1 × 10 15 to 1 × 10 16 ions / cm 2, and boron is secondarily implanted, and when implanted for poly doping, 3 to 30 keV for ion implantation of n + poly gate The phosphorus ion is implanted at an energy of 1 × 10 15 to 1 × 10 16 ions / cm 2 .
그리고, 폴리 게이트 도펀트의 활성화를 위해 레이저 열공정을 사용하며, 상기 레이저 열공정은 게이트 위의 실리콘 영역이 모두 용융되었다가 다시 재결정화될 수 있는 정도의 에너지로 하며, 이는 0.2 J/cm22.0 J/cm2로 하고, 형성된 폴 리-실리콘 위에 금속 또는 금속-실리사이드, 금속-니트라이드를 200∼1500 Å 의 두께로 형성하고, 마스크 산화막을 500∼1500 Å 의 두께로 증착한다.In addition, a laser thermal process is used to activate the poly gate dopant, and the laser thermal process is such that the energy of the silicon region on the gate is melted and recrystallized, which is 0.2 J / cm 2 2.0 J / cm 2 , a metal, metal-silicide, metal-nitride is formed on the formed poly-silicon to a thickness of 200 to 1500 kPa, and a mask oxide film is deposited to a thickness of 500 to 1500 kPa.
이상 설명한 바와 같이, 본 발명은 폴리 도우핑을 위한 도펀트 이온 주입전, 게르마늄 비정질을 선 이온 주입하고, 이후 LTP 함에 따라 실리콘-게르마늄을 형성하는 한편, LTP 가 실리콘을 용융시켰다가 재결정화시키는 어닐링 공정이므로, 가용성이 매우 증가하여 활성화가 극대화됨에 따라 게이트의 공핍을 방지할 수 있을뿐만 아니라, 후속 열처리에도 도펀트들의 확산을 최소화하여 확산에 의한 게이트 산화막의 열화 및 임계전압, 변동, 단채널 효과를 방지하는 등 전기적 특성을 향상시킬 수 있는 효과가 있다.As described above, the present invention is an annealing process in which before the dopant ion implantation for poly doping, germanium amorphous pre-ion implantation, and then LTP to form silicon-germanium, while LTP melts and recrystallizes silicon. In addition, the availability is greatly increased and activation is maximized to prevent depletion of the gate, and also to minimize the diffusion of dopants in subsequent heat treatments to prevent deterioration of gate oxide film and threshold voltage, fluctuation, and short channel effects due to diffusion. This has the effect of improving the electrical characteristics.
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