KR20020002975A - Method for manufacturing semiconductor device - Google Patents
Method for manufacturing semiconductor device Download PDFInfo
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- KR20020002975A KR20020002975A KR1020000037354A KR20000037354A KR20020002975A KR 20020002975 A KR20020002975 A KR 20020002975A KR 1020000037354 A KR1020000037354 A KR 1020000037354A KR 20000037354 A KR20000037354 A KR 20000037354A KR 20020002975 A KR20020002975 A KR 20020002975A
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- Prior art keywords
- titanium
- titanium nitride
- film
- nitride film
- depositing
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 70
- 239000010936 titanium Substances 0.000 claims abstract description 36
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 30
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 29
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 18
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 18
- 239000010937 tungsten Substances 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 10
- 238000000151 deposition Methods 0.000 claims description 26
- 239000002574 poison Substances 0.000 claims description 17
- 231100000614 poison Toxicity 0.000 claims description 17
- 238000005240 physical vapour deposition Methods 0.000 claims description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- 238000010438 heat treatment Methods 0.000 claims description 11
- 229910021332 silicide Inorganic materials 0.000 claims description 10
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 10
- 230000007704 transition Effects 0.000 claims description 7
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 239000007789 gas Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract description 32
- 230000008569 process Effects 0.000 abstract description 21
- 230000004888 barrier function Effects 0.000 abstract description 11
- 239000011229 interlayer Substances 0.000 abstract description 10
- 229910021341 titanium silicide Inorganic materials 0.000 abstract description 9
- 238000009792 diffusion process Methods 0.000 abstract description 6
- 239000012535 impurity Substances 0.000 abstract description 6
- 238000005530 etching Methods 0.000 abstract description 2
- 238000005289 physical deposition Methods 0.000 abstract 1
- 229910052751 metal Inorganic materials 0.000 description 8
- 239000002184 metal Substances 0.000 description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 5
- 239000001301 oxygen Substances 0.000 description 5
- 229910052760 oxygen Inorganic materials 0.000 description 5
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910052731 fluorine Inorganic materials 0.000 description 3
- 239000011737 fluorine Substances 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 230000002776 aggregation Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 239000002341 toxic gas Substances 0.000 description 2
- 229910010421 TiNx Inorganic materials 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000011065 in-situ storage Methods 0.000 description 1
- 238000012423 maintenance Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 231100000956 nontoxicity Toxicity 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000007669 thermal treatment Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
- H10B12/48—Data lines or contacts therefor
- H10B12/482—Bit lines
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Electrodes Of Semiconductors (AREA)
- Semiconductor Memories (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 DRAM에서 텅스텐을 이용한 비트라인의 형성 방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for forming a bit line using tungsten in a DRAM.
일반적으로 DRAM 제조시 비트라인(Bitline)을 형성하는 물질로 금속층을 이용하는데, 이러한 금속층으로는 PVD-Ti/TiN, PVD-Ti/TiN + TiCl4CVD-TiN, TiCl4Ti/TiN 등이 있다. 상기한 금속층 증착을 위한 기술이 콘택에서 지니는 단차피복성 (Step coverage)에 따라 반도체 세대별로 차별 적용되었거나 적용될 기술이다.Generally, a metal layer is used as a material to form a bitline in DRAM manufacturing, and such metal layers include PVD-Ti / TiN, PVD-Ti / TiN + TiCl 4 CVD-TiN, TiCl 4 Ti / TiN, and the like. . The technique for depositing the metal layer is applied or discriminated for each semiconductor generation according to the step coverage of the contact.
이와 같이 비트라인 물질을 적용한 다양한 기술들이 제안되었는데, 첨부도면을 참조하여 종래기술에 따른 비트라인 형성 방법을 설명하기로 한다.As described above, various techniques using bitline materials have been proposed, and a bitline forming method according to the related art will be described with reference to the accompanying drawings.
도 1은 종래기술에 따른 비트라인 형성 방법의 일예를 나타낸 도면으로서, 소정 공정이 완료된 반도체기판(11) 상에 층간절연막(12)을 증착한 다음, 상기 층간절연막(12)을 선택식각하여 상기 반도체 기판(11)의 소정 표면이 노출되는 콘택홀을 형성하고, 상기 콘택홀을 포함한 전면에 스퍼터링증착법(Sputtering)을 이용하여 티타늄(Ti)(13), 티타늄나이트라이드(TiN)(14)를 순차적으로 증착한다. 도면부호 11a는 티타늄실리사이드를 나타낸다.1 is a view illustrating an example of a method for forming a bit line according to the related art, in which an interlayer insulating film 12 is deposited on a semiconductor substrate 11 on which a predetermined process is completed, and then selectively etching the interlayer insulating film 12. A contact hole exposing a predetermined surface of the semiconductor substrate 11 is formed, and titanium (Ti) 13 and titanium nitride (TiN) 14 are formed on the entire surface including the contact hole by sputtering. Deposition sequentially. Reference numeral 11a denotes titanium silicide.
그러나, 도시된 바와 같이, 티타늄나이트라이드(TiN)(14), 티타늄(Ti)(13)을 증착하기 위한 스퍼터링증착법은 단차피복성의 한계를 나타내기 때문에, 소자의 집적도(0.2㎛ 이하)가 증가하면 증착이 불가능하다.However, as shown, the sputtering deposition method for depositing the titanium nitride (TiN) 14 and the titanium (Ti) 13 exhibits a limit of step coverage, so that the density of the device (0.2 μm or less) is increased. Deposition is impossible.
또한, 티타늄 공정을 생략한 티타늄나이트라이드(TiNx) 공정의 경우, 티타늄이 다량 함유된 티타늄나이트라이드막을 증착하므로써 티타늄실리사이드화를 위한 티타늄 공정을 생략하고 티타늄나이트라이드 증착 후 급속열처리로 실리사이드반응이 이루어진다. 그러나, 이 방법은 티타늄나이트라이드를 증착할 시 타겟에 부분적으로 티타늄나이트라이드가 형성되므로 플라즈마에 의한 스퍼터링시 그 수율이 타겟 전체에 걸쳐 달라짐으로 파티클이 발생되는 문제점이 있다.In addition, in the case of a titanium nitride (TiNx) process in which a titanium process is omitted, a titanium nitride film containing a large amount of titanium is deposited to omit a titanium process for titanium silicide, and a silicide reaction is performed by rapid thermal treatment after the titanium nitride is deposited. . However, in this method, since titanium nitride is partially formed on the target when the titanium nitride is deposited, there is a problem in that particles are generated when the yield is varied throughout the target during sputtering by plasma.
도 2는 종래기술의 다른 예를 나타낸 도면으로서, IMP(Ionized Metal Plasma) Ti, IMP TiN에 의해 단차피복성을 개선하고자 티타늄(13), 티타늄나이트라이드(14)를 IMP법으로 증착한 다음, 상기 티타늄나이트라이드(14) 상에 TiCl4반응가스를 이용한 CVD(Chemical Vapor Deposition)-TiN(15)을 증착하고, 상기 CVD-TiN(15) 상에 CVD법으로 텅스텐막(16)를 증착한다.FIG. 2 is a view showing another example of the prior art, in which titanium (13) and titanium nitride (14) are deposited by IMP to improve step coverage by ionized metal plasma (IMP) Ti and IMP TiN. Chemical Vapor Deposition (CVD) -TiN (15) using TiCl 4 reaction gas is deposited on the titanium nitride (14), and a tungsten film (16) is deposited on the CVD-TiN (15) by CVD. .
그러나, W-CVD공정에 대한 배리어로서 IMP TiN(14)만으로는 충분하지 못하기 때문에 TiCl4CVD TiN 공정이 실시되어야만 하고, 텅스텐플러그(W-plug)에 대한 배리어로서 TiN은 딥포이즌모드(deep poison mode)가 효과적이나, IMP TiN의 경우 포이즌모드(Poison mode)에 의한 스터핑 효과(Stuffing effect)가 통상 TiN에 비하여 불리하다.However, since the IMP TiN 14 alone is not sufficient as a barrier to the W-CVD process, the TiCl 4 CVD TiN process must be performed, and the TiN as a barrier to tungsten plug (W-plug) is in the deep poison mode (deep poison). mode) is effective, but in the case of IMP TiN, the stuffing effect due to the poison mode (Poison mode) is generally disadvantageous compared to TiN.
도 3은 종래기술에 따른 또 다른 예를 나타낸 도면으로서, TiCl4CVD Ti기술 을 추가하여 인시튜로 티타늄실리사이드막(Ti-Silicide)(11a)을 형성한다.3 is a view showing another example according to the prior art, in which a titanium silicide film (Ti-Silicide) 11a is formed in situ by adding TiCl 4 CVD Ti technology.
즉, TiCl4CVD-Ti막(17)을 증착한 다음 TiCl4CVD-TiN막(18)을 증착하므로써후속 텅스텐플러그(19)에 대한 배리어층을 형성한다.That is, by depositing the TiCl 4 CVD-Ti film 17 and then depositing the TiCl 4 CVD-TiN film 18 to form a barrier layer for the subsequent tungsten plug 19.
그러나, TiCl4를 이용한 CVD공정의 경우, 그 산출량(Throughput)이 20wfs/hr미만으로서 PVD 공정에 비해 매우 낮으며, 주기적으로 챔버(Chamber)를 세정해야만 하는 문제점이 있다. 또한, Cl계 공정가스를 사용하므로 후처리 문제 및 위험성이 있으며, 세정시에도 Cl 또는 ClF3와 같은 독성가스(Toxic gas)를 사용해야만 하는 문제점이 있다.However, in the CVD process using TiCl 4 , the throughput is less than 20 wfs / hr, which is very low compared to the PVD process, and there is a problem in that the chamber must be periodically cleaned. In addition, since Cl-based process gas is used, there is a post-treatment problem and danger, and there is a problem that a toxic gas such as Cl or ClF 3 must be used even when cleaning.
본 발명은 상기한 종래기술의 제반 문제점을 해결하기 위해 안출한 것으로서, 물리적증착법을 이용하여 텅스텐플러그의 배리어층을 형성하므로써 산출량 및 독성가스사용에 대한 문제를 해결하고, 후속 열공정에 의해 산소나 불소 등의 불순물이 확산되는 것을 방지하는데 적합한 반도체 소자의 제조 방법을 제공함에 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, by forming a barrier layer of tungsten plug using the physical vapor deposition method to solve the problem of output and toxic gas use, by the subsequent thermal process It is an object of the present invention to provide a method for manufacturing a semiconductor device suitable for preventing diffusion of impurities such as fluorine.
도 1은 종래기술의 제 1 예를 나타낸 도면,1 is a view showing a first example of the prior art,
도 2는 종래기술의 제 2 예를 나타낸 도면,2 is a view showing a second example of the prior art;
도 3은 종래기술의 제 3 예를 나타낸 도면,3 is a view showing a third example of the prior art,
도 4a 내지 도 4c는 본 발명의 제 1 실시예에 따른 비트라인 형성 방법을 나타낸 도면,4A to 4C are diagrams illustrating a bit line forming method according to a first embodiment of the present invention;
도 5는 물리적증착법으로 증착된 티타늄나이트라이드막의 특성을 나타낸 도면,5 is a view showing the characteristics of the titanium nitride film deposited by physical vapor deposition,
도 6a 내지 도 6c는 본 발명의 제 2 실시예에 따른 비트라인 형성 방법을 나타낸 도면.6A to 6C illustrate a bit line forming method according to a second embodiment of the present invention.
*도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 층간절연막21 semiconductor substrate 22 interlayer insulating film
23 : 티타늄막 24 : 제 1 티타늄나이트라이드막23 titanium film 24 first titanium nitride film
25 : 제 2 티타늄나이트라이드막 26 : 티타늄실리사이드막25: second titanium nitride film 26: titanium silicide film
27 : 텅스텐막27: tungsten film
상기의 목적을 달성하기 위한 본 발명은 반도체 소자의 제조 방법에 있어서, 반도체 기판 상에 티타늄막을 증착하는 제 1 단계, 상기 티타늄막 상에 물리적증착법을 이용하여 불연속적으로 티타늄나이트라이드막을 증착하는 제 2 단계, 열처리를 실시하여 상기 반도체 기판과 티타늄막의 계면에 실리사이드막을 형성하는 제 3단계, 상기 열처리 후 상기 티타늄나이트라이드막 상에 화학적기상증착법으로 텅스텐막을 증착하는 제 4 단계를 포함하여 이루어짐을 특징으로 한다.The present invention for achieving the above object is a method of manufacturing a semiconductor device, the first step of depositing a titanium film on a semiconductor substrate, a method of depositing a titanium nitride film discontinuously by using a physical vapor deposition method on the titanium film A second step of forming a silicide film at an interface between the semiconductor substrate and the titanium film by performing a heat treatment, and a fourth step of depositing a tungsten film by chemical vapor deposition on the titanium nitride film after the heat treatment. It is done.
이하, 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부 도면을 참조하여 설명하기로 한다.Hereinafter, the preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .
도 4a 내지 도 4c는 본 발명의 실시예에 따른 비트라인 콘택 형성 방법을 나타낸 도면이다.4A through 4C illustrate a method of forming a bit line contact according to an exemplary embodiment of the present invention.
도 4a에 도시된 바와 같이, 트랜지스터 형성이 완료된 반도체 기판(21) 상에 층간절연막(22)을 형성하고, 상기 층간절연막(22)을 선택적으로 식각하여 상기 트랜지스터의 소오스/드레인에 접속되는 비트라인 또는 금속배선을 위한 콘택홀을 형성한다.As shown in FIG. 4A, an interlayer dielectric layer 22 is formed on the semiconductor substrate 21 on which transistor formation is completed, and the bit line is selectively etched to connect to the source / drain of the transistor. Alternatively, a contact hole for metal wiring is formed.
이어 상기 콘택홀을 포함한 층간절연막(22) 전면에 물리적증착법(PVD)인 IMP(Ionized Metal Plasma)법과 SIP(Self Ionized Plasma)법을 이용하여 티타늄막 (23)을 증착한다. 이처럼, 물리적증착법인 IMP법과 SIP법을 이용하면, 통상적인 물리적증착법의 장점, 예를 들면, 산출량, 유지보수의 용이성, 무독성, 축척된 공정경험 등을 유지하면서 단차피복성이 양호한 티타늄막을 증착할 수 있다.Subsequently, a titanium film 23 is deposited on the entire surface of the interlayer insulating layer 22 including the contact hole by using an ionized metal plasma (IMP) method and a self ionized plasma (SIP) method. In this way, the IMP method and the SIP method, which are physical vapor deposition methods, can be used to deposit titanium films having good step coverage while maintaining the advantages of conventional physical vapor deposition methods, for example, yield, ease of maintenance, nontoxicity, and accumulated process experience. Can be.
도 4b에 도시된 바와 같이, 상기 티타늄막(23) 상에 배리어(Barrier)로서, 티타늄나이트라이드막 을 증착하는데, 물리적증착법(PVD)만을 이용하여 2단계로 증착한다.As shown in FIG. 4B, a titanium nitride film is deposited on the titanium film 23 as a barrier, and is deposited in two steps using only physical vapor deposition (PVD).
먼저 제 1 티타늄나이트라이드막(24)을 증착하는 1단계에서는, 티타늄나이트라이드막의 밀도가 가장 높은 천이영역(Transition region)에 치우친 티타늄나이트라이드막을 증착하도록 질소/아르곤(N2/Ar)의 유량비를 조절한다.First, in the first step of depositing the first titanium nitride film 24, the flow rate ratio of nitrogen / argon (N 2 / Ar) to deposit the titanium nitride film biased to the transition region having the highest density of the titanium nitride film Adjust
여기서, 티타늄나이트라이드막은 상기 질소/아르곤의 혼합 비율에 따라 그 증착막의 특성이 다르게 되는데, 도 5에 도시된 바와 같이, 메탈릭모드(Metallic mode)와 포이즌모드(Poison mode)의 티타늄나이트라이드막으로 구분되며, 상기 메탈릭모드와 포이즌모드의 사이에 천이영역이 존재한다. 일반적으로 메탈릭모드와 포이즌모드는 N2유량에 의하여 결정되는데, 텅스텐플러그(w-plug)가 사용되는 콘택 또는 비아(Via)에는 포이즌모드 티타늄나이트라이드가 선별적으로 사용된다. 이는 포이즌모드의 티타늄나이트라이드막이 컬럼나(culumnar)구조보다 다공질(Porous)이기 때문에 이후 급속열처리(Rapid Thermal Process; RTP) 공정에 의한 질소(N2) 또는 산소(O2)의 스터핑(Stuffing)효과가 크기 때문이다.Herein, the titanium nitride film has different characteristics of the deposited film according to the mixing ratio of nitrogen / argon. As shown in FIG. 5, the titanium nitride film is a titanium nitride film in a metallic mode and a poison mode. The transition region exists between the metallic mode and the poison mode. In general, the metallic mode and the poison mode are determined by the N 2 flow rate. The poison mode titanium nitride is selectively used in a contact or via in which tungsten plug is used. Since the titanium nitride film in the poison mode is more porous than the columnar structure, the stuffing of nitrogen (N 2 ) or oxygen (O 2 ) by a rapid thermal process (RTP) process is followed. This is because the effect is large.
따라서 텅스텐비트라인에 사용되는 배리어층으로 상기 포이즌모드에 따른 티타늄나이트라이드막의 특성을 이용한다.Therefore, the barrier layer used in the tungsten bit line utilizes the characteristics of the titanium nitride film according to the poison mode.
상기 제 1 티타늄나이트라이드막(24) 증착시, 메탈릭모드로 치우치지 않도록 하는데, 이는 메탈릭모드의 경우 파티클이 발생되는 문제가 있기 때문이다.When the first titanium nitride film 24 is deposited, it is not biased in the metallic mode, because there is a problem that particles are generated in the metallic mode.
상기와 같이, 밀도가 높은 천이영역에 치우치도록 제 1 티타늄나이트라이드막(24)을 증착하므로써 800℃ 이상의 급속열처리(RTP)시 산소 등이 티타늄실리사이드 계면으로 확산하는 것을 억제할 수 있다.As described above, by depositing the first titanium nitride film 24 so as to be biased in the high density transition region, it is possible to suppress diffusion of oxygen or the like into the titanium silicide interface during rapid heat treatment (RTP) of 800 ° C. or higher.
이어 제 2 티타늄나이트라이드막(25)을 증착하는 2단계는, 질소/아르곤의 유량비가 포이즌모드에 깊숙히 치우친 영역으로 증착하도록 하는데, 이처럼 포이즌모드에 치우치도록 증착하면 800℃ 이상의 열처리 과정동안 제 1 티타늄나이트라이드막(24)에 대한 보충층으로서 스터핑효과가 크므로, 실리사이드 응집(Silicide Agglormeration)의 주요 요인인 산소(O2)가 대다수 2단계의 제 2 티타늄나이트라이드막(25)에 트랩핑(Trapping)되게 하므로써 1단계의 제 1 티타늄나이트라이드막 (24)에 실질적으로 확산되는 불순물의 경로를 차단하게 된다.Subsequently, in the second step of depositing the second titanium nitride film 25, the flow rate ratio of nitrogen / argon is deposited in a region deeply oriented in the poison mode. Since the stuffing effect is large as a supplementary layer to the titanium nitride film 24, oxygen (O 2 ), which is a major factor of silicide agglomeration, is applied to the second titanium nitride film 25 in most two stages. By trapping, the path of impurities substantially diffused in the first titanium nitride film 24 in one step is blocked.
또한, 스트레스 완화(Stress relaxation)에 대한 버퍼층(Buffer) 역할을 하는데, 이는 밀도가 높은 티타늄나이트라이드막이 두꺼운 경우, 고온의 열처리를 급속열처리공정 이후 캐패시터 공정에서도 받게되고 티타늄막의 실리사이드화에 의한 체적확장(Volume expansion)에 기인된 스트레스에 의해 깨지는 현상이 자주 발생된다. 그러나, 컬럼나(culumnar)구조이며 좀더 다공성인 제 2 티타늄나이트라이드막 (25)은 이러한 열공정사이클(Heat cycle)에 대해서 좀더 완충적이며, 제 1 티타늄나이트라이드막(24)이 받는 스트레스도 완충해주는 버퍼층역할을 해줄 수 있다. 즉, 밀도가 높은 제 1 티타늄나이트라이드막(24)이 제 1 티타늄나이트라이드막(24)과 제 2 티타늄나이트라이드막(25)을 합한 두께만큼 있는 경우보다 그 스트레스에 대한 저항성이 높다.In addition, it acts as a buffer layer for stress relaxation. When the titanium nitride film having a high density is thick, it is subjected to high temperature heat treatment in the capacitor process after the rapid heat treatment process and the volume expansion due to the silicideization of the titanium film. Cracking is often caused by stress caused by volume expansion. However, the columnar (culumnar) structure and the more porous second titanium nitride film 25 is more buffered against this heat cycle, and the stress of the first titanium nitride film 24 is also increased. It can act as a buffer layer to buffer. That is, the first titanium nitride film 24 having a high density has a higher resistance to stress than when the first titanium nitride film 24 and the second titanium nitride film 25 have the same thickness.
마지막으로, 이후 열공정 사이클동안 스터핑된 막의 성질을 이용하므로써 후속 텅스텐플러그 공정동안 불소계열의 원소가 실리콘쪽으로 확산하는 것을 방지할 수 있으므로 콘택저항이나 누설특성의 안정을 도모할 수 있다.Finally, by using the properties of the stuffed film during the subsequent thermal process cycle, it is possible to prevent the fluorine-based elements from diffusing into the silicon during the subsequent tungsten plug process, thereby improving the contact resistance and leakage characteristics.
도 4c에 도시된 바와 같이, 전면에 급속열처리 공정을 실시하여 실리사이드반응을 발생되어 상기 티타늄막(22)과 반도체 기판(21)의 계면에 티타늄실리사이드막(26)이 형성된다. 이어 상기 구조 전면에 화학증착법을 이용하여 텅스텐막(27)을 증착한다.As shown in FIG. 4C, a silicide reaction is generated by performing a rapid heat treatment process on the entire surface to form a titanium silicide layer 26 at an interface between the titanium layer 22 and the semiconductor substrate 21. Subsequently, a tungsten film 27 is deposited on the entire structure by chemical vapor deposition.
도 6a 내지 도 6c는 본 발명의 제 2 실시예에 따른 비트라인 형성 방법을 나타낸 도면이다.6A to 6C are diagrams illustrating a bit line forming method according to a second embodiment of the present invention.
도 6a에 도시된 바와 같이, 트랜지스터 형성이 완료된 반도체 기판(31) 상에 층간절연막(32)을 형성하고, 상기 층간절연막(32)을 선택적으로 식각하여 상기 트랜지스터의 소오스/드레인에 접속되는 비트라인 또는 금속배선을 위한 콘택홀을 형성한다.As shown in FIG. 6A, an interlayer insulating layer 32 is formed on the semiconductor substrate 31 on which transistor formation is completed, and the bit line is selectively etched to connect to the source / drain of the transistor. Alternatively, a contact hole for metal wiring is formed.
이어 상기 콘택홀을 포함한 층간절연막(32) 전면에 물리적증착법(PVD)인 IMP(Ionized Metal Plasma)법과 SIP(Self Ionized Plasma)법을 이용하여 단차피복성이 양호한 티타늄막(33)을 증착한다.Subsequently, a titanium film 33 having good step coverage is deposited on the interlayer insulating layer 32 including the contact hole by using an ionized metal plasma (IMP) method and a self ionized plasma (SIP) method.
이어 상기 티타늄막(33) 상에 배리어(Barrier)로서, 밀도가 가장 높은 천이영역에 치우진 제 1 티타늄나이트라이드막(34)을 증착하는데, 물리적증착법(PVD)을 이용하여 증착한다.Subsequently, a first titanium nitride film 34 deposited as a barrier is deposited on the titanium film 33 in a region having the highest density. The film is deposited using physical vapor deposition (PVD).
도 6b에 도시된 바와 같이, 열처리를 실시하여 실리사이드 반응을 발생시키므로써 상기 반도체 기판(31)과 티타늄막(33)의 계면에 티타늄실리사이드막(35)을 형성한다. 이 때, 상기 제 1 티타늄나이트라이드막(34)은 밀도가 높기 때문에 실리사이드 반응을 위한 열처리시 산소 등의 불순물이 티타늄실리사이드막(35)으로 확산되는 것을 방지한다.As shown in FIG. 6B, a silicide reaction is performed to generate a silicide reaction, thereby forming a titanium silicide layer 35 at an interface between the semiconductor substrate 31 and the titanium layer 33. At this time, since the first titanium nitride film 34 has a high density, impurities such as oxygen may be prevented from being diffused into the titanium silicide film 35 during the heat treatment for the silicide reaction.
도 6c에 도시된 바와 같이, 상기 제 1 티타늄나이트라이드막(34) 상에 딥포이즌모드의 제 2 티타늄나이트라이드막(36)을 증착하고, 상기 제 2 티타늄나이트라이드막(36) 상에 화학증착법으로 텅스텐막(37)을 증착한다.As shown in FIG. 6C, a second titanium nitride film 36 in deep poison mode is deposited on the first titanium nitride film 34, and a chemical is deposited on the second titanium nitride film 36. The tungsten film 37 is deposited by vapor deposition.
상술한 바와 같이, 본 발명에서는 텅스텐플러그의 배리어로서 티타늄나이트라이드막을 2단계로 증착하여 그레인경계면의 불연속성을 주므로써 불순물의 확산경로를 차단하며, 딥포이즌모드의 티타늄나이트라이드막을 스트레스에 대한 버퍼층으로 사용한다.As described above, in the present invention, the titanium nitride film is deposited as a barrier of tungsten plugs in two steps, thereby discontinuity of the grain boundary surface, thereby blocking the diffusion path of impurities, and using the deep poison mode titanium nitride film as a buffer layer for stress. use.
도면에 도시되지 않았지만, 티타늄나이트라이드막을 확산배리어층으로 이용하는 모든 공정에도 적용할 수 있다.Although not shown in the drawings, the present invention can also be applied to any process using a titanium nitride film as a diffusion barrier layer.
본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.
상술한 본 발명은 IMP와 SIP의 물리적증착법을 이용하여 텅스텐막을 균일하게 증착하므로써 단차피복성을 양호하게 하여 제품의 산출량을 증가시킬 수 있으며, 확산배리어층을 불연속적으로 증착하므로써 실리사이드의 응집을 방지하고 후속 열공정동안 산소, 불소 등의 불순물이 반도체 기판으로 확산하는 것을 방지하여 콘택저항이나 누설전류 특성을 향상시킬 수 있는 효과가 있다.According to the present invention described above, by uniformly depositing a tungsten film using physical vapor deposition of IMP and SIP, it is possible to increase the yield of the product by improving the step coverage, and to prevent the aggregation of silicide by discontinuously depositing the diffusion barrier layer. In addition, during the subsequent thermal process, impurities such as oxygen and fluorine are prevented from diffusing into the semiconductor substrate, thereby improving contact resistance and leakage current characteristics.
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