KR20020001265A - Liquid crystal display device with a partial display mode and method of driving the same - Google Patents

Abstract

PURPOSE: An LCD(Liquid Crystal Display) having a partial display mode is provided to make pixels of non-switched pixel circuits keep regular display states including specific color and gray scale by preventing generation of noise caused by off-current of access TFTs(Thin Film Transistor), leakage current of LC and coupling between switched signal lines and non-switched signal lines during a partial display mode. CONSTITUTION: An LCD having a partial display mode is an active matrix TFT-LCD. Plural first row lines(GL1-GLm,101) and plural column lines(DL1-DLn,102) are arranged in matrix form on the substrate of an LCD panel. Second row lines(PL1-PLm,104) are arranged parallel with the first row lines. Plural pixel circuits(112) are arranged at each cross between the first and second row lines and the column lines. Each pixel circuit includes an access TFT(114), an LC capacitor(116), a storage capacitor(118) and a switching transistor(120). In a partial display mode, if two row lines(GL1,GL2) are selected, partial display mode control signals(PM1,PM2) become active high. The other control signals(PM3-PMm) become inactive low. The outputs of corresponding level shifters(LS1,LS2) are logic low, and switching transistors of the second row lines(PL1,PL2) are turned off. The other level shifters(LS3-LSm) have logic high outputs, and the switching transistors of the second row lines(PL3-PLm) are turned on. Voltage at both terminals of corresponding LC capacitors and storage capacitors becomes the same as reference voltage(103).

Description

Liquid crystal display having a partial display mode and a driving method therefor {LIQUID CRYSTAL DISPLAY DEVICE WITH A PARTIAL DISPLAY MODE AND METHOD OF DRIVING THE SAME}

The present invention relates to a flat panel display device, and more particularly to a thin film transistor liquid crystal display device having a partial display mode and a driving method thereof. will be.

In recent mobile applications such as cordless phones, personal digital assistant (PDA) terminals, and the like, flat panel display devices such as liquid crystal displays, plasma display panels (PDPs), and electro-luminescence (EL) displays, etc. Is used as an essential component, and in particular, liquid crystal displays are widely used.

1 is a circuit diagram schematically showing a configuration of a typical thin film transistor liquid crystal display. Referring to FIG. 1, a thin film transistor liquid crystal display (TFT-LCD) includes a pixel array 10 formed on a panel. In the pixel array 10, a plurality (m) gate lines GL1-GLm (1), a plurality (n) data lines (DL1-DLn) (2), and a plurality (mxn) pixel circuits ( 12) is disposed on a substrate (not shown).

Each pixel circuit 12 controls the amount of light passing through the access transistor 14 serving as a switch and the liquid crystal as a dielectric and locally changing the light transmission characteristics of the liquid crystal according to the applied voltage. It consists of a liquid crystal capacitor (16), and a storage capacitor (18) for increasing the ability of collecting charges accumulated across the liquid crystal.

The liquid crystal display device, as is well known, includes a row driver 20 and a column driver 30. The row driver 20 is also commonly referred to as a 'gate driver' in the sense of driving the gate electrodes of the access transistors 14. The row driver 20 sequentially generates scan signals for selecting the gate lines 1. do. The column driver 30 drives the source electrodes of the access transistors 14, also referred to as a 'source driver', and the row driver 20 pulses the gate electrodes of the access transistors 14. When turned on, the access transistors 14 serve to actually apply the image signal voltages to the respective pixel circuits 12 through the data lines 2.

When an image signal voltage is applied to the corresponding liquid crystal capacitor 16 through each access transistor 14, the liquid crystal is driven. At this time, when the access transistor 14 is turned off, the liquid crystal capacitor 16 is in a floating state and the signal voltage applied thereto is maintained. According to this operating principle, it is possible to drive all the pixels of the panel by sequentially applying pulses to all the gate electrodes and applying image signal voltages to the corresponding source electrodes, respectively. After displaying an image of one frame in this manner, and displaying another frame continuously, a moving image can be displayed.

The charges applied to the liquid crystal capacitor 16 must be maintained for at least one frame, but it is difficult to sufficiently hold the liquid crystal capacitor 16 alone. For this reason, a storage capacitor 18 is provided which is connected in parallel with the liquid crystal capacitor 16. The storage capacitor 18 assists the liquid crystal capacitor 16 to store charge.

On the other hand, power consumption is just as important as image quality in mobile applications. Therefore, in order to reduce power consumption, the mobile application has a partial display mode in a concept relative to a conventional display mode (that is, a full display mode) in which a character or an image is displayed on the entire screen of the display device. ) Is introduced and used.

Entry into the partial display mode is made while the mobile device is not in use, in which only a certain portion of the display device pixel array (e.g., a portion where essential characters and images should be displayed) is driven and the remaining portions are not driven. . As such, only part of the screen is displayed while the device is not in use, thereby reducing power consumption.

However, when the partial display mode is applied to a mobile application device using a liquid crystal display device that does not have pixels emitting light itself, the following problem may occur. That is, the gate lines of the pixel circuits of the unselected portion of the pixel array are not driven during the partial display mode, in which case the off-current of the thin film access transistors 14, the leakage current of the liquid crystal ), Noise is generated in pixel circuits that are not driven due to coupling between the signal lines that are driven and the signal lines that are not driven, and the pixels that are not driven are caused to have a constant display state (i.e., Color and gradation state).

It is therefore an object of the present invention to provide a liquid crystal display device having a pixel array circuit and its driving circuits suitable for application of the partial display mode.

Another object of the present invention is to provide a method for driving a liquid crystal display device to maintain a stable display state even in a partial display mode.

1 is a circuit diagram schematically showing the configuration of a typical liquid crystal display device;

2 is a circuit diagram showing a first preferred embodiment of the liquid crystal display according to the present invention; And

3 is a circuit diagram showing a second preferred embodiment of the liquid crystal display according to the present invention.

* Description of the symbols for the main parts of the drawings *

100: pixel array circuit 101: first gate line

102: data line 103: reference voltage

104: second gate line 112: pixel circuit

200: row driver 300: column driver

400: partial display mode controller UGD1-UGDm: unit low driver

LS1-LSm: Level Shifter G1-G (m-1): Logic Gate

The liquid crystal display device of the present invention for achieving the above objects is the liquid crystal capacitors and storage of pixel circuits not selected by the row lines (gate lines) during the partial display mode in which characters and images are displayed only at a specific portion of the screen. It is characterized by a circuit for maintaining a constant potential difference between both ends of the capacitors. According to this aspect of the invention, due to the off-current of the access transistors, the leakage current of the liquid crystal, the coupling between the driven signal lines and the undriven signal lines, etc. in pixel circuits not driven during the partial display mode. Since the generation of noise can be prevented, the corresponding pixels of the non-driven pixel circuits can maintain a stable display state (i.e., a specific color and gradation).

A liquid crystal display according to an exemplary embodiment of the present invention includes a plurality of pixel circuits each disposed in a matrix at intersections of row lines (gate lines) and column lines (data or source lines). Each pixel circuit includes an access transistor connected to a corresponding one of the row lines and a corresponding one of the column lines, a liquid crystal capacitor connected between the access transistor and the reference voltage, between the access transistor and the reference voltage and And a storage capacitor connected in parallel with the liquid crystal capacitor. The liquid crystal display according to this embodiment includes a partial display mode controller for generating partial display mode control signals for selectively driving the pixel circuits during the partial display mode, and a liquid crystal capacitor between the access transistors of the pixel circuits and a reference voltage. And a plurality of switching transistors each connected in parallel with each other and driven by the partial display mode control signals, respectively.

In the partial display mode, switching transistors of pixel circuits not selected by row lines are turned on by corresponding partial display mode control signals, while switching transistors of pixel circuits selected by the row lines are selected. It is turned off by corresponding partial display mode control signals. In the entire display mode in which characters or images are displayed on the entire screen, all of the switching transistors of the pixel circuits are turned off by the partial display mode control signals.

Meanwhile, the switching transistors may be replaced by a plurality of diodes respectively connected in parallel with liquid crystal capacitors between the access transistors of the pixel circuits and the reference voltage and respectively driven by the partial display mode control signals. . In each pixel circuit, the diode's cathode is connected to an access transistor, and its anode is connected to a corresponding one of the second row lines. These diodes are driven in the same manner as the switching transistors.

A liquid crystal display according to another exemplary embodiment of the present invention includes a plurality of first row lines (or first gate lines) and a plurality of second row lines arranged in parallel with the first row lines. (Or second gate lines), a plurality of column lines (or data lines), and a plurality of pixel circuits each disposed in a matrix form at intersections of the row lines and the column lines. . Each pixel circuit includes an access transistor having a current path having one end connected to a corresponding one of the first row lines and a control electrode connected to a corresponding one of the column lines, and the other end of the access transistor current path and a reference. A liquid crystal capacitor connected between the voltage, a storage capacitor connected in parallel with the liquid crystal capacitor between the other end of the access transistor current path and the reference voltage, and between the other end of the access transistor current path and the reference voltage. And a switching transistor having a current path connected in parallel with the liquid crystal transistor and a control electrode connected with the corresponding second row line.

Further, the liquid crystal display of this embodiment includes a partial display mode controller for generating a plurality of partial display mode control signals, a row driver for driving the first and second row lines, and image data signals to the column lines. And a column driver for driving the column lines by applying each. The row driver is disposed to correspond to the first row lines, respectively, and is disposed between a plurality of unit row drivers and a pair of adjacent unit row drivers respectively for driving the first row lines. A plurality of logic gates disposed respectively, and a plurality of level shifters connected between the partial display mode control signals and the second row lines, respectively, and converting voltage levels of the partial display mode control signals. The unit row drivers sequentially drive the first row lines under the control of a known timing controller. End or NAND logic gates may be used as the logic gates.

Diodes may also be used instead of the switching transistors in this embodiment, each diode being connected in parallel with the liquid crystal capacitor between the access transistor and the corresponding second row line.

According to another feature of the present invention, a method of driving a liquid crystal display device is provided. According to this method, first, one of the display modes (full display mode or partial display mode) of the liquid crystal display device is selected, and then the pixel circuits of the liquid crystal display device are selectively driven when the partial display mode is selected, and finally As a result, both ends of the liquid crystal capacitors and the storage capacitors of the pixel circuits which are not driven during the partial display mode are maintained at a predetermined potential difference. The potential difference across each of the liquid crystal capacitors and the storage capacitors is preferably kept at 0V. A predetermined constant voltage is applied across the liquid crystal capacitors and the storage capacitors of the non-driven pixel circuits, preferably in the range of 5V to 7V (preferably 6V).

This feature of the present invention prevents noise from occurring in pixel circuits that are not driven during the partial display mode, so that the corresponding pixels of the pixel circuits that are not driven have a stable display state (i.e., a specific color and gradation). I can keep it.

Next, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Although specific circuit configurations, voltage ranges, and the like are presented here, it should be noted that this is for the purpose of aiding a clear understanding of the invention and is not intended to limit the invention thereto.

2 is a circuit diagram showing a first preferred embodiment of a liquid crystal display according to the present invention. The liquid crystal display is an active matrix thin film transistor liquid crystal display, and includes a plurality of m first row lines (hereinafter, 'first gate lines') in a region of the pixel array 100 of the liquid crystal panel. (GL1-GLm) 101 and a plurality (n) column lines (hereinafter referred to as 'data lines') (DL1-DLn) 102 are formed in a matrix form along rows and columns. (Not shown). In addition, second row lines (hereinafter, referred to as 'second gate lines') PL1-PLm 104 are arranged on the substrate of the panel in parallel with the first gate lines 101. A plurality of pixel circuits 112 are disposed at points where the first and second gate lines 101 and the data lines 102 cross each other.

Each pixel circuit 112 uses a thin film access transistor 114 that functions as a switch and a liquid crystal as a dielectric, and locally controls the amount of light passing through the light transmission characteristic of the liquid crystal according to the applied voltage. A liquid crystal capacitor 116, a storage capacitor 118 for increasing the ability of collecting charges accumulated across the liquid crystal, and a switching transistor 120.

The gate electrode of the thin film metal oxide semiconductor (MOS) access transistor 114 of each pixel circuit 112 is connected to a corresponding one of the first gate lines 101. One end (ie, source electrode) of the source-drain current path of the access transistor 114 is connected to the corresponding one of the data lines 102. The liquid crystal capacitor 116 and the storage capacitor 118 are parallel to each other between the other end of the current path of the access transistor 114 (that is, the drain electrode) and the reference voltage (or the common voltage V _COM : 5V-7V) 103. Leads to. The current path of the switching transistor 120 is connected in parallel with the liquid crystal capacitor 116 between the drain electrode of the access transistor 114 and the reference voltage 103.

The liquid crystal display may operate in a full display mode and a partial display mode, and when the partial display mode is selected, it is possible to selectively drive pixel circuits in the liquid crystal panel such that a character or an image is displayed only in a portion of the screen.

As shown in Fig. 2, the liquid crystal display of this embodiment has a row driver 200 for driving the first and second gate lines 101 and 104, and an image data signal to the data lines 102. As shown in Figs. And a column driver 300 for driving each of them.

The row driver 200 has a plurality (m) of unit row drivers UGG1-UGDm, which are arranged to correspond to the first gate lines GL1-GL _m 101, respectively. . The unit row drivers UGD1-UGDm are composed of an m-bit shift register circuit, and the first gate lines GL1-GLm 101 are controlled under a known timing controller (not shown). Drives sequentially. For example, immediately after the gate line GL1 is driven to an active high state by the unit row driver UGD1, the unit row driver UGD2 responds to the output of the driver UGD2 in response to the output of the driver UGD2. Drive GL2). In this manner, in the entire display mode, the first gate lines GL1 -GLm are sequentially driven by the unit row drivers UGD1 -UGDm.

The row driver 200 further includes a plurality of m−1 AND logic gates G1 -G (m−1). The (m-1) AND logic gates G1 -G (m-1) are disposed one by one between a pair of adjacent unit row drivers UGD1 -UGD _m . One of the two input terminals of each end gate (G1, G2, ..., or G (m-1)) is a unit row driver (UGD1, UGD2, ..., or UGD (m-1) immediately preceding it. Is connected to the output terminal of < RTI ID = 0.0 >)< / RTI > The output terminal of each AND gate (G1, G2, ..., or G (m-1)) is a unit row driver (GUD2, GUD3, ..., GUDm) immediately after the end.

On the other hand, a person having ordinary knowledge in the art may use transfer gate circuits, NAND logic gates, or other logic gates instead of the AND logic gates G1 -G (m-1). You can understand well.

In addition, the row driver 200 includes a plurality (m) of level shifters LS1 to LSm. The level shifters LS1-LSm are disposed to correspond to the second gate lines PL1 -PLm, respectively. These level shifters LS1-LSm convert input logic voltage levels swinging within a predetermined range (eg 0V-3V) to logic voltage levels of another range (eg 0V-10V), Inverted level shifters that output logic states by inverting them.

The liquid crystal display of this embodiment further includes a partial display mode controller 400. The controller 400 automatically detects whether a character or an image on the screen does not change for a predetermined time, or in response to a command provided from the outside, a plurality of controllers for controlling the liquid crystal display to enter the partial display mode. m) generates the partial display mode control signals PM1-PMm. The partial display mode control signals PM1-PMm from the partial display mode controller 400 are provided to the AND logic gates G1-Gm, respectively. In addition, the partial display mode control signals PM1-PMm are provided to the level shifters LS1-LSm, respectively. The level shifters LS1-LSm convert the logic voltage levels of the partial display mode control signals PM1-PMm within a predetermined range (eg, 0V to 10V) and use the converted signals to generate the second voltage. Drive the gate lines PL1 -PLm.

In the partial display mode, the partial display mode control signals corresponding to the pixel circuits 112 selected by the first gate lines 101 are maintained at a logic high (or logic '1') state, and the first gate Partial display mode control signals not selected by lines 101 remain at a logic low (or logic '0') state. For example, when two gate lines GL1 and GL2 are selected, the partial display mode control signals PM1 and PM2 become active high, and the remaining control signals PM3-PMm. Goes into the inactive low state. As a result, the AND gate G1 causes the output of the unit row driver UGD1 to be transferred directly to the next driver UGD2.

At this time, although the AND gate G2 also causes the output of the unit row driver UGD2 to be transferred directly to the next driver UGD3, the unit row driver UGD3 is disabled by the timing controller, thereby providing the corresponding gate line ( GL3) is not driven.

In this case, the outputs of the level shifters LS1 and LS2 are in a logic low state, so that the switching transistors 120 connected to the corresponding second gate lines PL1 and PL2 are It is turned off to operate in the same way as a conventional pixel circuit. On the other hand, the outputs of the remaining level shifters LS3-LSm go to a logic high state, so that the switching transistors 120 connected to the corresponding second gate lines PL3-Im are turned on to The voltage across the liquid crystal capacitors 116 and the storage capacitors 118 becomes equal to the reference voltage 103. This maintains a constant potential difference (0V) between the liquid crystal capacitors and the storage capacitors of the unselected pixel circuits.

As described above, in pixel circuits that are not driven during the partial display mode, a constant potential difference (0V) is maintained between the liquid crystal capacitors and the storage capacitors, so that the off-current of the access transistors, the leakage current of the liquid crystal, and the driven signal line are maintained. Noise due to coupling between the signal lines and the signal lines that are not driven can be prevented from occurring in pixel circuits that are not driven. As a result, the corresponding pixels of the non-driven pixel circuits can maintain a stable display state (ie, a specific color and gradation).

3 is a circuit diagram showing a second preferred embodiment of the liquid crystal display according to the present invention. Referring to FIG. 3, the liquid crystal display of this embodiment has the same circuit configuration as the liquid crystal display shown in FIG. 2 except for using diodes 122 instead of the switching transistors 120. As shown in FIG. 3, in each pixel circuit, the cathode of diode 122 is connected to an access transistor 114, and its anode is connected to a corresponding second gate line 104. Diodes 122 are driven in the same manner as switching transistors 120 of FIG. 2. As a result, a constant potential difference between the liquid crystal capacitors and the storage capacitors of the non-selected pixel circuits (V _PL -V ₁₀₃ + V _th , where V _PL is the voltage of the second gate line, V ₁₀₃ is the reference voltage, and V _th is maintained at the diode's threshold voltage.

As such, in pixel circuits that are not driven, access is maintained since the constant potential difference (V _PL -V ₁₀₃ + V _th ) is maintained between the liquid crystal capacitors and the storage capacitors in the pixel circuits that are not driven during the partial display mode. Noise generated by off-currents of transistors, leakage currents of liquid crystals, coupling between driven signal lines and undriven signal lines, and the like can be prevented from occurring. As a result, the corresponding pixels of the non-driven pixel circuits can maintain a stable display state (ie, a specific color and gradation).

According to the present invention, in the liquid crystal display device, off-current of the access transistors, leakage current of the liquid crystal, coupling between driven signal lines and undriven signal lines in pixel circuits not driven during the partial display mode. Since it is possible to prevent the generation of noise due to and the like, the pixels of the non-driven pixel circuits can maintain a stable display state (i.e., a specific color and gradation).

Claims (15)

In the liquid crystal display: A plurality of row lines; A plurality of column lines to which image data signals are respectively applied; A plurality of pixel circuits each disposed in a matrix at intersections of the row lines and the column lines; Each of the pixel circuits includes an access transistor connected to a corresponding one of the row lines and a corresponding one of the column lines, a liquid crystal capacitor connected between the access transistor and a reference voltage, the access transistor and the reference. A storage capacitor connected between the voltage and in parallel with the liquid crystal capacitor; And Means for maintaining a constant potential difference between liquid crystal capacitors and storage capacitors of pixel circuits not selected by said row lines during a partial display mode such that text and images are displayed only at certain portions of the screen; Liquid crystal display device. The method of claim 1, The means, A partial display mode controller for generating partial display mode control signals for selectively driving the pixel circuits during the partial display mode; And a plurality of switching transistors respectively connected in parallel with the liquid crystal capacitors between the access transistors of the pixel circuits and the reference voltage and driven by the partial display mode control signals, respectively. The method of claim 2, And the switching transistors of the pixel circuits not selected by the row lines during the partial display mode are turned on by corresponding partial display mode control signals. The method of claim 2, And the switching transistors of the pixel circuits selected by the row lines during the partial display mode are turned off by corresponding partial display mode control signals. The method of claim 2, And all the switching transistors of the pixel circuits are turned off by the partial display mode control signals during the entire display mode of displaying a character or an image on the entire screen. The method of claim 1, The means, A partial display mode controller for generating partial display mode control signals for selectively driving the pixel circuits during the partial display mode; And a plurality of diodes each connected in parallel with liquid crystal capacitors between the access transistors of the pixel circuits and a reference voltage and respectively driven by the partial display mode control signals. The method of claim 6, Diodes of pixel circuits not selected by the row lines during the partial display mode are turned on by corresponding partial display mode control signals. The method of claim 6, And the diodes of the pixel circuits selected by the row lines during the partial display mode are turned off by corresponding partial display mode control signals. The method of claim 6, And all of the diodes of the pixel circuits are turned off by the partial display mode control signals during the entire display mode of displaying a character or an image on the entire screen. In the liquid crystal display: A plurality of first row lines; A plurality of second row lines; A plurality of column lines; A plurality of pixel circuits each disposed in a matrix at intersections of the row lines and the column lines; Each of the pixel circuits includes an access transistor having a current path having one end connected to a corresponding one of the first row lines and a control electrode connected to a corresponding one of the column lines, and the other of the access transistor current path. A liquid crystal capacitor connected between the stage and a predetermined reference voltage, a storage capacitor connected in parallel with the liquid crystal capacitor between the other end of the access transistor current path and the reference voltage, and the other end of the access transistor current path and the reference A switching transistor having a current path connected in parallel with said liquid crystal capacitor between voltages and a control electrode connected with a corresponding one of said second row lines; A partial display mode controller for generating a plurality of partial display mode control signals; A row driver for driving the first and second row lines; The row drivers may be disposed to correspond to the first row lines, respectively, and may be disposed between a plurality of unit row drivers for driving the first row lines, respectively, and a plurality of unit row drivers disposed between a pair of adjacent unit row drivers. Logic gates and a plurality of level shifters connected between the partial display mode control signals and the second row lines, respectively, and converting voltage levels of the partial display mode control signals, wherein the unit row drivers Driving first row lines sequentially; And And a column driver for driving the column lines by applying image data signals to the column lines, respectively. In the liquid crystal display: A plurality of first row lines; A plurality of second row lines; A plurality of column lines; A plurality of pixel circuits each disposed in a matrix at intersections of the row lines and the column lines; Each of the pixel circuits includes an access transistor having a current path having one end connected to a corresponding one of the first row lines and a control electrode connected to a corresponding one of the column lines, and the other of the access transistor current path. A liquid crystal capacitor connected between the stage and a predetermined reference voltage, a storage capacitor connected in parallel with the liquid crystal capacitor between the other end of the access transistor current path and the reference voltage, and the other end of the access transistor current path and the first A diode connected in parallel with said liquid crystal capacitor between a corresponding one of two row lines; A partial display mode controller for generating a plurality of partial display mode control signals; A row driver for driving the first and second row lines; The row drivers may be disposed to correspond to the first row lines, respectively, and may be disposed between a plurality of unit row drivers for driving the first row lines, respectively, and a plurality of unit row drivers disposed between a pair of adjacent unit row drivers. Logic gates and a plurality of level shifters connected between the partial display mode control signals and the second row lines, respectively, and converting voltage levels of the partial display mode control signals, wherein the unit row drivers Driving first row lines sequentially; And And a column driver for driving the column lines by applying image data signals to the column lines, respectively. A plurality of pixel circuits, each pixel circuit comprising an access transistor connected to a corresponding row line, a liquid crystal capacitor connected between the access transistor and a reference voltage, and the liquid crystal between the access transistor and the reference voltage A method of driving a liquid crystal display device having a storage capacitor connected in parallel with the capacitor, the method comprising: A first step of selecting one of a full display mode and a partial display mode; A second step of selectively driving said pixel circuits during said partial display mode; And a third step of maintaining a predetermined potential difference between the liquid crystal capacitors and the storage capacitors of the pixel circuits not driven during the partial display mode. The method of claim 12, And said predetermined potential difference is 0V. The method of claim 12, The third step may include applying a predetermined constant voltage to both ends of the liquid crystal capacitors and the storage capacitors of the non-driven pixel circuits. The method of claim 14, The predetermined constant voltage is a driving method of the liquid crystal display device, characterized in that 5V to 7V.