KR20020000431A - method for manufacturing semiconductor devices - Google Patents

method for manufacturing semiconductor devices Download PDF

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Publication number
KR20020000431A
KR20020000431A KR1020000035235A KR20000035235A KR20020000431A KR 20020000431 A KR20020000431 A KR 20020000431A KR 1020000035235 A KR1020000035235 A KR 1020000035235A KR 20000035235 A KR20000035235 A KR 20000035235A KR 20020000431 A KR20020000431 A KR 20020000431A
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South Korea
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metal
etching
film
oxide film
silicon residue
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KR1020000035235A
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Korean (ko)
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오영묵
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윤종용
삼성전자 주식회사
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Priority to KR1020000035235A priority Critical patent/KR20020000431A/en
Publication of KR20020000431A publication Critical patent/KR20020000431A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32138—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only pre- or post-treatments, e.g. anti-corrosion processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: A method for manufacturing a semiconductor device is provided to improve reliability and to reduce etching damage to an oxide layer when silicon residue is eliminated, by controlling the increase of a leakage current of a high-voltage metal-oxide-semiconductor field-effect-transistor. CONSTITUTION: An oxide layer(20) is formed on a semiconductor substrate(10). A metal layer is formed on the oxide layer. A pattern of an etching mask is formed on the metal layer. The metal layer not masked by the pattern of the etching mask is etched until the oxide layer under the metal layer is exposed so that silicon residue is left on the oxide layer while metal interconnections(35) are separated. The silicon residue is removed while damage to the oxide layer is reduced.

Description

반도체소자의 제조방법{method for manufacturing semiconductor devices}Method for manufacturing semiconductor devices

본 발명은 반도체소자의 제조방법에 관한 것으로, 더욱 상세하게는 실리콘 잔존물을 남기지 않으면서도 후막 금속배선을 형성하여 동작 신뢰성을 향상하도록 한 반도체소자의 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device in which a thick film metal wiring is formed without leaving a silicon residue to improve operation reliability.

일반적으로, 반도체소자의 금속배선을 위한 금속막 증착은 반도체소자 제조공정 중의 한 단계로서 양질의 금속막을 웨이퍼 상에 증착시키는 공정을 말한다. 금속막은 사진식각공정을 거쳐 패턴화하고, 열처리공정을 거쳐 합금화시키면 반도체칩 내에서 각 소자들을 전기적으로 상호 연결하는 역할을 담당하게 된다. 금속막은 고전도도, 양호한 접착력, 실리콘과의 낮은 접촉저항, 고신뢰도의 특성을 갖추어야 하는데 이를 위한 재질로는 순수 알루미늄, 알루미늄 합금, 고융점 금속, 실리사이드, 금(Au) 등이 있다. 알루미늄 합금은 순수 알루미늄(Al)에 1∼2% 실리콘(Si)과 1∼4%의 구리(Cu) 등이 첨가된 것이다. 고융점 금속으로는 텅스텐(W), 몰리브덴(Mo), 티타늄(Ti), 탄탈륨(Ta), 코발트(Co) 등이 있다. 실리사이드로는 텅스텐실리사이드(WSi2), 백금실리사이드(PtSi), 몰리브덴실리사이드(MoSi2), 티타늄실리사이드(TiSi2) 등이 있다.In general, metal film deposition for metal wiring of a semiconductor device refers to a process of depositing a high quality metal film on a wafer as one step of a semiconductor device manufacturing process. When the metal film is patterned through a photolithography process and alloyed through a heat treatment process, the metal film plays a role of electrically interconnecting each device in the semiconductor chip. The metal film should have high conductivity, good adhesion, low contact resistance with silicon, and high reliability. Materials for this purpose include pure aluminum, aluminum alloy, high melting point metal, silicide, and gold (Au). In the aluminum alloy, 1 to 2% silicon (Si), 1 to 4% copper (Cu), or the like is added to pure aluminum (Al). High melting point metals include tungsten (W), molybdenum (Mo), titanium (Ti), tantalum (Ta), and cobalt (Co). Examples of the silicide include tungsten silicide (WSi 2 ), platinum silicide (PtSi), molybdenum silicide (MoSi 2 ), titanium silicide (TiSi 2 ), and the like.

현재, 고전압용 MOSFET과 같은 반도체소자에는 두꺼운 알루미늄합금의 금속배선이 사용되고 있으므로 고전압용 MOSFET의 금속배선을 형성하고 나면 실리콘 잔존물이 남는 식각불량현상이 다발하기 쉽다. 이러한 식각불량현상에 대하여 도 1을 참조하여 설명하면, 소스/드레인영역, 게이트산화막, 게이트전극 등과 같은 단위소자(도시 안됨)를 반도체기판(10)에 형성하고 난 다음에 반도체기판(10) 상에 산화막(20)을 화학기상증착법에 의해 두껍게 적층한다. 이어서 산화막(20) 상에 스퍼터링법이나 진공증착법에 의해 금속막을 두껍게 증착하고, 상기 금속막 상에 금속배선을 형성하기 위한 식각마스크인 감광막(40)의 패턴을 패터닝한다. 그런 다음 감광막(40)의 패턴으로 마스킹되지 않은 부분의 금속막을 그 아래의 산화막(20)이 노출될 때까지 식각함으로써 원하는 금속배선(35)을 분리한다.At present, since a thick aluminum alloy metal wiring is used in a semiconductor device such as a high voltage MOSFET, an etching defect in which silicon residues remain after the metal wiring of the high voltage MOSFET is easily formed. Referring to FIG. 1, the etching defect is formed on the semiconductor substrate 10 after forming unit elements (not shown) such as a source / drain region, a gate oxide film, a gate electrode, and the like on the semiconductor substrate 10. The oxide film 20 is thickly laminated by chemical vapor deposition. Subsequently, a metal film is thickly deposited on the oxide film 20 by sputtering or vacuum deposition, and the pattern of the photosensitive film 40 which is an etching mask for forming metal wiring on the metal film is patterned. Then, the desired metal wiring 35 is separated by etching the metal film of the portion not masked by the pattern of the photosensitive film 40 until the oxide film 20 below it is exposed.

그런데, 종래의 고전압용 금속배선(35)이 30000∼60000Å의 두꺼운 두께로 이루어진다. 또한 금속배선(35)이 99%의 알루미늄에 1%의 실리콘이 고용된 알루미늄합금으로 이루어지는데 이는 순수 알루미늄으로만 이루어진 금속배선이 확산영역에 콘택하는 경우 이들 계면에 스파이크 현상이 발생하는 것을 방지하기 위함이다.By the way, the conventional high voltage metal wiring 35 is made with the thick thickness of 30000-60000 kPa. In addition, the metal wiring 35 is made of an aluminum alloy in which 99% of aluminum and 1% of silicon are dissolved. This prevents the occurrence of spikes at these interfaces when the metal wiring of pure aluminum contacts the diffusion region. For sake.

이로써 종래에는 금속배선(35)을 형성하기 위해 먼저 금속막을 건식식각공정으로 일부 두께만큼 식각하여 금속막을 10000Å의 두께로 줄이고 나면, 알루미늄과 실리콘의 선택 식각비 차이가 크기 때문에 금속막 내의 알루미늄이 식각되더라도 실리콘이 식각되지 않고 미세한 실리콘 잔존물의 형태를 이룬다. 이후 남은 금속막을 습식식각공정으로 그 아래의 산화막(20)이 노출될 때까지 식각하여 금속배선(35)을 분리하고 나면, 산화막(20) 상에 실리콘 잔존물(33)이 매우 큰 사이즈로 남아버린다. 이는 반도체소자의 누설전류를 증가시켜서 동작 신뢰성을 취약하게 만드는 결함으로 작용한다.Accordingly, in order to form the metal wiring 35, the metal film is first etched by a part thickness by a dry etching process to reduce the metal film to a thickness of 10000 kPa. Even though the silicon is not etched, it forms a fine silicon residue. After the remaining metal film is etched by the wet etching process until the oxide film 20 below is exposed, the metal wiring 35 is separated, and the silicon residue 33 remains on the oxide film 20 in a very large size. . This acts as a defect that increases the leakage current of the semiconductor device, making the operation reliability weak.

또한 종래에는 산화막(20) 상의 실리콘 잔존물(33)을 완전히 제거하기 위해 습식식각공정을 장시간 진행하는 경우, 산화막(20)이 상당한 식각손상을 받는다.Also, conventionally, when the wet etching process is performed for a long time to completely remove the silicon residue 33 on the oxide film 20, the oxide film 20 is subjected to considerable etching damage.

따라서 본 발명의 목적은 실리콘 잔존물을 남기지 않으면서도 금속배선을 형성하여 동작 신뢰성을 향상시키도록 한 반도체소자의 제조방법을 제공하는데 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device to improve the operation reliability by forming a metal wiring without leaving a silicon residue.

본 발명의 다른 목적은 실리콘 잔존물을 제거하면서도 금속막의 하지막을 식각 손상으로부터 보호하도록 한 반도체소자의 제조방법을 제공하는데 있다.It is another object of the present invention to provide a method for manufacturing a semiconductor device which removes silicon residue and protects the underlying film of the metal film from etching damage.

도 1은 종래 기술에 의한 반도체소자의 금속배선을 형성한 후에 하지막에 잔존하는 실리콘 잔존물을 나타낸 예시도.1 is an exemplary view showing a silicon residue remaining on a base film after forming a metal wiring of a semiconductor device according to the prior art.

도 2 내지 도 6은 본 발명에 의한 반도체소자의 제조방법을 나타낸 공정도.2 to 6 is a process chart showing a manufacturing method of a semiconductor device according to the present invention.

이와 같은 목적을 달성하기 위한 본 발명에 의한 반도체소자의 제조방법은The semiconductor device manufacturing method according to the present invention for achieving the above object is

반도체기판 상에 산화막을 형성하는 단계;Forming an oxide film on the semiconductor substrate;

상기 산화막 상에 금속막을 형성하는 단계;Forming a metal film on the oxide film;

상기 금속막 상에 식각마스크의 패턴을 형성하는 단계;Forming a pattern of an etching mask on the metal layer;

상기 식각마스크의 패턴으로 마스킹되지 않은 금속막을 그 아래의 산화막이 노출될 때까지 식각하여 금속배선들을 분리하면서 상기 산화막 상에 실리콘 잔존물을 남기는 단계; 그리고Etching the metal film, which is not masked with the pattern of the etching mask, until the oxide film below is exposed to separate the metal wires, leaving silicon residue on the oxide film; And

상기 산화막의 식각손상을 줄이면서 상기 실리콘 잔존물을 제거하는 단계를 포함하는 것을 특징으로 한다.And removing the silicon residue while reducing the etch damage of the oxide film.

바람직하게는 실리콘 잔존물을 제거하는 단계에서 건식식각공정을 적용한다. 또한 사이드 에칭 특성을 갖는 SF6가스를 주 식각가스로 사용하고 He 가스를 분위기 가스로 사용하고, SF6가스를 25∼200SCCM의 범위에서 공급할 수 있다. 실리콘 잔존물과 산화막의 식각선택비를 30:1 이상으로 유지함으로써 산화막의 식각손상을 줄여줄 수 있다.Preferably, a dry etching process is applied in the step of removing the silicon residue. In addition, SF 6 gas having side etching characteristics can be used as the main etching gas, He gas is used as the atmosphere gas, and SF 6 gas can be supplied in the range of 25 to 200 SCCM. By maintaining the etching selectivity of the silicon residue and the oxide layer of 30: 1 or more can reduce the etching damage of the oxide layer.

따라서 본 발명은 고전압 MOSFET의 금속배선을 형성하고 나더라도 실리콘 잔존물을 남기지 않고 더욱이 하지막인 산화막을 식각손상으로부터 보호하여 누설전류를 줄이고 나아가 동작 신뢰성을 향상시킬 수 있다.Therefore, the present invention can reduce the leakage current and further improve the operation reliability by protecting the underlying oxide film from etching damage without leaving silicon residue even after forming the metal wiring of the high voltage MOSFET.

이하, 본 발명에 의한 반도체소자의 제조방법을 첨부된 도면을 참조하여 상세히 설명하기로 한다. 도면에서 종래의 부분과 동일 구조 및 동일 작용의 부분에는 동일 부호를 부여한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the drawings, the same reference numerals are assigned to the same structures and parts of the same operation as the conventional parts.

도 2 내지 도 6은 본 발명에 의한 반도체소자의 제조방법을 나타낸 공정도이다. 도 2를 참조하면, 먼저, 반도체기판(10) 상에 하지막인 산화막(20)을 화학기상증착공정에 의해 두껍게 적층한다. 여기서, 설명의 편의상 본 발명의 요지에 관련성이 적으므로 설명의 이해를 돕기 위하여 도면에 도시하지 않았으나 반도체기판의 액티브영역들을 전기적으로 분리하기 위해 반도체기판의 필드영역에 예를 들어 LOCOS(local oxidation of silicon) 공정에 의해 아이솔레이션층을 형성하고, 반도체기판의 액티브영역들 상에 MOSFET의 게이트산화막을 열산화공정에 의해 성장시키고 그 위에 게이트전극을 위한 도전층, 예를 들어 고농도의 다결정실리콘층을 적층한 후 사진식각공정에 의해 상기 도전층을 게이트전극의 패턴으로 형성하고, 게이트전극의 패턴을 사이에 두고 반도체기판의 액티브영역에 소스/드레인영역을 형성하는 것은 자명한 사실이다.2 to 6 are process charts showing a method of manufacturing a semiconductor device according to the present invention. Referring to FIG. 2, first, an oxide film 20 serving as a base film is thickly stacked on a semiconductor substrate 10 by a chemical vapor deposition process. Here, for convenience of explanation, since it is less relevant to the gist of the present invention, although not shown in the drawings for the purpose of understanding, for example, LOCOS (local oxidation of an isolation layer is formed, and a gate oxide film of a MOSFET is grown by thermal oxidation on active regions of a semiconductor substrate, and a conductive layer for a gate electrode, for example, a high concentration polycrystalline silicon layer is deposited thereon. After that, it is obvious that the conductive layer is formed into a pattern of a gate electrode by a photolithography process, and a source / drain region is formed in an active region of the semiconductor substrate with the pattern of the gate electrode interposed therebetween.

산화막(20)의 적층이 완료되고 나면, 산화막(20) 상에 스퍼터링공정이나 진공증착공정에 의해 금속막(30)을 고전압 MOSFET의 금속배선으로서 적합한 두께, 예를 들어 30000∼60000Å의 두꺼운 두께로 적층한다. 여기서, 금속막(30)은 99%의 알루미늄에 1%의 실리콘이 고용된 알루미늄합금으로 이루어지는데 이는 순수 알루미늄으로만 이루어진 금속배선이 확산영역에 콘택하는 경우 이들 계면에 스파이크 현상이 발생하는 것을 방지하기 위함이다.After the deposition of the oxide film 20 is completed, the metal film 30 is formed on the oxide film 20 by a sputtering process or a vacuum deposition process to a thickness suitable for metal wiring of a high voltage MOSFET, for example, a thick thickness of 30000 to 60000 kPa. Laminated. Here, the metal film 30 is made of an aluminum alloy in which 1% of silicon is dissolved in 99% of aluminum, which prevents spikes on these interfaces when a metal wiring made of pure aluminum contacts the diffusion region. To do this.

금속막(30)의 적층이 완료되고 나면, 사진공정을 이용하여 금속막(30) 상에 금속배선을 형성하기 위한 식각마스크로서 감광막(40)의 패턴을 형성한다.After the lamination of the metal film 30 is completed, a pattern of the photosensitive film 40 is formed as an etching mask for forming metal wiring on the metal film 30 by using a photographic process.

도 3을 참조하면, 감광막(40)의 패턴이 완성되고 나면, 감광막(40)의 패턴을 마스크로 이용하여 금속막(30)의 노출된 부분을 예를 들어 10000Å의 두께만 남기고 제 1 건식식각공정으로 제거한다. 제 1 건식식각공정에서는 Cl2가스와 BCl3가스를 혼합한 식각가스가 사용된다. 이때, 알루미늄과 실리콘의 식각선택비 차이가 크므로 식각되고 남은 금속막(30) 상에 작은 사이즈의 실리콘 잔존물(31)이 남는다. 실리콘 잔존물(31)의 높이가 100∼500Å이고, 넓이가 100∼300Å이며 그 형태가 일정하지 않고 부정형으로 존재한다.Referring to FIG. 3, after the pattern of the photoresist film 40 is completed, the first dry etching is performed using the pattern of the photoresist film 40 as a mask, for example, leaving the exposed portion of the metal film 30 with a thickness of 10000 μs. Removed by process. In the first dry etching process, an etching gas obtained by mixing Cl 2 gas and BCl 3 gas is used. At this time, since the difference in etching selectivity between aluminum and silicon is large, silicon residues 31 having a small size remain on the etched metal layer 30. The height of the silicon residue 31 is 100-500 mV, the width is 100-300 mV, and the form is not constant but exists in indeterminate form.

도 4를 참조하면, 금속막(30)의 제 1 건식식각공정이 완료되고 나면, 감광막(40)의 패턴을 마스크로 이용하여 남은 금속막(30)을 그 아래의 산화막(20)이 노출될 때까지 습식식각하여 각각의 금속배선(35)으로 분리한다. 여기서, 습식식각공정은 알루미늄과 실리콘의 식각선택비가 큰 특성을 갖고 있기 때문에 산화막(20) 상에 큰 사이즈의 실리콘 잔존물(33)이 남는다. 심한 경우에는 실리콘 잔존물(31)의 높이가 10000∼15000Å이고, 넓이가 300∼1000Å이며 그 형태가 일정하지 않고 부정형으로 존재한다. 실리콘 잔존물(33)은 누설전류 증가와 같은 불량현상을 일으킬 수 있는 결함으로서 작용한다.Referring to FIG. 4, after the first dry etching process of the metal film 30 is completed, the oxide film 20 below the exposed metal film 30 is exposed using the pattern of the photosensitive film 40 as a mask. Wet etch until separated into metal wires (35). Here, in the wet etching process, since the etching selectivity of aluminum and silicon has a large characteristic, a large sized silicon residue 33 remains on the oxide film 20. In severe cases, the height of the silicon residue 31 is 10000 to 15000 mm, the width is 300 to 1000 mm 3, and the shape is not constant and exists in an irregular shape. The silicon residue 33 serves as a defect that can cause a defect phenomenon such as an increase in leakage current.

통상적으로 금속막(30)을 제 1 건식식각공정과 습식식각공정으로 구분하여 실시하는데 이는 금속막(30)을 한번에 걸쳐 습식식각공정하는 경우, 금속막(30)의사이드 에칭이 크게 발생하기 때문이다.Typically, the metal film 30 is divided into a first dry etching process and a wet etching process, because when the wet etching process of the metal film 30 is performed at once, the side etching of the metal film 30 is large. to be.

도 5를 참조하면, 금속배선(35)의 분리가 완료되고 나면, 감광막(40)의 패턴을 마스크로 이용하여 산화막(20) 상의 실리콘 잔존물(33)을 제 2 건식식각공정으로 완전히 제거한다. 여기서, 제 2 건식식각공정에서는 사이드 에칭 특성을 갖는 SF6가스를 주 식각가스로 사용하고 He 가스를 분위기 가스로 사용한다. 바람직하게는 SF6가스를 25∼200SCCM의 범위에서 공급하되 적당한 식각속도와 균일도(uniformity)를 얻을 수 있는 조건에 맞추어 가스 유량을 결정한다. 더욱이 실리콘 잔존물(33)과 산화막(20)의 식각선택비가 30:1 이상으로 크므로 산화막(20)의 식각손상을 작게 줄이면서도 실리콘 잔존물(33)을 완전히 제거할 수 있다.Referring to FIG. 5, after the separation of the metal wiring 35 is completed, the silicon residue 33 on the oxide film 20 is completely removed by the second dry etching process by using the pattern of the photosensitive film 40 as a mask. Here, in the second dry etching process, SF 6 gas having side etching characteristics is used as the main etching gas, and He gas is used as the atmosphere gas. Preferably, the SF 6 gas is supplied in the range of 25 to 200 SCCM, and the gas flow rate is determined according to the conditions for obtaining an appropriate etching rate and uniformity. Furthermore, since the etching selectivity of the silicon residue 33 and the oxide film 20 is greater than 30: 1, the silicon residue 33 can be completely removed while reducing the etching damage of the oxide film 20.

따라서 본 발명은 금속배선(35)을 분리하고 난 후에 산화막(20) 상에 실리콘 잔존물을 전혀 남기지 않으므로써 누설전류를 저감할 수 있고 나아가 동작 신뢰성을 향상시킬 수 있다.Therefore, the present invention can reduce the leakage current and further improve the operation reliability by leaving no silicon residue on the oxide film 20 after separating the metal wiring 35.

도 6을 참조하면, 실리콘 잔존물(33)의 제거가 완료되고 나면, 감광막(40)의 패턴을 스트립공정에 의해 완전히 제거하여 금속배선(35)을 노출시킴으로써 본 발명의 공정을 완료한다.Referring to FIG. 6, after the removal of the silicon residue 33 is completed, the process of the present invention is completed by completely removing the pattern of the photoresist film 40 by the strip process to expose the metal wiring 35.

이상에서 살펴본 바와 같이, 본 발명에 의한 반도체소자의 제조방법에서는 반도체기판 상에 산화막을 적층하고 그 위에 고전압용 MOSFET의 금속배선을 위한 금속막을 두껍께 적층한 후 금속막을 사진식각공정에 의해 금속배선으로 분리하면서 산화막 상에 실리콘 잔존물을 남긴다. 그런 다음에 사이드 에칭 특성을 갖는 SF6의 공정가스를 이용하고 실리콘 잔존물과 산화막의 식각선택비를 30:1 이상으로 하는 건식식각공정을 이용하여 실리콘 잔존물을 제거한다.As described above, in the method of manufacturing a semiconductor device according to the present invention, an oxide film is laminated on a semiconductor substrate, and a metal film for metal wiring of a high voltage MOSFET is laminated thereon, and then the metal film is metallized by a photolithography process. The silicon residue is left on the oxide film while being separated. Then, the silicon residue is removed by using a process gas of SF 6 having side etching characteristics and using a dry etching process in which the etching selectivity of the silicon residue and the oxide film is 30: 1 or more.

따라서 본 발명은 고전압용 MOSFET의 누설전류 증대를 억제하여 소자의 동작 신뢰성을 향상할 수 있다. 또한 실리콘 잔존물의 제거할 때 산화막의 식각손상을 줄여줄 수 있다.Therefore, the present invention can suppress the increase of the leakage current of the high-voltage MOSFET to improve the operation reliability of the device. In addition, the etching damage of the oxide layer can be reduced when removing the silicon residue.

한편, 본 발명은 도시된 도면과 상세한 설명에 기술된 내용에 한정하지 않으며 본 발명의 사상을 벗어나지 않는 범위 내에서 다양한 형태의 변형도 가능함은 이 분야에 통상의 지식을 가진 자에게는 자명한 사실이다.On the other hand, the present invention is not limited to the contents described in the drawings and detailed description, it is obvious to those skilled in the art that various modifications can be made without departing from the spirit of the invention. .

Claims (3)

반도체기판 상에 산화막을 형성하는 단계;Forming an oxide film on the semiconductor substrate; 상기 산화막 상에 금속막을 형성하는 단계;Forming a metal film on the oxide film; 상기 금속막 상에 식각마스크의 패턴을 형성하는 단계;Forming a pattern of an etching mask on the metal layer; 상기 식각마스크의 패턴으로 마스킹되지 않은 금속막을 그 아래의 산화막이 노출될 때까지 식각하여 금속배선들을 분리하면서 상기 산화막 상에 실리콘 잔존물을 남기는 단계; 그리고Etching the metal film, which is not masked with the pattern of the etching mask, until the oxide film below is exposed to separate the metal wires, leaving silicon residue on the oxide film; And 상기 산화막의 식각손상을 줄이면서 상기 실리콘 잔존물을 제거하는 단계를 포함하는 반도체소자의 제조방법.Removing the silicon residue while reducing the etching damage of the oxide film. 제 1 항에 있어서, 상기 실리콘 잔존물을 건식식각공정으로 제거하는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the silicon residue is removed by a dry etching process. 제 1 항에 있어서, 상기 건식식각공정에서 상기 실리콘 잔존물과 상기 산화막의 식각선택비를 30:1 이상으로 하는 것을 특징으로 하는 반도체소자의 제조방법.The method of claim 1, wherein the etching selectivity of the silicon residue and the oxide layer is 30: 1 or more in the dry etching process.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101038943B1 (en) * 2011-01-27 2011-06-03 주식회사 태조엔지니어링 A turnel which has absorbing vibration of ground

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101038943B1 (en) * 2011-01-27 2011-06-03 주식회사 태조엔지니어링 A turnel which has absorbing vibration of ground

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