KR200177306Y1 - Shield assembly for semiconductor sputtering apparatus - Google Patents
Shield assembly for semiconductor sputtering apparatus Download PDFInfo
- Publication number
- KR200177306Y1 KR200177306Y1 KR2019970027308U KR19970027308U KR200177306Y1 KR 200177306 Y1 KR200177306 Y1 KR 200177306Y1 KR 2019970027308 U KR2019970027308 U KR 2019970027308U KR 19970027308 U KR19970027308 U KR 19970027308U KR 200177306 Y1 KR200177306 Y1 KR 200177306Y1
- Authority
- KR
- South Korea
- Prior art keywords
- shell assembly
- semiconductor wafer
- sputtering apparatus
- wafer
- target
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/34—Gas-filled discharge tubes operating with cathodic sputtering
- H01J37/3411—Constructional aspects of the reactor
- H01J37/3441—Dark space shields
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/54—Controlling or regulating the coating process
- C23C14/542—Controlling the film thickness or evaporation rate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/34—Gas-filled discharge tubes operating with cathodic sputtering
- H01J37/3464—Operating strategies
- H01J37/347—Thickness uniformity of coated layers or desired profile of target erosion
Landscapes
- Chemical & Material Sciences (AREA)
- Engineering & Computer Science (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Analytical Chemistry (AREA)
- Physical Vapour Deposition (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
Abstract
본 고안은 반도체 웨이퍼 세라믹 스퍼터링장치의 쉘드어셈블리구조에 관한 것으로, 종래에는 쉘드어셈블리의 내측면에 스퍼터링되는 입자가 증착되어 웨이퍼의 에지부분에 증착량의 감소를 초래함으로써, 증착두께 유니퍼머티가 저하되는 문제점이 있었다. 본 고안 반도체 웨이퍼 세라믹 스퍼터링장치의 쉘드어셈블리구조는 쉘드어셈블리(12)의 내측면(12a) 중앙을 상,하단부 보다 넓게 형성하여, 플라즈마 포텐셜을 낮춤과 동시에 증착두께 유니퍼머티를 향상시키는 효과가 있다.The present invention relates to a shell assembly structure of a semiconductor wafer ceramic sputtering apparatus. In the related art, the sputtered particles are deposited on the inner surface of the shell assembly, thereby reducing the deposition amount on the edge of the wafer, thereby reducing the deposition thickness uniformity. There was a problem. The shell assembly structure of the semiconductor wafer ceramic sputtering device of the present invention has an effect of forming the center of the inner surface 12a of the shell assembly 12 wider than the upper and lower ends, thereby lowering the plasma potential and improving the deposition thickness uniformity. .
Description
본 고안은 반도체 웨이퍼 세라믹 스퍼터링장치의 쉘드어셈블리구조에 관한 것으로, 특히 그라운드로 사용되는 쉘드의 면적을 넓혀서 웨이퍼의 품질불량을 방지함과 동시에 웨이퍼의 증착두께 우니퍼머티를 향상시키도록 하는데 적합한 반도체 웨이퍼 세라믹 스퍼터링장치의 쉘드어셈블리구조에 관한 것이다.The present invention relates to a shell assembly structure of a semiconductor wafer ceramic sputtering apparatus. In particular, the semiconductor wafer is suitable for increasing the area of the shell used as the ground to prevent wafer defects and at the same time improving the deposition thickness of the wafer. A shell assembly structure of a ceramic sputtering apparatus.
일반적으로 반도체 웨이퍼 제조공정 중 캐패시터를 제조하기 위하여 유전율이 높은 BST(BaSrTiO2)막을 스퍼터링증착장치에서 증착하게 되는데, 이와 같은 증착공정을 진행하기 위한 증착장치를 제작하는데 있어서, 타겟의 크기에 비하여 그라운드의 면적을 크게 설정하는 것은 플라즈마의 포텐셜을 낮출 수 있기 때문에 매우 중요하며, 이와 같이 제작된 스퍼터링증착장치가 도 1에 도시되어 있는 바, 이를 간단히 설명하면 다음과 같다.In general, a high dielectric constant BST (BaSrTiO 2 ) film is deposited in a sputtering deposition apparatus to manufacture a capacitor during a semiconductor wafer manufacturing process. It is very important to set a large area of the plasma because the potential of the plasma can be lowered, and the sputtering deposition apparatus manufactured as described above is illustrated in FIG. 1.
도 1은 종래 반도체 웨이퍼 스퍼터링장치의 내측 구성을 개략적으로 보인 단면도로써, 도시된 바와 같이, 종래에는 챔버의 내측 상부에 음극이 됨과 동시 모재가 되는 타겟(TARGET)(1)이 설치되어 있고, 그 타겟(1)의 하부 외측으로는 양극이 됨과 동시에 그라운드가 되는 쉘드어셈블리(2)가 설치되어 있으며, 그 쉘드어셈블리(2)의 하측에는 서셉터에 장착된 웨이퍼(3)가 설치되어 있다.FIG. 1 is a cross-sectional view schematically showing the inner structure of a conventional semiconductor wafer sputtering apparatus. As shown in the drawing, a target TARGET 1 serving as a cathode and a base material is provided on an inner upper portion of a chamber. The shell assembly 2 which becomes an anode and becomes a ground is provided in the lower outer side of the target 1, and the wafer 3 attached to the susceptor is provided in the lower side of the shell assembly 2. As shown in FIG.
상기와 같이 구성되어 있는 종래 반도체 스퍼터링증착장비는 서셉터의 상면에 웨이퍼(2)를 장착하고, 챔버의 내측온도를 500∼650℃로 가열한 상태에서 아르곤 , 산소 등의 공정가스를 챔버의 내측으로 주입하며, 상기 타겟(1)으로 전원을 인가하면 챔버의 내부에 플라즈마가 형성되어 아르곤 이온이 BST재질인 타겟(1)에 충돌하여 원자가 방출되고, 이것이 웨이퍼(3)의 상면에 부착하게 된다.Conventional semiconductor sputtering deposition equipment configured as described above is equipped with a wafer (2) on the upper surface of the susceptor, the process gas such as argon, oxygen, etc. in the state of heating the inner temperature of the chamber to 500 ~ 650 ℃ inside the chamber When the power is applied to the target 1, plasma is formed inside the chamber, and argon ions collide with the target 1, which is a BST material, to release atoms, which are attached to the upper surface of the wafer 3. .
그러나, 타겟(1)에서 스퍼터링되어 튀어나오는 입자들이 5mTorr의 낮은 압력에도 불구하고, 전적으로 직진성을 따르기 보다는 상당량이 아르곤 가스와 충돌산란을 일으키며 퍼져서 쉘드어셈블리(2)의 내측면에 부착되어 증착양의 감소를 초래하고, 이와 같은 증착양의 감소는 웨이퍼(3)의 중앙 보다 쉘드어셈블리(2)가 근접하게 설치된 에지부분에 심하게 일어나서 증착두께 유니퍼머티가 저하되는 문제점이 있었다.However, despite the low pressure of 5 mTorr, sputtered and protruding particles from the target (1), rather than following the straightness entirely, they spread and collide with the argon gas, causing them to adhere to the inner side of the shell assembly (2), thereby increasing the amount of deposition. The decrease in deposition amount is caused to occur at the edge portion where the shell assembly 2 is located closer than the center of the wafer 3, so that the deposition thickness uniformity is lowered.
상기와 같은 문제점을 감안하여 안출한 본 고안의 목적은 플라즈마 포텐셜을 낮춤과 동시에 증착두께 유니퍼머티를 향상시키도록 하는데 적합한 반도체 웨이퍼 세라믹 스퍼터링장치의 쉘드어셈블리구조를 제공함에 있다.An object of the present invention devised in view of the above problems is to provide a shell assembly structure of a semiconductor wafer ceramic sputtering apparatus suitable for lowering plasma potential and improving deposition thickness uniformity.
도 1은 종래 반도체 웨이퍼 스퍼터링장치의 내측 구성을 개략적으로 보인 단면도.1 is a cross-sectional view schematically showing the inner structure of a conventional semiconductor wafer sputtering apparatus.
도 2는 본 고안 반도체 웨이퍼 스퍼터링장치의 내측 구성을 개략적으로 보인 단면도.Figure 2 is a schematic cross-sectional view showing the inner structure of the semiconductor wafer sputtering device of the present invention.
* * 도면의 주요 부분에 대한 부호의 설명 * ** * Explanation of symbols for the main parts of the drawing * *
11 : 타겟 12 : 쉘드어셈블리11: target 12: shell assembly
12a : 내측면 13 : 웨이퍼12a: inner side 13: wafer
상기와 같은 본 고안의 목적을 달성하기 위하여 타겟의 하부에 쉘드어셈블리가 설치되어 있고, 그 쉘드어셈블리의 하부에 웨이퍼가 장착되는 서셉터가 설치되어 있는 반도체 웨이퍼 세라믹 스퍼터링장치에 있어서, 상기 쉘드어셈블리의 내측면 중앙에 상하단부 보다 넓게 항아리형상으로 형성된 것을 특징으로 하는 반도체 웨이퍼 세라믹 스퍼터링장치의 쉘드어셈블리구조가 제공된다.In order to achieve the object of the present invention as described above, the shell assembly is provided in the lower portion of the target, the semiconductor wafer ceramic sputtering device is provided with a susceptor is mounted on the lower portion of the shell assembly, the shell assembly Provided is a shell assembly structure of a semiconductor wafer ceramic sputtering apparatus, characterized in that it is formed in a jar shape at a center on an inner side of a surface thereof.
이하, 상기와 같이 구성되는 본 고안 반도체 웨이퍼 세라믹 스퍼터링장치의 쉘드어셈블리구조를 첨부된 도면의 실시예를 참고하여 보다 상세히 설명하면 다음과 같다.Hereinafter, the shell assembly structure of the inventive semiconductor wafer ceramic sputtering device configured as described above will be described in more detail with reference to an embodiment of the accompanying drawings.
도 2는 본 고안 반도체 웨이퍼 스퍼터링장치의 내측 구성을 개략적으로 보인 단면도로써, 도시된 바와 같이, 본 발명이 구비된 반도체 웨이퍼 세라믹 스퍼터링장치는 챔버의 내측 상부에 음극이 됨과 동시 모재가 되는 타겟(TARGET)(11)이 설치되어 있고, 그 타겟(11)의 하부 외측으로는 양극이 됨과 동시에 그라운드가 되는 쉘드어셈블리(12)가 설치되어 있으며, 그 쉘드어셈블리(12)의 하측에는 서셉터에 장착된 웨이퍼(13)가 설치되어 있는 구성은 종래와 유사하다.FIG. 2 is a cross-sectional view schematically illustrating an internal configuration of a semiconductor wafer sputtering device of the present invention. As shown in the drawing, a semiconductor wafer ceramic sputtering device equipped with the present invention has a target which becomes a cathode and a base material at the same time as a cathode on an inner upper portion of a chamber. 11 is provided, and the shell assembly 12 which becomes an anode and becomes a ground at the lower outer side of the target 11 is installed, and is mounted to the susceptor below the shell assembly 12. The structure in which the wafer 13 is provided is similar to the conventional one.
여기서, 상기 쉘드어셈블리(12)의 내측면(12a) 중앙을 상하단부 보다 넓게 항아리형상으로 형성하여서 구성된다.Here, the center of the inner surface (12a) of the shell assembly 12 is formed by forming a jar shape wider than the upper and lower ends.
즉, 쉘드어셈블리(12)의 면적을 넓게 형성하여 알에프 플라즈마의 포텐셜을 정상화시키면서 쉘드어셈블리(12)의 중앙부를 상.하단부 보다 넓게 형성하여 스퍼터링되는 입자들이 쉘드어셈블리(12)의 내측면에 증착되어 웨이퍼(13)의 에지부분에 증착량감소를 초래하는 것을 방지하도록 하였다.That is, while forming the wide area of the shell assembly 12 to normalize the potential of the RF plasma, while forming the central portion of the shell assembly 12 wider than the upper and lower ends, sputtered particles are deposited on the inner surface of the shell assembly 12 It was made to prevent the deposition amount from being reduced at the edge portion of the wafer 13.
상기와 같이 구성되어 있는 본 고안 쉘드어셈블리구조가 형성된 반도체 웨이퍼 세라믹 스퍼터링장치의 동작은 종래와 유사하다.The operation of the semiconductor wafer ceramic sputtering device in which the inventive shell assembly structure is constructed as described above is similar to the conventional one.
즉, 서셉터의 상면에 웨이퍼(13)를 장착하고, 챔버의 내측온도를 500∼650℃로 가열한 상태에서 아르곤 , 산소 등의 공정가스를 챔버의 내측으로 주입하며, 상기 타겟(11)으로 전원을 인가하면 챔버의 내부에 플라즈마가 형성되어 아르곤 이온이 BST재질인 타겟(11)에 충돌하여 원자가 방출되고, 이것이 웨이퍼(13)의 상면에 부착하게 되는데, 이때 본 고안에서는 타겟(11)의 면적에 비하여 쉘드어셈블리(12)의 면적이 충분히 넓게 형성되어 있으므로 플라즈마 포텐셜이 낮게 형성되고, 또한 쉘드어셈블리(12)의 중앙부를 항아리 모양으로 넓게 형성함으로써 스퍼터링되는 입자들이 쉘드어셈블리(12)의 내측면에 증착되지 않도록 되어 있다.That is, the wafer 13 is mounted on the upper surface of the susceptor, and a process gas such as argon or oxygen is injected into the chamber while the inner temperature of the chamber is heated to 500 to 650 ° C. When the power is applied, a plasma is formed inside the chamber, and argon ions collide with the target 11 made of BST material, and atoms are released, which is attached to the upper surface of the wafer 13. Since the area of the shell assembly 12 is sufficiently wide compared to the area, the plasma potential is low, and the sputtered particles are formed on the inner surface of the shell assembly 12 by forming the center portion of the shell assembly 12 in a jar shape. It is not to be deposited on the.
이상에서 상세히 설명한 바와 같이 본 고안 반도체 웨이퍼 세라믹 스퍼터링장치의 쉘드어셈블리구조는 쉘드어셈블리의 내측면 중앙을 상,하단부 보다 넓게 형성하여, 플라즈마 포텐셜을 낮춤과 동시에 증착두께 유니퍼머티를 향상시키는 효과가 있다.As described in detail above, the shell assembly structure of the semiconductor wafer ceramic sputtering device of the present invention has the effect of improving the deposition thickness uniformity while lowering the plasma potential by forming the center of the inner surface of the shell assembly wider than the upper and lower ends. .
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970027308U KR200177306Y1 (en) | 1997-09-30 | 1997-09-30 | Shield assembly for semiconductor sputtering apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019970027308U KR200177306Y1 (en) | 1997-09-30 | 1997-09-30 | Shield assembly for semiconductor sputtering apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR19990013991U KR19990013991U (en) | 1999-04-26 |
| KR200177306Y1 true KR200177306Y1 (en) | 2000-05-01 |
Family
ID=19511196
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR2019970027308U KR200177306Y1 (en) | 1997-09-30 | 1997-09-30 | Shield assembly for semiconductor sputtering apparatus |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR200177306Y1 (en) |
-
1997
- 1997-09-30 KR KR2019970027308U patent/KR200177306Y1/en not_active IP Right Cessation
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990013991U (en) | 1999-04-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4362611A (en) | Quadrupole R.F. sputtering system having an anode/cathode shield and a floating target shield | |
| US3661761A (en) | Rf sputtering apparatus for promoting resputtering of film during deposition | |
| US20020187647A1 (en) | Stepped upper electrode for plasma processing uniformity | |
| US6214184B1 (en) | Insulated wafer pedestal | |
| JP2000342958A (en) | Plasma apparatus and method for manufacturing shielding plate therefor | |
| EP0326531B1 (en) | Improved rf plasma processing apparatus | |
| US6030509A (en) | Apparatus and method for shielding a wafer holder | |
| CA1192672A (en) | Method of producing positive slope step changes on vacuum deposited layers | |
| KR200177306Y1 (en) | Shield assembly for semiconductor sputtering apparatus | |
| US4153528A (en) | Contoured quartz anode plate | |
| KR101870051B1 (en) | Parts for plasma processing apparatus having tungsten carbide bulk | |
| KR20050091854A (en) | Focus ring of semiconductor wafer manufacturing device | |
| KR20010089674A (en) | Physical vapor deposition of semiconducting and insulating materials | |
| JPS6383257A (en) | Sputtering device | |
| KR100672629B1 (en) | Sputtering device | |
| KR200266553Y1 (en) | preventing structure for arcing of sputterring device for manufacturing LCD | |
| CN212925157U (en) | 8-inch physical vapor deposition tantalum cavity heating base protection accessory | |
| KR100458294B1 (en) | Method for forming barrier metal layer of semiconductor device to form stable contact | |
| KR102039799B1 (en) | Parts for plasma processing apparatus having tungsten oxide bulk | |
| KR100480572B1 (en) | Metalization method using aluminium | |
| KR0125868Y1 (en) | Separable out-target structure of metal evaporator | |
| US20020162739A1 (en) | Cathodic sputtering chamber for applying material to the surface of a semiconductor wafer located therein | |
| KR0134539Y1 (en) | Shield in chamber for producing metal thin film on semiconductor | |
| JPH09266201A (en) | Plasma cvd apparatus | |
| KR20010039233A (en) | Apparatus for etching wafer in semiconductor sputtering system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A201 | Request for examination | ||
| E701 | Decision to grant or registration of patent right | ||
| REGI | Registration of establishment | ||
| FPAY | Annual fee payment |
Payment date: 20101224 Year of fee payment: 12 |
|
| LAPS | Lapse due to unpaid annual fee |