KR200159477Y1 - Tft lcd - Google Patents
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- KR200159477Y1 KR200159477Y1 KR2019940003233U KR19940003233U KR200159477Y1 KR 200159477 Y1 KR200159477 Y1 KR 200159477Y1 KR 2019940003233 U KR2019940003233 U KR 2019940003233U KR 19940003233 U KR19940003233 U KR 19940003233U KR 200159477 Y1 KR200159477 Y1 KR 200159477Y1
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- South Korea
- Prior art keywords
- thin film
- film transistor
- gate electrode
- gate
- etch stopper
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- 239000010409 thin film Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000010408 film Substances 0.000 claims abstract description 8
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 7
- 238000000034 method Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000000368 destabilizing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000001052 transient effect Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2201/00—Constructional arrangements not provided for in groups G02F1/00 - G02F7/00
- G02F2201/40—Arrangements for improving the aperture ratio
Abstract
본 고안은 액정표시소자용 박막트랜지스터에 관한 것으로, 액정표시소자용 박막트랜지스터의 개구율 및 플릭커 특성을 향상시키기 위한 것이다.The present invention relates to a thin film transistor for a liquid crystal display device, and to improve the aperture ratio and flicker characteristics of the thin film transistor for a liquid crystal display device.
본 고안은 절연기판과, 상기 절연기판 상부에 형성된 게이트전극, 상기 게이트전극이 형성된 절연기판 전면에 형성된 게이트절연막, 상기 게이트절연막 상부에 상기 게이트전극보다 넓은 폭을 가지며 형성된 절연층패턴, 상기 게이트전극 상부의 상기 절연층패턴 소정영역에 형성된 콘택홀, 상기 콘택홀 상부에 섬모양의 형태를 가지고 형성된 활성층, 상기 활성층 상부에 형성된 소오스 및 드레인 전극을 포함하여 이루어진 액정표시소자용 박막트랜지스터를 제공한다.The present invention provides an insulating substrate, a gate electrode formed on the insulating substrate, a gate insulating film formed on the entire surface of the insulating substrate on which the gate electrode is formed, an insulating layer pattern formed on the gate insulating film and having a wider width than the gate electrode, and the gate electrode. Provided is a thin film transistor for a liquid crystal display device comprising a contact hole formed in an upper portion of the insulating layer pattern, an active layer formed in an island shape on the contact hole, and a source and a drain electrode formed on the active layer.
Description
제1a도~제1d도는 종래의 에치스토퍼형 박막트랜지스터의 공정을 설명하기 위한 레이아웃도.1A to 1D are layout diagrams for explaining the steps of a conventional etch stopper type thin film transistor.
제2도는 종래의 에치스토퍼형 박막트랜지스터 단면구조도.2 is a cross-sectional view of a conventional etch stopper type thin film transistor.
제3a도~제3d도는 본 고안의 에치스토퍼형 박막트랜지스터 공정을 설명하기 위한 레이아웃도.3a to 3d are layout views for explaining the etch stopper type thin film transistor process of the present invention.
제4도는 본 고안의 에치스토퍼형 박막트랜지스터 단면구조도.4 is a cross-sectional view of an etch stopper type thin film transistor of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
10 : 절연기판 11 : 게이트전극10: insulating substrate 11: gate electrode
12 : 게이트절연막 13 : 에치스토퍼12 gate insulating film 13 etch stopper
13A : 콘택홀 14 : 활성층13A: contact hole 14: active layer
14a : 오믹접촉층 15 : 소오스 및 드레인전극14a: ohmic contact layer 15: source and drain electrodes
본 고안은 액정표시소자용 박막트랜지스터에 관한 것으로, 특히 액정표시소자용 박막트랜지스터 어레이 설계에 관한 것이다.The present invention relates to a thin film transistor for a liquid crystal display device, and more particularly to a thin film transistor array design for a liquid crystal display device.
종래의 에치스토퍼(Etch stopper)형 박막트랜지스터를 설명하면 다음과 같다.A conventional etch stopper type thin film transistor is described as follows.
제1a도~제1d도는 종래의 에치스토퍼형 박막트랜지스터의 공정을 설명하기 위한 레이아웃도이고, 제2도는 종래의 에치스토퍼형 박막트랜지스터 구조단면도이다.1A to 1D are layout diagrams for explaining a process of a conventional etch stopper type thin film transistor, and FIG. 2 is a structure cross sectional view of a conventional etch stopper type thin film transistor.
먼저, 제1a도와 같은 게이트 버스라인(1)이 형성된 기판 전면에 게이트절연막(7)을 형성하고 버스라인(1)의 돌출부 상측의 게이트절연막 위에 제1b도와 같이 아일랜드(Island)의 활성층(3)을 형성한다.First, the gate insulating film 7 is formed on the entire surface of the substrate on which the gate bus line 1 as shown in FIG. 1a is formed, and the active layer 3 of the island as shown in FIG. 1b is formed on the gate insulating film above the protrusion of the bus line 1. To form.
이때 활성층(3)의 폭은 상기 버스라인의 돌출부(1)의 폭보다 더 넓게 형성한다.In this case, the width of the active layer 3 is wider than the width of the protrusion 1 of the bus line.
제1c도와 같이 활성층(3)상의 채널영역에 해당되는 부분에 섬모양으로 에치스토퍼(2)를 형성한다.As illustrated in FIG. 1C, the etch stopper 2 is formed in an island shape in a portion corresponding to the channel region on the active layer 3.
그리고 제1d도와 같이 오믹접촉층(8)과 소오스 및 드레인금속을 증착하고 상기 에치스토퍼(2)를 에치스톱으로 이용하여 상기 오믹접촉층 및 소오스 및 드레인금속을 선택적으로 제거하여 소오스 및 드레인전극(4)을 형성한다.As shown in FIG. 1D, the ohmic contact layer 8 and the source and drain metals are deposited, and the ohmic contact layer and the source and drain metals are selectively removed using the etch stopper 2 as an etch stop. 4) form.
박막트랜지스터를 구동시키는데 있어서 게이트(1)와 활성층(3), 불순물이 도핑된 반도체층, 소오스 및 드레인전극(4)이 오버랩되는 폭(5)은 0.5㎛ 정도면 충분하므로 게이트 선폭은 에치스토퍼의 선폭보다 1㎛ 정도 크면 된다.In the driving of the thin film transistor, the width 5 of the overlapping of the gate 1, the active layer 3, the semiconductor layer doped with impurities, the source and drain electrodes 4 is sufficient to be about 0.5 μm, so that the gate line width of the etch stopper What is necessary is just 1 micrometer larger than line width.
그러면 실제 박막트랜지스터 어레이 제작시 게이트패턴의 과도식각과 에치스토퍼의 얼라인 정도를 고려할 때 게이트 선폭을 4-6㎛ 정도 더 크게 제작해야 에치스토퍼 패턴이 안정되게 게이트 위에 형성된다.Then, considering the overetching of the gate pattern and the alignment of the etch stopper when the thin film transistor array is actually manufactured, the etch stopper pattern is stably formed on the gate only when the gate line width is larger than about 4-6 μm.
이와 같이 얼라인을 고려한 게이트 전폭의 증대는 실제로 다음과 같은 문제를 야기시킨다.This increase in gate width considering alignment actually causes the following problems.
첫째, 게이트선폭의 증가는 상대적으로 픽셀전극(화소전극)의 크기를 감소시키고 블랙매트릭스의 크기를 증가시켜 개구율을 감소시킨다.First, increasing the gate line width relatively decreases the size of the pixel electrode (pixel electrode) and increases the size of the black matrix to decrease the aperture ratio.
둘째, 픽셀쪽의 오버랩되는 폭은 픽셀이 충전되었을 때 픽셀과 게이트간의 커패시터 형성에 의해 픽셀전압 강하를 유발시켜 액정구동을 불안정하게 함으로써 플릭커, 투과율감소는 물론 이를 보상하기 위한 스토리지 커패시터 크기를 크게 해야 하기 때문에 개구율 감소를 또한 유발시킨다.Second, the overlap width of the pixel side causes the pixel voltage drop by the formation of the capacitor between the pixel and the gate when the pixel is charged, thereby destabilizing the liquid crystal drive, thereby increasing the size of the storage capacitor to compensate for the flicker and transmittance as well. This also causes a reduction in aperture ratio.
셋째, 에치스토퍼의 미스얼라인에 의해 에치스토퍼 양쪽의 오버랩되는 폭의 차이는 어레이 내에 버스라인별 플릭커 현상을 유발시킨다.Third, the difference in the overlapping widths of both sides of the etch stopper due to the misalignment of the etch stopper causes a flicker phenomenon per bus line in the array.
본 고안은 기존의 액정표시소자용 박막트랜지스터가 갖고 있는 개구율, 플릭커 특성을 향상시키기 위해 개구율감소 및 플릭커의 원인이 되는 게이트 과도식각 공차, 에치스토퍼 미스얼라인 공차를 근본적으로 해결함으로써 높은 개구율을 실현, 플릭커 발생요인을 제거함은 물론 그에 개구율 향상을 크게 하는데 그 목적이 있다.In order to improve the aperture ratio and flicker characteristics of conventional thin film transistors, the present invention fundamentally solves the gate transient etching tolerance and the etch stopper misalignment tolerance, which causes the aperture ratio decrease and the flicker, thereby realizing a high aperture ratio. The purpose of this is to eliminate the cause of flickering and to increase the aperture ratio.
상기 목적을 달성하기 위한 본 고안의 액정표시소자용 박막트랜지스터를 첨부된 도면을 참조하여 설명하면 다음과 같다.Referring to the accompanying drawings, a thin film transistor for a liquid crystal display device of the present invention for achieving the above object is as follows.
제3a도~제3d도는 본 고안에 의한 박막트랜지스터의 공정을 설명하기 위한 레이 아웃도이고, 제4도는 제3도의 A-A'선에 따른 단면구조도를 나타낸 것이다.3A to 3D are layout views for explaining the process of the thin film transistor according to the present invention, and FIG. 4 is a cross-sectional view taken along line AA ′ of FIG. 3.
본 고안은 에치스토퍼의 엣지에 오버랩을 형성시키지 않고 에치스토퍼의 패턴 내부에 오버랩을 형성시키는 것으로, 게이트-에치스토퍼-활성층-소오스 및 드레인의 연속 얼라인에 의한 오버랩 결정이 아니라, 에치스토퍼 패턴화 작업시 에치스토퍼 패턴에만 의하여 게이트 오버랩크기, 박막트랜지스터의 채널폭과 길이를 결정시킴으로써 공정상의 영향없이 에치스토퍼 마스크 설계에 의하여 정확하게 조절하는 것이다.The present invention is to form an overlap inside the pattern of the etch stopper without forming an overlap on the edge of the etch stopper, and not to form an overlap crystal by the continuous alignment of the gate-etch stopper-active layer-source and drain, but to pattern the etch stopper. During operation, the gate overlap size and channel width and length of the thin film transistor are determined by the etch stopper pattern, thereby precisely controlling the etch stopper mask without affecting the process.
제3도 및 제4도를 참조하여 본 고안에 의한 박막트랜지스터의 제조공정을 살펴보면, 먼저, 기판(10) 상부에 제3a도와 같이 게이트전극/라인(11)을 형성한 후, 기판전면에 게이트절연막(12)을 형성한다.Referring to FIGS. 3 and 4, the manufacturing process of the thin film transistor according to the present invention is described. First, the gate electrode / line 11 is formed on the substrate 10 as shown in FIG. The insulating film 12 is formed.
제3b도와 같이 비정질실리콘층과 절연층을 차례로 증착하고 이를 패터닝하여 드레인전극/라인의 형상으로 게이트전극/라인보다 넓은 폭을 갖는 활성층(16) 및 에치스토퍼(13)를 형성한다.As shown in FIG. 3B, an amorphous silicon layer and an insulating layer are sequentially deposited and patterned to form an active layer 16 and an etch stopper 13 having a width wider than that of the gate electrode / line in the shape of a drain electrode / line.
이때 게이트전극(11) 상측에서 상기 활성층(16) 및 에치스토퍼(13) 부분에 2개의 콘택홀(13A)을 형성한다.In this case, two contact holes 13A are formed in the active layer 16 and the etch stopper 13 above the gate electrode 11.
그리고 제3c도와 같이 상기 콘택홀 상부에 고농도 n형 비정질 반도체층을 증착하고 이를 섬모양으로 패터닝하여 오믹접촉층(14)를 형성하고, 제3d도와 같이 상기 오믹접촉층(14) 상부에 소오스 및 드레인전극(15)을 형성한다.In addition, as shown in FIG. 3c, a high concentration n-type amorphous semiconductor layer is deposited on the contact hole and patterned into an island shape to form an ohmic contact layer 14, and a source and an upper portion of the ohmic contact layer 14 as shown in 3d. The drain electrode 15 is formed.
상기에서 콘택홀을 2개 형성하여 콘택홀 상부에 각각 소오스 및 드레인전극(15)을 형성하며, 상기 콘택홀의 크기가 게이트전극과 활성층, 소오스 및 드레인전극이 오버랩되는 폭(W)이 된다.In the above, two contact holes are formed to form source and drain electrodes 15 on the contact holes, respectively, and the contact hole has a width W overlapping the gate electrode, the active layer, the source and the drain electrode.
상기와 같은 본 고안의 박막트랜지스터 구조를 사용하게 되면, 에치스토퍼 패턴화작업에 의해 오버랩되는 크기를 최소화하여 개구율감소 및 플릭커현상 등의 문제를 해결할 수 있으며, 소오스 및 드레인전극 양쪽의 오버랩 크기를 동일하게 하여 플릭커를 막을 수 있고, 에치스토퍼 설계만으로 트랜지스터의 크기를 정확히 결정할 수 있으며 따라서 각 픽셀마다 트랜지스터 크기를 달리하여 시야각을 개선할 수 있게 된다.When the thin film transistor structure of the present invention is used as described above, problems such as reduction of aperture ratio and flickering can be solved by minimizing the overlapped size by the etch stopper patterning operation, and the overlap size of both source and drain electrodes is the same. This prevents the flicker, and precisely determines the size of the transistor with only the etch stopper design, thus improving the viewing angle by varying the transistor size for each pixel.
Claims (4)
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR2019940003233U KR200159477Y1 (en) | 1994-02-22 | 1994-02-22 | Tft lcd |
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| KR2019940003233U KR200159477Y1 (en) | 1994-02-22 | 1994-02-22 | Tft lcd |
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| KR950025629U KR950025629U (en) | 1995-09-18 |
| KR200159477Y1 true KR200159477Y1 (en) | 1999-10-15 |
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1994
- 1994-02-22 KR KR2019940003233U patent/KR200159477Y1/en not_active IP Right Cessation
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| Publication number | Publication date |
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| KR950025629U (en) | 1995-09-18 |
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