KR20010109625A - Ferroelectric substance memeory device generating reference voltage using reference cell and sense amplifier - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ferroelectric memory device of a semiconductor memory device, which eliminates aging of ferro-capacitor by using a ferroelectric memory cell and a sense amplifier that store '0' data, thereby extending the life of the memory. You can. To this end, the present invention provides a ferroelectric memory device, comprising: a reference cell including a ferroelectric capacitor storing data '0' and a switching transistor for occupying the voltage of the ferroelectric capacitor and the voltage of a bit line; And a plurality of resistors having an input terminal configured as a PMOS transistor to receive a voltage loaded on the bit line, generate a reference voltage, and output the reference voltage to the bit bar line, wherein the output terminal outputs the output signal to adjust the reference voltage. It consists of a sense amplifier.

Description

Ferroelectric substance memeory device generating reference voltage using reference cell and sense amplifier

The present invention relates to a semiconductor memory device, and more particularly to a ferroelectric memory device.

In general, a capacitor using a ferroelectric material as a dielectric has a hysteresis relationship between the voltage across the capacitor and the amount of charged charge.

Fig. 1 is a diagram showing the relationship of the charge amount according to the voltage between the ferroelectric capacitor terminals a and b.

Referring to FIG. 1, when the voltage between the ferroelectric capacitors is 0V, the polarization state of the ferroelectric material exists in two states, 'a' and 'b', so that data in binary form may be stored without supply of power. By utilizing these characteristics, the ferroelectric capacitor is used as a storage means of the nonvolatile memory device.

According to the magnitude of the voltage applied across the ferroelectric capacitor, the polarization state in the ferroelectric is changed to change the amount of charge stored in the capacitor. When a sufficiently large negative voltage is applied to the ferroelectric capacitor that maintains the polarization state in the 'ga' state, the polarization state changes along the hysteresis curve in the direction of 'multi', and removes the negative voltage to reset the voltage across the capacitor. If you set it to 0V, it moves to 'I' state.

In recent years, development of a memory using such a ferroelectric capacitor as a storage means has been in progress. A paper on this development is published in the IEEE Journal of Solid State Circuits, VOL31, NO.11, NOVEMBER 1996. The ferroelectric memory currently under development has a structure similar to that of general DRAM. In a memory cell consisting of one ferroelectric capacitor and one switch transistor, a wordline is connected to the gate of the switch element to turn the switch element on and off, and a ferroelectric capacitor is connected to the drain or source node of the switch element and the other node of the capacitor. Is connected to the plate line. In addition, the other node of the switch element is connected to the bit line, and the bit line and the word line cross each other. Ferroelectric memory cell configurations and memory arrays thus have a structure similar to DRAM.

Another commonality between DRAM and ferroelectric memory is that in order to output the data stored in the capacitor, it must generate a reference voltage that can be compared with the data to be output.

2 is a circuit diagram illustrating generation of a reference voltage in a ferroelectric memory.

Referring to FIG. 2, a ferroelectric memory cell generates a reference voltage using a scheme shown in FIG. 2 unlike a DRAM. That is, two ferroelectric memory cell transistors 200 and 210 are simultaneously turned on by the logic high value of the word line, and data values of '0' and '1' are output to the bit line and the bit bar line, respectively. The data values output to the bit line and the bit bar line cause charge sharing by the components of the capacitors existing in the bit line and the bit bar line before the cell transistor is turned on. Charge sharing occurs and after a while, an equalizing signal is turned on to equalize the voltage difference between the bit line and the bit bar line, and the transistor 220 for the equivalent is turned on. In this equivalent process, the bit line and the bit bar line exist at the same level.

The voltage level at which this bit line and the bit bar line are the same becomes the reference voltage.

However, when the reference voltage is created in the above manner, a disadvantage arises in that the ferro-capacitor of the cell used to create the reference level is quickly aged. In particular, in the case of a Far-Capacitor of a cell storing '1' data, aging occurs, resulting in a problem that the voltage level of the '1' stored is lowered and the lifespan of the memory is shortened.

The present invention has been made to solve the above problems of the prior art, a sense that can eliminate the aging of the ferro-capacitor of the cell when the reference voltage is generated in the ferroelectric memory and extend the life of the memory It is an object of the present invention to provide a ferroelectric memory device having an amplifier.

1 is a circuit diagram and a diagram showing the relationship of the amount of charge according to the voltage between the ferroelectric capacitor terminals a, b;

2 is a circuit diagram showing generation of a reference voltage in a ferroelectric memory;

3 is a circuit diagram of a reference cell for explaining the principle proposed in the present invention;

4 is a circuit diagram of a sense amplifier of the present invention;

5 is a block diagram illustrating a sense amplifier input and output between a bit line and a bit bar line.

Explanation of symbols on the main parts of the drawings

400: first PMOS transistor 430: first NMOS transistor

500: sense amplifier

In order to achieve the above object, the ferroelectric memory device of the present invention includes a ferroelectric capacitor storing data '0', and a switching transistor for occupying the voltage of the ferroelectric capacitor and the voltage of the bit line. A reference cell; And a plurality of resistors having an input terminal configured as a PMOS transistor to receive a voltage loaded on the bit line, generate a reference voltage, and output the reference voltage to the bit bar line, wherein the output terminal outputs the output signal to adjust the reference voltage. It consists of a sense amplifier.

As described above, the present invention eliminates the aging phenomenon of the ferro-capacitor by using a ferroelectric reference cell and a sense amplifier that store '0' data, thereby extending the life of the memory.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. .

3 is a circuit diagram of a reference cell for explaining the principle proposed in the present invention.

Referring to FIG. 3, a reference cell includes an NMOS transistor 300 having a gate terminal connected to a word line and a source-drain stage formed between a bit line and a capacitor, and the NMOS transistor 300 and a plate. ) A ferroelectric capacitor 310 storing '0' data between the lines.

4 is a circuit diagram of a sense amplifier of the present invention.

Referring to FIG. 4, the sense amplifier of the present invention includes a first resistor R1 connected between a power supply voltage and a node d, a second resistor R2 formed between the node d and an output bit bar line, and '0'. A first PMOS transistor 400 having a bit line of a cell storing data as a gate terminal and a source-drain terminal formed between a power supply voltage and a node a, and the node d as a gate terminal receiving a source- A second PMOS transistor 410 having a drain terminal formed between the node a and the node b, and a third PMOS transistor having a source line and a drain terminal formed between the node a and the node c while receiving the bit line as a gate terminal; 420, a first NMOS transistor 430 having a gate terminal and a drain terminal connected to the node b, and a source terminal connected to the ground terminal, the node b being input to the gate terminal, and a source-drain terminal being connected to the node c. The second NMOS transistor 440 formed between the ground terminals , Receives the node c to the gate terminal the source-to-drain output stage comprising a third NMOS transistor (450) formed between the bit is at the ground terminal.

In FIG. 3, when the word line is turned on, '0' data stored in the ferro-capacitor flows into the bit line to charge and share the bit line. The voltage of the bit line after sharing is input to the input of the sense amplifier of FIG. The reason why the input terminal of FIG. 4 is replaced with the PMOS transistor instead of the EnMOS transistor is because the input voltage of the sense amplifier is 0.4 V, which is the low data of the cell, and the threshold voltage is 0.7 V or less. It is not turned on and eventually the sense amplifier does not operate so that the desired reference voltage cannot be generated. For this reason, in the present invention, the input terminal transistor of the sense amplifier uses a PMOS transistor instead of an enMOS transistor.

As the bit line voltage of FIG. 3 enters the input of FIG. 4, the sense amplifier operates and generates a reference voltage through the output stage. In order to adjust the reference voltage generated as shown in FIG. 4, the resistor R1, R2 will be connected in parallel. The output voltage output through the sense amplifier is output by Equation 1 below.

Vout = (1 + R1 / R2) × Vin

5 is a block diagram illustrating a sense amplifier input and output between a bit line and a bit bar line.

Referring to FIG. 5, a bit line carrying data of a memory cell enters an input of a sense amplifier, and an amplified reference voltage is output as a bit bar line and compared with data of a memory cell loaded on the bit line.

Through this comparison process, data of the memory cell is output.

Although the technical spirit of the present invention has been described in detail according to the above-described preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

As described above, the present invention eliminates the aging phenomenon of the cell capacitor and extends the lifespan of the ferroelectric memory cell by using a sense amplifier that inputs the voltage of the bit line.

Claims (2)

In a ferroelectric memory device, A reference cell including a ferroelectric capacitor storing data '0' and a switching transistor for charge-sharing the voltage of the ferroelectric capacitor and the voltage of the bit line; And Its input terminal is composed of a PMOS transistor, and receives the voltage loaded on the bit line to generate a reference voltage and output it to the bit bar line, and includes a plurality of resistors to adjust the reference voltage at the output terminal for outputting the output signal. Sense amplifier Ferroelectric memory device comprising a. The method of claim 1, The sense amplifier, A first PMOS transistor having a source-drain path formed between a first power supply terminal and the first node and a gate connected to the bit line; First and second resistors connected in series between the first power supply terminal and an output node; A second PMOS transistor having a gate connected to the common node of the first resistor and the second resistor and having a source-drain path formed between the first node and the second node; A third PMOS transistor having a gate connected to the bit line and having a source-drain path formed between the first node and the third node; A first NMOS transistor having a source-drain path formed between the second node and a second power supply terminal, and a gate of which is connected to the second node; A second NMOS transistor having a source-drain path formed between the third node and the second power supply terminal and having a gate connected to the second node; And A third NMOS transistor having a source-drain path formed between the output node and the second power supply terminal and having a gate connected to the third node; A ferroelectric memory device comprising a.