KR20010106950A - Semiconductor memory device - Google Patents

Abstract

The present invention discloses a semiconductor memory device. The apparatus includes a row decoder for generating a plurality of word line selection signals by decoding a row address, a column decoder for generating a plurality of column selection signals by decoding a column address, and a plurality of word lines output from the row decoder. A predetermined number of word lines are activated in response to the selection signals, and each of the plurality of memory cell array blocks is configured to input and output a predetermined bit of data in response to one column selection signal among the plurality of column selection signals. It consists of a predetermined number of memory cell arrays. Accordingly, the number of input and output data can be increased by simultaneously activating a plurality of word lines to input and output data. In addition, by activating the plurality of word lines with a predetermined time difference, noise generated during word line activation may be reduced.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of activating a plurality of word lines within a word line activation period and reducing noise generated when the plurality of word lines are activated.

In a conventional semiconductor memory device, one word line and one column select signal line in a memory cell array are selected to input and output data between selected memory cells and a data input / output line.

Fig. 1 is a block diagram showing the structure of a conventional semiconductor memory device, which includes four memory cell array blocks 10-1, 10-2, 10-3, 10-4, row decoder 12, and column decoder. It consists of (14).

Referring to the data read and write operations using the block diagram shown in FIG.

The row decoder 12 decodes the n-bit row address RA0-n so that the k word line select signals (WL1, ..., WL (k / 4)), (WL (k / 4 + 1) ), ..., WL (k / 2)), (WL (k / 2 + 1), ..., WL (3k / 4 + 1), ..., WLk)).

The column decoder 14 decodes the m-bit column address CA0-m to generate L column select signals CSL1, CSL2, ..., CSLl.

When the memory cell array block 10-1 is selected and the word line WL1 is activated, the memory cells MC (not shown) connected to the word line WL1 are activated. When the column select signal CSL1 is selected, data is read from the selected memory cell MC (not shown) or data is written to the selected memory cell MC (not shown) in response to the column select signal CSL1. .

As described above, in a conventional semiconductor memory device, one word line is selected during a read or write operation, and data is written to a memory cell connected to the selected word line, or data is read from a memory cell connected to the selected word line. .

FIG. 2 shows a configuration of an embodiment of the memory cell array block 10-1 shown in FIG. 1, wherein the memory cells MC and precharge circuits PRE 20-1, 20-2, ..., 20- (2m)) and data input / output gates 22-1, 22-2, ..., 22- (2m).

Each function of the block shown in FIG. 2 is explained as follows.

The memory cells MC include bit line pairs (BL1, BL1B), (BL2, BL2B), ..., (BL (2m), BL (2m) B)) and word lines WL1, WL2,. .., WL (m / 4)) are connected respectively to store data. The precharge circuits PRE 20-1, 20-2, ..., 20- (2m) are the bit line pairs (BL1, BL1B), (BL2, BL2B), ..., (BL (2m) and BL (2m) B)) are respectively precharged.

The data input / output gates 22-1, 22-2, ..., 22- (2m) are the bit line pairs (BL1, BL1B), (BL2, BL2B), ..., (BL (2m) Column select signals CSL1, CSL2, ..., CSLm to transfer data between the BL (2m) B) and the data input / output line pairs ((IO1, IO1B), (IO2, IO2B)). In response to the bit line pairs (BL1, BL1B), (BL2, BL2B), ..., (BL (2m), BL (2m) B)) and the data input / output line pairs ((IO1, IO1B), (IO2, IO2B)).

In the conventional semiconductor memory device as shown in FIG. 1, memory cells connected between one word line and one bit line pair are activated to input and output data.

However, the conventional semiconductor memory device as described above has a limitation in increasing the number of input / output data by only inputting one word line to input and output data.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of increasing the number of input / output data by activating a plurality of word lines within a word line activation period.

Another object of the present invention is to provide a semiconductor memory device capable of reducing noise that may be generated when a plurality of word lines are activated.

A semiconductor memory device of the present invention for achieving the above object and other objects is a row decoder for generating a plurality of word line selection signals by decoding a row address, a row decoder for generating a plurality of column selection signals by decoding a column address A predetermined number of word lines are activated in response to a column decoder and a plurality of word line selection signals output from the row decoder, respectively, and a predetermined number of bits is generated in response to one column selection signal of the plurality of column selection signals. And a predetermined number of memory cell arrays each having a plurality of memory cell array blocks for inputting and outputting data.

When the predetermined number of word lines are activated, the word lines are activated with a predetermined time difference within a word line activation period.

1 is a block diagram showing the structure of a conventional semiconductor memory device.

FIG. 2 is a detailed block diagram of the memory cell array block shown in FIG.

3 is a block diagram showing the structure of a conventional semiconductor memory device.

Fig. 4 is a block diagram showing the construction of one embodiment of a semiconductor memory device of the present invention.

Fig. 5 is a block diagram showing the construction of another embodiment of the semiconductor memory device of the present invention.

Hereinafter, a conventional semiconductor memory device will be described with reference to the accompanying drawings before describing the semiconductor memory device of the present invention.

Fig. 3 is a block diagram showing the structure of a conventional semiconductor memory device, which includes memory cell array blocks 30-1, 30-2, ..., 30-8, row decoder 32, and column decoders ( 34-1, 34-2).

3 shows a block diagram when the memory cell array block is doubled in the word line direction (horizontal direction) in order to double the memory capacity of the semiconductor memory device shown in FIG.

The semiconductor memory device shown in FIG. 3 uses memory column array blocks 30-1, ..., 30-4 and memory cell array blocks (2-4) using two column decoders 34-1, 34-2. 30-5, ..., 30-8) Each of the column select signal lines CSL1, ..., CSLl is selected.

A column for selecting one column select signal line of each of the memory cell array blocks 30-1, ..., 30-4 and the memory cell array blocks 30-5, ..., 30-8. The decoders 34-1 and 34-2 decode the m-bit column addresses CA0-m, respectively, to generate L column select signal lines CSL1, ..., CSLl.

That is, one column select signal line of each of the memory cell array blocks 30-1,..., 30-4 and the memory cell array blocks 30-5,. CSL1, ..., CSLl) are selected simultaneously.

Therefore, the semiconductor memory device shown in FIG. 3 can select two column select signal lines at the same time and input / output twice as much data as the semiconductor memory device shown in FIG. 1 can input and output.

The configuration of each of the memory cell array blocks shown in FIG. 3 will be referred to with reference to the configuration shown in FIG. 2.

The present invention does not increase the memory cell array block in the word line direction to increase the number of data input / output, but increases the memory cell array block in the column select signal line direction.

Fig. 4 is a block diagram showing the construction of an embodiment of a semiconductor memory device of the present invention, wherein memory cell array blocks 40-1, ..., 40-8, row decoders 42-1, 42-2. ) And a column decoder 44.

In the semiconductor memory device shown in Fig. 4, two row decoders 42-1 and 42-2 decode the same n-bit row addresses RA0-n so that k-bit word line select signals WL1,. ..WLk).

Accordingly, one word line of each of the memory cell array blocks 40-1,..., 40-4 and the memory cell array blocks 40-5,..., 40-8 is selected. That is, two word lines are activated at the same time.

That is, two word lines of the memory cell array blocks 40-1, ..., 40-4 and the memory cell array blocks 40-5, ..., 40-8 are simultaneously activated, one When the column select signal line is selected, twice the data that can be input and output by the semiconductor memory device shown in FIG. 1 can be input and output.

However, as described above, when two word line selection signals are selected at the same time, noise is generated when the word line is activated.

Thus, in the present invention, in order to reduce noise generated when two word line selection signals are selected at the same time, the row decoders 42-1 and 42-2 do not simultaneously generate word line selection signals, but word lines. One word line selection signal is activated by the row decoder 42-1 and another word line selection signal is activated by the row decoder 42-2 after a predetermined time within the activation period.

This can be implemented simply by delaying the time point at which the row decoder 42-2 outputs the word line selection signals from the time point at which the row decoder 42-1 outputs the word line selection signals.

Fig. 5 is a block diagram showing the construction of another embodiment of the semiconductor memory device of the present invention, wherein the memory cell array blocks 40-1, ..., 40-8, row decoders 42-1, and columns are shown. The decoder 44 is comprised.

The block diagram of the embodiment shown in FIG. 5 is constructed by removing the row decoder 42-2 from the block diagram shown in FIG.

That is, two word lines are simultaneously activated using one row decoder 42-1.

In the above-described embodiment, the two word line selection signals are activated with a predetermined time difference, but the idea of the present invention may be applied even when two or more word line selection signals are activated with a predetermined time difference. .

Although the above has been described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the present invention without departing from the spirit and scope of the invention described in the claims below. I can understand that you can.

Accordingly, the semiconductor memory device of the present invention can increase the number of input and output data by simultaneously activating a plurality of word lines to input and output data.

In addition, by activating the plurality of word lines with a predetermined time difference, noise generated during word line activation may be reduced.

Claims (2)

A row decoder for generating a plurality of word line select signals by decoding the row address; A column decoder for generating a plurality of column select signals by decoding a column address; And A predetermined number of word lines are activated in response to a plurality of word line selection signals output from the row decoder, and input and output a predetermined bit of data in response to one column selection signal of the plurality of column selection signals. And a predetermined number of memory cell arrays each having a plurality of memory cell array blocks. The method of claim 1, wherein the predetermined number of memory cell arrays And the word lines are activated with a predetermined time difference within a word line activation period when the predetermined number of word lines are activated.