KR20010105797A - Capacitor in semiconductor device and method for manufacturing thereof - Google Patents

Abstract

An apparatus (1) for bonding a first disk (D1) coated with bonding agent and a second disk (D2) together. The second disk (D2) is held by suction to cause it to bend in the opposite direction of the first disk (D1) and is attached to the first disk (D1) with their borders in contact to join the two disks (D1) and (D2) by suction resulted from a partial vacuum between them.

Description

CAPACITY OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a capacitor of a semiconductor device and a method of manufacturing the same, and more particularly, to a capacitor capable of maintaining a constant sheet resistance while increasing capacitance by double concentration deposition of an upper electrode of a capacitor, and a method of manufacturing the same.

In order to increase the capacitance of the semiconductor memory device, it is possible to change the three variables of the dielectric constant and the area and the thickness of the dielectric film.

--------------------- (One)

Here, the permittivity of the ε _Γ dielectric film, A is the electrode area, and d is the thickness of the dielectric film.

As a method of increasing the effective area in order to increase the capacitance of the capacitor, a method of increasing the surface area of an electrode by growing HSG (heavy crystal grain) and curved crystal grains on the surface of the lower electrode is generally used.

HSG is a method of increasing the surface area of an electrode by using a kind of surface movement mechanism, that is, surface movement of silicon. That is, when the amorphous silicon of a certain thickness is transformed into crystalline silicon, it is achieved by generating surface curvature. Since the deposited dielectric film and the upper electrode is deposited along the curve, the portion where the upper electrode is in contact with the dielectric film is also bent.

Therefore, when a positive voltage is applied to the upper electrode, concentration of an electric field occurs along the curved portion as compared with the case where the surface is flat. Therefore, since the electric field received by the electrons in the upper electrode becomes large, the thickness of the depletion layer generated in the upper electrode increases. The thickness of this depletion layer results in a reduction in the value of the capacitance and eventually in the overall capacitance.

There is a method of reducing the thickness of the depletion layer by increasing the impurity concentration of the upper electrode. If the impurity concentration is increased, the resistance of the upper electrode is lowered, which is beyond the design target sheet resistance. Typically, the upper electrode is provided as a load resistor as well as the upper electrode of the capacitor. Therefore, the load resistor must have a certain level or more of sheet resistance. In general, sheet resistance is proportional to thickness and inversely proportional to resistivity. Therefore, if the impurity concentration of the upper electrode is increased, the specific resistance decreases, so that the desired sheet resistance value cannot be obtained. Therefore, simply increasing the concentration of impurities to reduce the thickness of the depletion layer of the upper electrode limits the formation of the load resistor using the upper electrode.

An object of the present invention is to form a top electrode by double deposition of high concentration primary deposition and low concentration secondary deposition in order to solve this problem of the prior art, while reducing the thickness of the depletion layer of the capacitor upper electrode while being used as a load resistor The present invention provides a capacitor of a semiconductor device capable of maintaining such a sheet resistance and a method of manufacturing the same.

Another object of the present invention is to provide a capacitor of a semiconductor device capable of increasing the breakdown voltage of the capacitor and a method of manufacturing the same.

1 is a cross-sectional view showing the configuration of a semiconductor device with a capacitor according to the present invention.

2a and 2b are views for explaining the field concentration phenomenon according to the surface curvature.

3 is a graph comparing the characteristics of the capacitance of the capacitor during single concentration deposition and double concentration deposition.

Figure 4 is a graph showing the characteristics of the capacitance of the capacitor during the double concentration deposition according to the present invention.

5 is a graph comparing the breakdown voltage characteristics of a capacitor during single concentration deposition and double concentration deposition.

<Description of the symbols for the main parts of the drawings>

10 semiconductor substrate 12 field oxide film

14: gate electrode layer 16; Pad electrode

18: insulating film 20: bit line

22: interlayer insulating film 24: contact hole

26: lower electrode 27: bent crystal grain

28 dielectric film 30 upper electrode

30a: high concentration first silicon layer 30b: low concentration second silicon layer

32: Insulation

membrane

In order to achieve the above object of the present invention, the apparatus of the present invention comprises the steps of forming a lower electrode composed of amorphous silicon on the semiconductor substrate, forming a curved crystal grain on the lower electrode surface, and the curved crystal grain phase Removing the natural oxide film formed on the dielectric layer; covering the lower electrode surface on which the curved crystal grains are formed with a uniform thickness of a dielectric film; depositing a first silicon layer doped with a high concentration of impurities on the dielectric film to a predetermined thickness; And depositing a second silicon layer doped with a low concentration of impurities to a predetermined thickness to form an upper electrode.

The capacitor of the present invention includes a lower electrode composed of amorphous silicon on a semiconductor substrate, a plurality of curved crystal grains formed on the surface of the lower electrode, a dielectric film coated with a uniform thickness on the lower electrode surface on which the curved crystal grains are formed, And depositing a first silicon layer doped with a high concentration of impurities to a predetermined thickness on the dielectric layer, and then depositing a second silicon layer doped with a low concentration of impurities to a predetermined thickness.

Here, the impurity is P or As, and the impurity concentration of the first silicon layer is 1E20 atoms / cm 2 or more, and the impurity concentration of the second silicon layer is less than 1E20 atoms / cm 2. The thickness of the first silicon layer is 50 to 500 kPa.

Hereinafter, with reference to the accompanying drawings, it will be described in detail the present invention through an embodiment of the present invention.

1 shows a configuration of a semiconductor device in which a capacitor according to the present invention is formed. As shown in FIG. 1, the capacitor of the present invention includes a lower electrode 26, a dielectric film 28, and an upper electrode 30 on a semiconductor substrate 10. The upper electrode 30 includes a first silicon layer 30a doped with a high concentration of impurities and a second silicon layer 30b doped with a low concentration of impurities. The impurity concentration of the first silicon layer 30a is 1E20 atoms / cm 2 or more, and the impurity concentration of the second silicon layer 30b is less than 1E20 atoms / cm 2.

A plurality of curved crystal grains 27 are formed on the surface of the lower electrode 26. The dielectric film 28 is deposited along the curvature of the surface of the lower electrode, and the upper electrode 30 is deposited thereon, so that the portion in contact with the dielectric film of the upper electrode is also curved.

Therefore, when a positive voltage is applied to the upper electrode, concentration of an electric field occurs along the curved portion as compared with when the surface is flat (see FIG. 2A) (see FIG. 2B). Therefore, since the electric field received by the electrons in the upper electrode becomes large, the thickness of the depletion layer generated in the upper electrode according to Equation (2) increases. The thickness of this depletion layer reduces the value of the capacitance by the following equation (3) and eventually reduces the total capacitance as shown in equation (3).

----------------(2)

------------------------------- (3)

-------------------------------(4)

C _tot is the total capacitance,

Capacitance for C ₀ dielectric film,

C _d is the capacitance by the depletion layer,

X _d is the depletion layer thickness,

₀ is the vacuum permittivity,

_si is the silicon dielectric constant.

A is the effective area,

V ₀ is the applied voltage,

q is the charge of the electron,

N _a represents the impurity number.

However, in the present invention, by increasing the impurity concentration of the first silicon layer 30a, the thickness of the depletion layer can be reduced by the formula (2), so that the total capacitance is increased by the formulas (3) and (4). You can.

On the other hand, the impurity concentration of the second silicon layer 30b of the upper electrode 30 is low so that the sheet resistance value required in the portion provided to the load resistor can be satisfied.

The manufacturing method of the semiconductor device of this invention comprised in this way is as follows.

First, the field oxide film 12 is formed on the semiconductor substrate 10 by a normal semiconductor manufacturing process. A gate oxide layer, a gate electrode layer, and an insulating layer are sequentially stacked on the semiconductor substrate 10, and then patterned to form a gate electrode pattern or a word line pattern 14. Sidewall spacers are formed on sidewalls of the gate electrode pattern 14.

Subsequently, polysilicon is deposited and patterned on the entire surface of the resultant to form the pad electrode 16. After the pad electrode 16 is formed, the insulating film 18 is deposited on the entire surface. The deposited insulating film 18 is patterned to form bit line contacts, and then polysilicon is deposited and patterned to form the bit line 20.

The contact line 24 is formed by covering the bit line 20 with the interlayer insulating layer 22 and patterning the interlayer insulating layer 22. Amorphous silicon is deposited and patterned on the interlayer insulating layer 22 having the contact hole to form a lower electrode 26, that is, a storage node.

Subsequently, the semiconductor substrate on which the strip node is formed is wet-washed to remove surface contamination and the surface oxide film using an etching process. The HSG process is performed in a high vacuum chamber of 10E -6 torr or less to form HSG grains 27 on the lower electrode 26 surface. The dielectric film 28 is then deposited by wet etching to remove contaminants and native oxide films.

The upper electrode 30 is deposited on the dielectric film 28. The upper electrode 30 deposits polysilicon 30a doped with a P concentration of 1E20 atoms / cm 2 or more at 50 to 500 GPa, followed by polysilicon 30b doped with a P concentration of less than 1E20 atoms / cm 2. Deposit.

The first and second polysilicon 30a and 30b are patterned to form an upper electrode 30 in the cell region, and a load resistor (not shown) in the peripheral region. The insulating film 32 is deposited on the semiconductor substrate on which the upper electrode is formed.

Figure 3 shows a graph comparing the characteristics of the capacitance of the capacitor during single concentration deposition and double concentration deposition. In FIG. 3, one-step deposition of the capacitance of a capacitor doped with 1,500 실리콘 of silicon doped with a P concentration of 3.6E20 atoms / cm 2 and 700 Å of silicon doped with a P concentration of 6.6E20 atoms / cm 2 was carried out, and a P concentration of 0.8E20 atoms was obtained. This is a comparison of the capacitances of a capacitor deposited at 800 mW with a silicon doped at / cm 2.

When the voltage of + 1.2V is applied to the upper electrode, the capacitance is Cmax, and when the voltage of -1.2V is applied, the capacitance is denoted as Cmin. As shown in the graph, it can be seen that the capacitance of the double concentration capacitor is increased by 3 fF / C and the Cmin / Cmax is also improved compared to the capacitance of the single concentration capacitor.

4 is a graph showing the characteristics of the capacitance of the capacitor during the double concentration deposition according to the present invention. The capacitive characteristics of the capacitor in which the upper electrode was deposited in one step of silicon doped with P concentration of 6.6E20 atoms / cm 2 at 950 mW and in two steps of silicon doped with P concentration of 0.8E20 atoms / cm 2 at 600 mW are shown. That is, the Cmax of the double concentration capacitor increases by 5fF / C compared to 26 ~ 27fF / C of the existing process and the Cmin / Cmax is closer to 1.0.

As the deposition rate of silicon doped with P concentration of 6.6E20 atoms / cm 2 is reduced by about 40% compared to silicon doped with P concentration of 3.6E20 atoms / cm 2, this change in deposition rate affects step coverage and thus the breakdown voltage I think it will improve.

5 shows a graph comparing the breakdown voltage characteristics of a capacitor during single concentration deposition and double concentration deposition. The breakdown voltage (10nA BV, 1K CellCap) of the double-density capacitor is 0.4V higher than the 3.7V of the existing process.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

As described above, in the present invention, the upper electrode of the capacitor is deposited with a high concentration of silicon as a primary and a low concentration of silicon as a secondary to reduce the depletion layer thickness of the upper electrode while maintaining the sheet resistance of the upper electrode at a desired value. . In addition, by depositing double concentration of silicon, the effect of reducing the void of the upper electrode can be obtained, thereby increasing the breakdown voltage of the capacitor.

Claims (8)

Forming a lower electrode composed of amorphous silicon on the semiconductor substrate; Forming curved crystal grains on the lower electrode surface; Removing the native oxide film formed on the curved crystal grains; Covering the lower electrode surface on which the curved crystal grains are formed with a uniform dielectric film; And depositing a first silicon layer heavily doped with impurities to a predetermined thickness on the dielectric layer, and then depositing a second silicon layer doped with a low concentration of impurities to a predetermined thickness to form an upper electrode. A method for manufacturing a capacitor of a semiconductor device. The method of claim 1, wherein the impurity concentration of the first silicon layer is 1E20 atoms / cm 2 or more, and the impurity concentration of the second silicon layer is less than 1E20 atoms / cm 2. The method of manufacturing a capacitor of a semiconductor device according to claim 2, wherein the first silicon layer has a thickness of 50 to 500 kPa. The method of manufacturing a capacitor of a semiconductor device according to claim 1, wherein the impurity is either P or As. A lower electrode composed of amorphous silicon on the semiconductor substrate; A plurality of curved crystal grains formed on the surface of the lower electrode; A dielectric film coated with a uniform thickness on a surface of the lower electrode on which the curved crystal grains are formed; And depositing a first silicon layer heavily doped with impurities to a predetermined thickness on the dielectric film, and then depositing a second silicon layer doped with a low concentration of impurities to a predetermined thickness. Capacitor. The method of claim 5, wherein the impurity concentration of the first silicon layer is 1E20 atoms / cm 2 or more, and the impurity concentration of the second silicon layer is less than 1E20 atoms / cm 2. The method of manufacturing a capacitor of a semiconductor device according to claim 6, wherein the thickness of said first silicon layer is 50 to 500 microseconds. 6. The method of claim 5, wherein the impurity is either P or As.