KR20010105678A - Histogram Equalization device using block histogram in image signal processor - Google Patents

Abstract

Methods for treating and/or preventing non-insulin dependent diabetes mellitus (NIDDM) in subjects having or at substantial risk of developing NIDDM, using specific retinoid compounds that are structurally related to 9-cis retinoid acid which induce the differentiation of preadipocytes into adipocytes, are provided. These compounds may be administered alone or in combination with other anti-diabetogenic agents such as thiazolidinediones.

Description

Histogram Equalization device using block histogram in image signal processor

The present invention relates to an image signal processor that receives image data output from an image sensor for better image quality, and more particularly relates to an image signal processor. A flattening device.

In general, since the image data output from the image sensor has a relatively low image quality characteristic, the image data from the image sensor is subjected to image processing in the image signal processor for better image quality.

Such an image signal processor processes signals through histogram equalization for applications requiring real-time processing because it is difficult to obtain a desired brightness quality due to low sensitivity when operating an image sensor in real time. .

Here, the flattening method of the distribution is to determine the degree of brightness of one screen, and the gray level of each pixel divided by brightness, that is, the brightness information of the pixel by multiplying the scale factor to appropriate the dark screen As a method of obtaining a new screen adjusted by brightness, it has been mainly implemented by a software method until now, but with the development of VLSI (Very Large Scaled Integration) technology, it can be implemented in hardware inside an image signal processor.

1 is a block diagram of a distribution planarization apparatus of an image signal processor for implementing a conventional distribution planarization method.

Referring to the drawings, the conventional planarization flattening apparatus receives a brightness information Y_In of a pixel output from an image sensor (not shown) and stores the screen information one by one, and the brightness information of each pixel ( Y_In) to receive and store the distribution at 256 levels (dynamic range), and store the distribution to determine the brightness information corresponding to the median value of the stored distribution as the reference brightness information (YF_Mean) and the brightness determination unit 110 of the intermediate value. A scale factor generator 120 generating a scale factor of each pixel divided by brightness with respect to reference brightness information YF_Mean using the distribution chart, and a generated scale factor, and stored in the frame memory 100 The scale factor storage and distribution planarization unit 130 is configured to flatten the brightness information of one screen by multiplying the brightness information of the pixel by the corresponding scale factor.

The conventional planarization flattening device configured as shown in FIG. 1 requires a lot of hardware resources, so that it is difficult to be implemented in hardware in an image signal processor, and uses a system host (for example, a microprocessor) and a system memory. If implemented in software, this can lead to degradation of the overall system due to image signal processing.

In addition, when the distribution factor is biased in a specific area by applying the middle value of the distribution chart composed of brightness information as the reference brightness information (YF_Mean), the image quality is good due to the extreme stretching in one direction. Can't get it.

The present invention has been made to solve the above problems, and stores the distribution of the brightness information of each pixel for each predetermined area divided into blocks, and uses the average value of the brightness information of each pixel as reference brightness information. In addition, the scale factor is generated by applying the scale factor for each block based on the average value of brightness information of one screen, and the distribution scale is flattened using the generated scale factor to increase the contrast to improve image quality and to increase the hardware size. SUMMARY To provide a flattening device for distribution using a block distribution in an image signal processing device.

1 is a block diagram of a distribution planarization apparatus of an image signal processor for implementing a conventional distribution planarization method.

Figure 2 is a graph for conceptually explaining a distribution planarization method according to the present invention.

3 is a block diagram of a distribution planarization apparatus according to the present invention;

4 is an internal block diagram of a brightness average value generator of a screen according to an embodiment of the present invention.

5 is a signal timing diagram for a brightness average value generator of the screen;

6 is an internal block diagram of a distribution chart generator for each block according to an embodiment of the present invention.

7 is an internal block diagram of a controller in the distribution chart generation unit for each block.

8 is an internal block diagram of a flattener according to an embodiment of the present invention.

9 is an internal block diagram of the range selector of FIG. 8; FIG.

FIG. 10 is an internal block diagram of the scale factor generator of FIG. 8. FIG.

In accordance with an aspect of the present invention, there is provided an apparatus for flattening a distribution using a block distribution in an image signal processing apparatus, and receiving brightness information of pixels from an external device in response to a clock signal and a frame synchronization signal and displaying the same on a screen. Means for generating a brightness average value of the screen for obtaining a brightness average of the screen; A brightness average value from the brightness average value generating means and the brightness information of the pixel are received and divided into a plurality of blocks to generate and store a distribution map, and a block to which the number of pixels for each block and the brightness average value output from the brightness average value generating means belong. Distribution block generation and storage means for outputting a number of pixels and a number of pixels having brightness information less than and exceeding the brightness average value; And a brightness value required by the user, first and second factors for determining a dynamic range of the brightness information of the pixel, brightness information of the pixel, and information on the number of pixels output from the block generation and storage means for each block. And a flattening means for generating a scale factor for each block to which the brightness average value belongs, and generating a scale factor for each block for each block to flatten the brightness information of one screen.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

In a preferred embodiment of the present invention, the brightness information is divided into 16 blocks to store a distribution map, and when the scale factor is generated, the block scale factor is linearly divided and applied to minimize the error of the block, and the brightness information of each pixel. For a block in which the reference brightness information YF_Mean, which is an average value of, exists, the distribution is stored for each brightness information of each pixel divided by the brightness information to remove an error in the block including the reference brightness information YF_Mean. That is, in a block including the reference brightness information YF_Mean, a scale factor is generated in pixel units and applied when flattening the distribution, and in the remaining blocks, a scale factor is generated in block units.

2 is a graph for conceptually explaining a distribution planarization method according to the present invention.

In the graph of FIG. 2, "Y" is gray level in the color space (pixel brightness information), YF_Mean is the average value of one screen brightness, Y_Target is the brightness level required by the user, and Y_Start and Y_end are brightness and contrast. The factor to determine the dynamic range is to support the adjustable, YaTotal is the number of pixels with brightness information greater than YF_Mean, Ya is the brightness information of any pixel in the brightness information area greater than YF_Mean, and YaSub is YF_Mean Is the number of pixels between Y and Yb, YbTotal is the number of pixels with brightness information less than YF_Mean, Yb is the brightness information of any pixel in brightness information area less than YF_Mean, and YbSub is between Ystart and Yb. Each pixel number is shown.

Referring to FIG. 2, YF_Mean, which is reference brightness information, is mapped to Y_Target by flattening the distribution, and the brightness information of pixels existing in a brighter area than YF_Mean and the brightness information of pixels in a darker area of YF_Mean are scaled around YF_Mean. By mapping in response to the factor, the screen is adjusted to the desired brightness.

In FIG. 2, Equation 1 is applied to map the brightness information Ya for any pixel present in the brightness information area larger than YF_Mean to Ya 'by distribution planarization.

Ya '= Ytarget + Range × Scale_Factor

Range = Yend-Ytarget

Scale_Factor = YaSub / YaTotal

In Equation 1, "Yend-Ytarget", which is a Range value, is a region where pixels of a range that are brighter than Ytarget will exist after flattening the distribution, and "YaSub / YaTotal" is a scale factor corresponding to Ya, and is "Yend-Ytarget". Each location is mapped to.

In FIG. 2, Equation 2 below is applied to map the brightness information Yb for any pixel present in the brightness information area smaller than YF_Mean to Yb 'by distribution planarization.

Yb '= Ystart + Range × Scale_Factor

Range = Ytarget-Ystart

Scale_Factor = YbSub / YbTotal

In Equation 2, the range value "Ytarget-Ystart" is a region where pixels of a range darker than Ytarget will exist after flattening the distribution, and "YbSub / YbTotal" is a scale factor corresponding to Yb and is a region of "Ytarget-Ystart". Each location is mapped to.

3 is a block diagram of the flattening device according to the present invention, an embodiment of flattening the distribution by dividing the distribution into 16 blocks.

Referring to FIG. 3, the distribution planarization apparatus of the present invention receives the brightness information YIn of a pixel output from an image sensor (not shown) in response to a clock signal Clk and a frame synchronization signal Vsync. 16 blocks by receiving the brightness average value generation unit 200, the brightness average value from the brightness average value generation unit 200 and the pixel brightness information YIn from the image sensor to obtain the average brightness of the screen displayed on one screen Generating a distribution chart, and outputting the number of pixels for each block, the number of pixels of a block to which the brightness average value output from the screen brightness average value generator 200 belongs, and the number of pixels exceeding and exceeding the brightness average value. The block diagram generation unit 210 and Ytarget, Ystart, Yend, brightness information (YIn) of the pixels, and the image information in response to the information about the number of pixels output from the block diagram generation unit 210. Each block includes a flattening unit 220 for generating a scale factor for each block belonging to the brightness average value and generating a scale factor for each other block to flatten the brightness information of one screen. It will be described in more detail with reference to Figures 4 to 8.

4 is an internal block diagram of the brightness average value generator 200 of the screen according to an embodiment of the present invention, Figure 5 is a signal timing diagram for the brightness average value generator of the screen.

4 and 5, the brightness average value generator 200 sequentially accumulates and receives brightness information YIn of a pixel on a screen in response to a clock signal Clk and accumulates 201 and a clock signal. A latch 202 for storing the accumulated value from the accumulator 201 in response thereto, a counter 203 for counting the number of pixels of brightness information input in response to the clock signal Clk, and a latch in the latch 202. A divider 204 which receives the accumulated value Sum and the count result value Cnt of the counter 203 and divides the count result value Cnt from the cumulative value Sum as the reference brightness information YF_Mean, A latch 205 for storing the reference brightness information YF_Mean of the divider 204 in response to the clock signal Clk and the latches 202 and 205 and the counter 203 in response to the frame synchronization signal Vsync. The control unit 206 controls the operation.

The brightness average value generation unit 200 configured as described above accumulates the brightness information (Yin) of each pixel while being displayed by the frame synchronization signal (Vsync) to obtain an average value of the brightness component (Yin) of the displayed image. The cumulative value is obtained, and reference brightness information YF_Mean, which is a brightness average value, is obtained while not being displayed.

In detail, the controller 206 activates a latch enable signal LatchEn1 that enables the latch 202 during a period in which the accumulator 201 calculates a cumulative value in response to the clock signal Clk. Activates latch enable signal LatchEn2 which enables latch 205 during divider period of divider 204, and latch 202 and counter 203 for accumulation of brightness information of the next screen after divider period. Activate the clear signal (Clear) to make "0".

The divider 204 divides the reference brightness information YF_Mean by dividing the accumulated value Sum stored in the latch 202 as the number of jets and the count result value Cnt stored in the counter 203 as the number of jets. In this case, the divider 204 can use both a parallel divider and a serial divider, and when the serial divider is used, the divider 204 operates in synchronization with the clock signal Clk.

In addition, the latch 205 stores and maintains the reference brightness information YF_Mean from the divider 204 for one screen period in synchronization with the latch enable signal LatchEn2.

FIG. 6 is an internal block diagram of a distribution chart generator 210 for each block according to an embodiment of the present invention. The controller 211 includes sixteen distribution map storage blocks and an incrementer. In response to the control of the block distribution diagram generation unit 212 and the block distribution diagram generation unit 212 and the block distribution diagram generation unit 212 to increment the active block according to the control of the control unit 211 The pixel number output unit 213 outputs the number of pixels for each block, the number of pixels of the block to which the brightness average value belongs, and the number of pixels exceeding and exceeding the brightness average value. In response to the shift enable signal (ShiftEn) from the control unit 211, the distribution of the active block is input from the block distribution generation unit 212 and output by 4-bit shift or the value of the active block is left as it is. The accumulator accumulates in response to the shift and bypass unit 214, the clock signal Clk, and the control signal AccClear from the control unit 211 and sequentially receives the distribution from the block distribution generator 212. 215 and 16 blocks and stores the result of the accumulator 215 in synchronization with the clock signal Clk in a block activated by the control signal DWriteSel from the control unit 211, and the control unit 211 The first storage unit 216 for outputting the number of pixels of the block activated by the control signal (DRead_Cur) from the block, which is composed of 16 blocks accumulated in the block activated by the control signal (MWriteSel) from the control unit 211 The second storage unit 217 and the control unit for storing the result of the unit 215 in synchronization with the clock signal Clk, and outputting the number of pixels of the block activated by the control signal MReadSel from the control unit 211. If the control signal (LowTotal_Wrt) from 211 is activated, The result of the unit 215 is stored in synchronization with the clock signal Clk, the stored value is output, and when the control signal HighTotal_Wrt from the control unit 211 is activated, the result of the accumulator 215 is converted into the clock signal Clk. ) And a third storage unit 218 for storing and synchronously storing the same.

Herein, when the frame synchronization signal Vsync indicates the display time, the controller 211 compares the brightness information Yin of the pixel and the reference brightness information YF_Mean, which is a brightness average value output from the brightness average value generator 200. And a control signal HWriteSel for incrementing a value of the corresponding distribution storage block in the block distribution generator 212 in response to each decoding result, and brightness information of the current pixel stored in the first storage unit 216. Generates the control signals Dread_Cur and Dread_Und in response to the clock signal Clk to control the output of the pixel number UnderDensity accumulated in the blocks belonging to the darker area than the current information of the current pixel density and the brightness of the current pixel. . The controller 211 outputs a control signal AccClear for clearing the value of the accumulator 215 to the accumulator 215 during the period that is not displayed by the frame sync signal Vsync, and generates a block distribution diagram stored during the display period. The control signal HReadSel for reading the value of each distribution storing block in the unit 212 is output to the block distribution generating unit 212. In addition, the control unit 211 controls to selectively store the result of the accumulator 215 in any one of 16 blocks in the first storage unit 216 during the period that is not displayed by the frame synchronization signal Vsync. A control signal MWriteSel is generated for generating the signal DWriteSel and outputting it to the first storage unit 216 and selectively storing the number of pixels of the block to which the brightness average value belongs in one of 16 blocks in the second storage unit 217. Brightness greater than the control signal LowTotal_Wrt and reference brightness information YF_Mean for outputting to the second storage unit 217 and storing the number of pixels having brightness smaller than the reference brightness information YF_Mean in the third storage unit 218. The control signal HighTotal_Wrt for storing the number of pixels having? In the third storage unit 218 is output to the third storage unit 218, respectively.

FIG. 7 is an internal block diagram of the control unit 211. As shown in the drawing, the control unit has 8-bit reference brightness, which is the brightness average value output from the 8-bit brightness information Yin and the brightness average value generation unit 200, and FIG. Comparing unit 300 for receiving and comparing the information (YF_Mean), decode the upper four bits of the 8-bit brightness information (Yin) to select any one of the 16 distribution map storage block in the block distribution generator 212 A first decoder 301 for generating a control signal YblockSel for generating the control signal YinblockSel for selecting any one of the subblocks in the distribution storage block by decoding the lower 4 bits of the 8-bit brightness information Yin. In the block distribution generator 212 in response to the second decoder 302, a control signal DisplayTime indicating a display period, and the control signals YblockSel and YinblockSel output from the first and second decoders 301 and 302. The number of pixels accumulated in the block to which the brightness information of the current pixel stored in the first storage unit 216 and the control signal HWriteSel which increments a value of the corresponding distribution map block are darker than the brightness information of the currentDensity and the current pixel. The first control signal generation unit 303 for outputting the control signals Dread_Cur, Dread_Und, and MReadSel for controlling the output of the pixel number UnderDensity accumulated in the blocks belonging to the block, and generating a block distribution diagram in response to 8-bit reference brightness information YF_mean. An address generator 304 for generating an address signal DblockSel for selecting any one of the 16 distribution blocks in the block 212 and an address signal DinblockSel for selecting any one of the subblocks in the distribution block. In response to the address signals DblockSel and DinblockSel from the address generator 304, each of the components in the block distribution generator 212. The second control signal generator 305 and frame for generating and outputting the control signal HReadSel for reading the value of the storage block and the control signals MWriteSel, DWriteSel, LowTotal_Wrt, and HighTotal_Wrt for controlling the output of the pixel number output unit 213. From the synchronization signal Vsync, the clock signal Clk, and the brightness average value generator 200, the address generator 304 and the second signal are generated in response to the valid signal Mean_Valid indicating that the current reference brightness information YF_mean is valid. The timing controller 306 outputs a plurality of timing control signals for controlling the operation timings of the first and second control signal generators 303 and 305.

Here, the comparison unit 300 outputs the signals YisHigh and YisMeanBlock to the flattening unit 220 as a result of comparing the reference brightness information (YF_Mean) and the brightness information (Yin), and the YisMeanBlock signal is the reference brightness information (YF_Mean) and brightness information. The upper 4 bits of (Yin) are compared and enabled in the same case.

The first control signal generator 303 controls the control signal YblockSel from the first decoder 301 to HWriteSel and DRead_Cur while the control signal DisplayTime indicating that the display period output from the timing controller 306 is enabled is enabled. Outputs a value less than the signal YblockSel to DRead_Und and YinblockSel to MReadSel, respectively, and disables all output signals while the control signal DisplayTime is disabled.

Next, the address generator 304 includes a block counting unit, a sub block counting unit, and a comparison unit to clear the block counting unit and the sub block counting unit in accordance with the control signal IncClr from the timing controller 306, and the control signal IncEn When is enabled, the block counting unit is incremented in synchronization with the clock signal Clk. When the counting value of the block counting unit is equal to YF_Mean [7: 4], the signal MeanBlock is enabled and output to the timing controller 306. The counting unit stops counting the block counting unit, and at the same time, the sub-block counting unit stops counting the clock signal Clk. Increment in synchronization. At this time, if the counting value of the sub block counting unit is equal to YF_Mean [3: 0], the signal YisMean is enabled and output to the timing controller 306. Subsequently, when counting of the sub block counting unit is completed, the signal MeanBlock is disabled again, counting of the block counting unit is started, and when counting of the block counting unit is completed, the signal DensityEnd is enabled and output to the timing controller 306, and the timing controller The operation ends by the control signal IncEn disabled from 306.

Next, the second control signal generator 305 uses the DblockSel from the address generator 304 as HReadSel and DWriteSel while the control signal DensityGenTime output from the timing controller 306 is enabled, and while MeanBlock is enabled. Output DinblockSel to DwriteSel, and enable LowTotal_Wrt when YisMean is enabled and HighTotal_Wrt when DensityEnd is enabled.

Next, the timing controller 306 distinguishes and enables the control signals DisplayTime and DensityGenTime in response to the frame synchronization signal Vsync, and enables IncEn after the IncClr and AccClear are activated when the valid signal Mean_Valid is enabled. . After that, when the enabled Densityend is input from the address generator 304, IncEn is disabled. When the enabled MeanBlock is input from the address generator 304, ShiftEn is enabled to the shift and bypass unit 214. Output When the enabled YisMean is input from the address generator 304, AccClear is enabled to clear the accumulator 215 to accumulate the number of pixels having brightness information larger than YF_Mean.

Next, in the pixel number output unit 213 of FIG. 6, the shift and bypass unit 214 shifts 4 bits to the right when ShiftEn is enabled to obtain the pixel number of the distribution block including YF_Mean to HReadSel. The function of dividing the value of the distribution block selected by the distribution by 16 and the number of pixels stored in the distribution block when disabling ShiftEn is output to the accumulator 215 when obtaining the number of pixels of the distribution block containing YF_Mean. Perform the function. In this case, in one embodiment of the present invention, the total brightness information is divided into 16 blocks, and the brightness information expressed in one block is 16. Here, the shift of the value of the distribution storage block to the right by 4 bits when obtaining the number of pixels of the distribution storage block including YF_Mean is to obtain a scale factor for each pixel in the distribution storage block including YF_Mean.

Finally, the internal configuration and operation of the flattening unit 220 of FIG. 4 will be described.

8 is an internal block diagram of the planarization unit 220 according to an embodiment of the present invention.

As mentioned above, the flattening unit 220 corresponds to the Ytarget, Ystart, Yend, brightness information (Yin) of pixels, and information on the number of pixels output from the distribution chart generator for each block 210 to which the brightness average value belongs. The scale factor is generated for each block and the scale factor is generated for each block, and the brightness information of the pixel inputting the frame sync signal Vsync is delayed to flatten the brightness information for one screen. The latches 400 and 401 for delaying, the latches 402 and 403 for latching the signal YisHigh output from the block-by-block distribution generator 210, and the block-by-block distribution in response to Ystart, Ytarget and Yend defined by the user The range is selected by YisHigh output from the generation unit 210 according to whether the position of brightness information of the pixel is in the brightness region or the dark region than YF_Mean. Generates a scale factor used to change the brightness information of the pixel in response to a plurality of signals output from the range selector 404 and the distribution chart generator 210 for each block and brightness information of the lower 4 bits. A multiplier 406 and a latch 403 that are multiplied by a range 405 and a range output from the range selector 404 and a scale factor output from the scale factor generator 405. In response to YisHigh, the multiplication result from the offset selector 407 and multiplier 406 that selectively outputs Ytarget and Ystart and the output value of the offset selector 407 are added to flatten the brightness information Yin of the pixel. And an adder 408 for finally outputting the brightness information Yout.

The flattening unit 220 formed as described above delays the frame synchronization signal Vsync as much as the brightness information Yin of the input pixel is delayed, and obtains the scale factor from the block diagram generation unit 210 of FIG. 6. The scale factor generator 405 generates a scale factor for two clocks by receiving signals necessary for lowTotal, HighTotal, CurrentDensity, UnderDensity, MeanDensity, and YisMeanBlock in response to the clock signal Clk. Then, the range selector 404 selects a range two clocks later according to Ytarget, Ystart, and Yend defined by the user, multiplies the selected range by the scale factor, and YisHigh identifies whether the area is larger or smaller than YF_Mean. After selecting Ytarget or Ystart as the offset value and adding the result value multiplied by the selected offset value, the brightness information of the flattened distribution pixel is finally output.

FIG. 9 is an internal block diagram of the range selector of FIG. 8. The upper limit boundary selector 500 selects and outputs Yend or Ytarget as an upper limit threshold in response to YisHigh, and a Ytarget or Ystart lower limit in response to YisHigh. The subtractor 502 which subtracts the lower limit boundary value from the lower limit boundary selector 501 from the lower limit boundary selector 501 to select and output the threshold value, and the upper limit boundary value from the upper limit boundary selector 500. It consists of two latches 503 and 504 for delaying the subtraction result value output from 502 in response to the clock signal Clk.

First, the range selector 404 selects Yend and Ytarget or Ytarget and Ystart as the upper and lower boundary values by the upper boundary selector 500 and the lower boundary selector 501 by YisHigh. Obtain "Yend-Ytarget" or "Ytarget-Ystart", delay the subtracted value by two clock signals, and export it as a range value.

FIG. 10 is an internal block diagram illustrating the scale factor generator of FIG. 8.

As mentioned above, the scale factor is a value that is multiplied by the brightness information of the pixel and used to change the brightness information of the pixel.

As illustrated in FIG. 10, the scale factor generator may include a jet number selector 600 and a jet number selector 600 configured to select LowTotal or HighTotal output from the block-by-block distribution generator 210 as jet number values in response to YisHigh. A latch 602 for latching LowTotal or HighTotal output from 600 in response to the clock signal Clk, a subtractor 601 for subtracting UnderDensity from the CurrentDensity output from the block-by-block distribution generator 210, and the subtractor 601 A multiplier 603 for multiplying the subtraction result value and Yin [3: 0], an adder 605 for adding the multiplication result value of the multiplier 603, and an UnderDensity, and an addition result of the adder 605 in response to YisMeanBlock. A pidget number selecting unit 607 that selects and outputs a value or MeanDensity as a pidget number value, a latch 608 for latching a value output from the pidget number selecting unit 607 in response to a clock signal Clk, and the latch 608 In the value output from A latch for dividing the division result of the divider 604 in response to the divider 604 and the clock signal Clk to divide the value output from the latch 602 and outputting the result as a scale factor. 606).

The scale factor generator configured as described above distinguishes darker areas from brighter areas than YF_Mean based on YF_Mean, and applies them based on the number of pixels (output of the latch 602) (YaTotal, YbTotal) present in each area. The ratio of the number of pixels (output of the latch 608) (YaSub, YbSub) existing up to the brightness of the pixel to be output is output in a scale factor. In this case, theoretically, the scale factor ranges from "0" to "1", which is very limited when implemented in digital logic. Therefore, in the present invention, in order to minimize the rounding error caused by the division operation, multiplying YaSub or YbSub by an arbitrary value corresponding to an integer multiple of 2 (that is, after shifting to the left by an arbitrary number) In order to compensate for this, the output of the multiplier 406 multiplied by the range of the range selector 404 and the scale factor is divided by an arbitrary value (that is, shifted to the right by an arbitrary number of digits). do).

On the other hand, as described above, the block-by-block distribution unit 210 equally divides and stores all the areas in which brightness information is divided into 16 equal parts. A subtractor 601 and a multiplier 603 to increase accuracy when generating scale factors. In addition, by linearly unfolding the distribution of the block in which the pixel to be applied through the adder 605 is located, the cumulative value is differently applied according to the degree of pixel position to be applied in the corresponding block. Specifically, CurrentDensity, which is an input of the subtractor 601, has all the number of pixels up to the block in which the applying pixel exists, and UnderDensity includes all the number of pixels up to the block in which the applying pixel exists. The output of " CurrentDensity-UnderDensity " of 601) is the number of all pixels in the block in which the pixel to be applied exists. In the present invention, since the brightness information is based on 8-bit data divided by 256, one block is divided into 16 internal blocks, and when the output of the subtractor 601 is multiplied by Yin [3: 0], The number of pixels up to where the applied pixels are located in the block can be obtained linearly.

In addition, the number of pixels located in the block containing YF_Mean in the 16 distribution map storage blocks is changed based on YF_Mean. For the sake of simplicity, the block corresponding to YF_Mean has all 16 levels classified by brightness information. The number of pixels of the location is classified and stored in advance, and MeanDensity has the information. If the pixel to be applied belongs to a block in which YF_Mean exists, the YisMeanBlock signal is activated and MeanDensity is selected by the pidget number selector 607.

In the present invention made as described above, based on an image system in which brightness information is divided into 256 levels, the distribution map is divided into 256 levels without obtaining distribution maps. It can be implemented by dividing into blocks or 64 blocks, and this can be changed according to the performance of the image system to be implemented.

Although the technical idea of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above-described embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

According to the present invention made as described above, the distribution of the brightness information of each pixel for each predetermined area divided into blocks is stored, the average value of the brightness information of each pixel is used as reference brightness information, and The scale factor is generated by applying the block factor based on the average value, and the distribution factor is flattened using the generated scale factor to increase the contrast to improve image quality and at the same time to realize an excellent effect of reducing the hardware size. .

Claims (7)

In the device for performing the distribution planarization using the block distribution in the image signal processing device, Brightness average value generating means for receiving brightness information of pixels from an external device in response to a clock signal and a frame synchronization signal to obtain a brightness average of a screen displayed on one screen; A brightness average value from the brightness average value generating means and the brightness information of the pixel are received and divided into a plurality of blocks to generate and store a distribution map, and a block to which the number of pixels for each block and the brightness average value output from the brightness average value generating means belong. Distribution block generation and storage means for outputting a number of pixels and a number of pixels having brightness information less than and exceeding the brightness average value; And The brightness value required by the user, first and second factors for determining a dynamic range of the brightness information of the pixel, brightness information of the pixel, and information on the number of pixels output from the block generation and storage means for each block. And a flattening means for generating a scale factor in pixels for the block to which the brightness average value belongs, and generating a scale factor for each block for the remaining blocks to flatten the brightness information of one screen. Distribution planarization device in the image signal processing device comprising a. The method of claim 1, wherein the brightness average value generating means, Accumulating means for sequentially receiving and accumulating brightness information of the pixel on a screen in response to the clock signal; First latch means for storing an accumulated value from said accumulating means in response to said clock signal; Counting means for counting the number of pixels of brightness information input in response to the clock signal; Division means for receiving a cumulative value latched by the first latch means and a count result value of the counting means, dividing the count result value from the cumulative value and outputting the result as a brightness average value of the screen; Second latch means for storing the average brightness value of the screen output from the dividing means in response to the clock signal; And Control means for controlling the operation of said first and second latch means and said counting means in response to said frame synchronization signal; Distribution planarization device in the image signal processing apparatus comprising a. The method of claim 1, wherein the distribution map generation and storage means for each block, Control means; Block distribution generating means for generating a distribution for each block by incrementing the storage block which is activated under the control of the control means, including a plurality of storage blocks and an incrementer; And The number of pixels for each block, the number of pixels of the block to which the brightness average value output from the brightness average value generating means belongs, and the brightness average value exceeding the block distribution degree of the block distribution chart generating means and the control of the control means. It comprises a pixel number output means for outputting the number of pixels with brightness information, The pixel number output means, The distribution distribution of the active storage block in response to the shift enable signal output from the control means is inputted from the block distribution generating unit and shifted by an arbitrary number of bits, or the value accumulated in the active storage block is bypassed as it is. Shift and bypass means; Accumulating means for receiving and accumulating a distribution diagram from said block distribution chart generation means in response to said clock signal and a cumulative clear signal output from said control means; Synchronizing a result value of the accumulating means with the clock signal in a storage unit activated by a first write selection signal from the control means, including the same number of storage units as the number of blocks of the block generation and storage means for each block; The number of pixels stored in the storage unit activated by the first and second read control signals from the control means is darker than the number of pixels accumulated in the block to which the brightness information of the current pixel belongs and the brightness information of the current pixel. First storage means for outputting the number of pixels accumulated in blocks belonging to the brightness region; Synchronizing a result value of the accumulating means to the clock signal in a storage unit activated by a second write selection signal from the control means, including the same number of storage units as the number of blocks of the block generation and storage means for each block; Second storage means for storing the number of pixels stored in the storage unit activated by the third read control signal from the control means as the number of pixels accumulated in the block to which the brightness average value output from the brightness average value generating means belongs; And In response to a first write control signal from the control means to store the result value of the accumulating means in synchronization with the clock signal, output the stored value as the number of pixels having brightness information less than the brightness average value, and the control means Third storage means for storing the resultant value of the accumulating means in synchronization with the clock signal in response to a second write control signal from and outputting the number of pixels having brightness information exceeding the brightness average value, The control means, When the frame synchronization signal indicates a display time, a comparison value between the brightness information of the pixel and the brightness average value output from the brightness average value generating means, and the value of the corresponding storage block in the block distribution chart generating means in response to each decoding result. Outputs an increment enable signal for incrementing; and outputs the first and second read control signals in response to the clock signal, Activate the cumulative clear signal when the frame synchronization signal is not displayed, and activate a fourth read control signal for reading a value of the corresponding storage block in the block distribution chart generating means stored during the display time, And activating the first and second write selection signals and the first and second write control signals. The method of claim 3, wherein the control means, Comparing means for receiving and comparing brightness information of the pixels and brightness average values output from the brightness average value generating means; First decoding means for decoding upper bits of a predetermined size among the brightness information of the pixel and outputting the first bits as a first block selection signal for selecting any one of the storage blocks in the block distribution chart generation means; Second decoding means for decoding the remaining lower bits except the upper bits of the brightness information of the pixel and outputting the second lower bit selection signal for selecting any one of the sub blocks in the storage block to which the brightness average value belongs; First control signal generating means for generating said increment enable signal and said first to third read control signals in response to first and second block selection signals output from said first and second decoding means during a display time; ; A first address signal for selecting any one of the storage blocks in the block distribution chart generating means and a second address for selecting any one of the subblocks in the storage block to which the brightness average value belongs, in response to the brightness average value Address generating means for generating a signal; Generating a second control signal for generating the fourth read control signal, the first and second write selection signals, and the first and second write control signals in response to first and second address signals from the address generating means; Way; And A plurality of controlling the operation timings of the address generating means, the first and second control signal generating means in response to a valid signal indicating the validity of the brightness value of the frame synchronization signal, the clock signal and the brightness average value generating means; Timing control means for outputting a timing control signal of a Distribution planarization device in the image signal processing apparatus comprising a. The method of claim 4, wherein the planarization means, First latch means for delaying the frame synchronization signal for a predetermined time; Second latching means for latching an output signal of said comparing means; Range depending on the brightness value required by the user and the output signal of the comparing means in response to the first and second factors, depending on whether the position of the brightness information of the corresponding pixel is in the brightness region or in the dark region than the brightness average value. Range selection means for selecting a; Scale factor generating means for generating a scale factor used when the brightness information of the pixel is changed; First multiplication means for multiplying a range output from said range selection means with a scale factor output from said scale factor generating means; Offset selection means for selectively outputting a brightness value or the first factor required by the user in response to an output signal of the comparison means to the second latch means; And First adding means for finally outputting flattened brightness information with respect to the brightness information of the pixel by adding a multiplication result value from the first multiplication means and an output value of the offset selecting means Distribution planarization device in the image signal processing apparatus comprising a. The method of claim 5, wherein the range selection means, Upper limit boundary selecting means for selecting and outputting a brightness value required by the second factor or the user as an upper limit threshold value in response to an output signal of the comparing means; Lower limit boundary selecting means for selecting and outputting a brightness value or the first factor required by the user as a lower limit threshold value in response to an output signal of the comparing means; And Subtraction means for subtracting the lower limit boundary value from the lower limit boundary selecting means from the upper limit boundary value from the upper limit boundary selecting means. Distribution planarization device in the image signal processing apparatus comprising a. The method of claim 5, wherein the scale factor generating means, In response to the output signal of the comparing means, the number of pixels having brightness information less than the brightness average value output from the third storage means or the number of pixels having brightness information exceeding the brightness average value is selected and output as the jet number value. Jet number selecting means for performing; Third latch means for latching a signal output from the jet number selecting means in response to the clock signal; Subtraction means for subtracting the number of pixels accumulated in blocks belonging to a brightness region darker than the brightness information of the current pixel from the number of pixels accumulated in the block to which the brightness information of the current pixel output from the first storage means belongs; Second multiplication means for multiplying the subtraction result value of the subtraction means with the lower bits of the brightness information of the pixel; Second addition means for adding the number of pixels accumulated in blocks belonging to a brightness region darker than the multiplication result value of the second multiplication means and the brightness information of the current pixel; The brightness result output from the second adding means or the brightness output from the second storage means in response to an output signal of the comparison means enabled when the brightness average value and the higher bits of the brightness information of the pixel are equal to each other. Pidget number selecting means for selecting and outputting the number of pixels accumulated in the block to which the average value belongs as the pidget value; Fourth latch means for latching a value output from said pidget number selecting means in response to said clock signal; And Division means for dividing the value output from the third latch means from the value output from the fourth latch means, and outputting the divided result in the scale factor in response to the clock signal. Distribution planarization device in the image signal processing apparatus comprising a.