JP5355024B2 - Liquid crystal display device and stereoscopic image display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a liquid crystal display device which prevents the occurrence of ghost caused by a response delay of liquid crystal under a low-temperature environment, and to prevent the occurrence of irregular luminance and irregular intensity of ghost. <P>SOLUTION: The liquid crystal display device includes a control circuit 21A, a source driver 27A, a liquid crystal display panel 28 and a temperature sensor 40. The control circuit 21A has a timing controller 22, a frame memory 23, a computing element 29, a memory 30 for an FFD conversion table and a voltage setting circuit 31. The voltage setting circuit 31 is controlled by the timing controller and applies prescribed voltage to the source driver 27A. The temperature sensor 40 gives a result of temperature detection to the timing controller 22. <P>COPYRIGHT: (C)2010,JPO&amp;INPIT

Description

  The present invention relates to a liquid crystal display device having a plurality of gate lines and a plurality of source lines, and more particularly to a time-division liquid crystal display device that performs stereoscopic display by alternately displaying left and right parallax images.

  For example, as shown in FIG. 1 of Patent Document 1, a conventional time-division liquid crystal stereoscopic image display device includes two light sources that respectively focus on the right and left eyes of an observer, and the liquid crystal display panel is on the right side. When displaying a parallax image for the eye, the right eye light source is turned on in synchronization with it, and when the left eye parallax image is displayed, the light source for the left eye is turned on in synchronization with it, and the left and right parallax images are displayed. Are alternately displayed to display a stereoscopic image. In this device, if two different images are used instead of the left and right parallax images, two different images can be displayed depending on the viewing direction.

JP 2001-66547 A (FIG. 1)

  A conventional time-division liquid crystal stereoscopic image display device has the following problems when used in a mobile phone, for example.

  In order to perform display without generating flicker in the stereoscopic image display device, it is desirable to display the left and right parallax images at a rate close to 60 times per second, and images at a rate close to 120 times / second in total on the left and right It is desirable to rewrite and display.

  However, when such a high-speed display is set under a driving condition in a standard state near 25 ° C., if the display is performed in a low-temperature state close to 0 ° C. as it is, the response speed of the liquid crystal is insufficient and 2 There was a problem that a heavy image (ghost) was generated.

  The present invention has been made to solve the above-mentioned problems, and prevents the occurrence of ghosts caused by the response delay of the liquid crystal in a low temperature environment, and also prevents the occurrence of uneven brightness and ghost intensity. An object of the present invention is to provide a liquid crystal display device.

The liquid crystal display device according to claim 1 of the present invention has a plurality of gate lines and a plurality of source lines, and the environmental temperature is measured in the liquid crystal display device in which pixels are selected by a combination of the gate lines and the source lines. a temperature sensor for a memory for storing the previous image picture data, from said gray scale value of the previous image data and current image data, predetermined to fit the tone values of the current image data on the environmental temperature A conversion table memory for storing first and second data conversion tables to be converted into gradation data, and the first and second data conversion tables corresponding to the environmental temperature are read from the conversion table memory. An arithmetic unit for determining an output gradation, a voltage setting circuit for setting a maximum gradation voltage and a minimum gradation voltage, and the maximum gradation voltage and the minimum gradation voltage. A gradation voltage generation circuit that divides a predetermined voltage width at one gradation interval; and an output of the gradation voltage generation circuit that receives the output of the gradation voltage generation circuit and receives the output gradation determined by the computing unit; The voltage determination circuit for determining the source voltage applied to the source line and the arithmetic unit are controlled to write the data twice for each of the pixels for each frame. In writing, the first output gradation determined using the first data conversion table is written so that the voltage reaches the transmittance corresponding to the current image data, and in the second data writing, A liquid crystal display device including a control device for writing a second output gradation determined by using the second data conversion table so as to maintain the transmittance. In writing data, the minimum transmittance of the liquid crystal at the ambient temperature is set as the minimum transmittance, and the transmittance of the liquid crystal that can be reached within a predetermined time from the minimum transmittance is set as the maximum transmittance. The setting circuit sets, as the maximum gradation voltage and the minimum gradation voltage, voltages that realize the maximum transmittance and the minimum transmittance, respectively, in the second data writing, and the maximum gradation voltage And the minimum gradation voltage are voltages assigned to each gradation of the current image data.

  The liquid crystal display device according to claim 2 of the present invention is a liquid crystal display device having a plurality of gate lines and a plurality of source lines, wherein a pixel is selected by a combination of the gate lines and the source lines. A temperature sensor for measuring the first image data, a memory for storing the previous image data, and converting the gradation values of the previous image data and the current image data into predetermined gradation data so as to conform to the environmental temperature, An arithmetic unit that has a second data conversion table, reads out the gradation data from the first and second data conversion tables corresponding to the environmental temperature measured by the temperature sensor, and determines an output gradation; Based on the environmental temperature measured by the temperature sensor, a control device for controlling the computing unit, a maximum gradation voltage and a maximum voltage for realizing the maximum transmittance and the minimum transmittance of the liquid crystal, respectively. A voltage setting circuit for setting a gradation voltage; a gradation voltage generating circuit for dividing a voltage width defined by the maximum gradation voltage and the minimum gradation voltage at one gradation interval; and the gradation voltage generating circuit And a voltage determining circuit that determines a source voltage to be applied to the source line of the pixel based on the output gradation determined by the computing unit, and the control device includes the computing unit. In this manner, data is written twice to each pixel for each frame, and the computing unit determines a first output gradation using the first data conversion table. The first data writing is performed, and in the second data writing, the second output gradation is determined using the second data conversion table, and the first data writing is performed using the temperature. Environment measured by sensor The first output gradation is determined so that the voltage reaches a maximum transmittance that can be reached within a predetermined time, and the second data writing is performed so as to maintain the maximum transmittance. Determining a second output gradation, the first and second output gradations interpolate the first and second gradation data read from the first and second data conversion tables, respectively; Furthermore, it is set by generating a pseudo gradation by changing the dither pattern with time by frame rate control.

According to the liquid crystal display device of the first aspect of the present invention, even in a low temperature environment of about 0 ° C., even when the reaction speed of the liquid crystal is slow, the transmittance of the liquid crystal that can be reached within a predetermined time is set as the maximum transmittance. Since the target transmittance is virtually reached, the left and right parallax images are mixed to generate a double image (ghost) and the ghost intensity because the transmittance does not reach the target value. Unevenness and brightness unevenness can be prevented. In addition, since a voltage between the maximum gradation voltage and the minimum gradation voltage in the second data writing is assigned to each gradation of the current image data , gradation display with a fine voltage width is possible, and an image is displayed. The number of gradations that can be expressed does not decrease. Therefore, even when a gradation image is displayed, it is possible to display a gentle color and luminance change.

  According to the liquid crystal display device of the second aspect of the present invention, even in a low temperature environment of about 0 ° C., even when the reaction speed of the liquid crystal is slow, the transmittance of the liquid crystal that can be reached within a predetermined time is set as the maximum transmittance. Since the target transmittance is virtually reached, the transmittance does not reach the target value, so that the left and right parallax images are mixed, resulting in ghosting, ghost intensity unevenness, and brightness unevenness. Can be prevented. Further, the computing unit interpolates the read first and second gradation data from the first and second data conversion tables, respectively, and further changes the dither pattern with time by frame rate control to change the pseudo gradation. Since the first and second output gradations are set by generating the first and second output gradations, the first and second output gradations are acquired digitally, so that it is not necessary to change the gradation voltage in an analog manner.

<Prerequisite technology>
Prior to description of the liquid crystal display device according to the present invention, a driving method (FFD) using feedforward control will be described with reference to FIGS. FIG. 1 is a block diagram showing a device configuration when a stereoscopic image display device using FFD is applied to a mobile phone capable of displaying a stereoscopic image.

  A stereoscopic image display device 100 illustrated in FIG. 1 includes a communication device module 1 and a display module 2.

  The communication device module 1 includes a communication device unit 11, a CPU unit 12, and a power source 15 such as a battery. The CPU unit 12 includes a decoder 131, an encoder 13, and a video random access memory (VRAM) 14 that is a video memory.

  The display module 2 includes a backlight blinking driver 20, a control circuit 21, a gate driver 26, a source driver 27, and a liquid crystal display panel 28. The control circuit 21 includes a timing controller 22, a frame memory 23, a decoder 24, a DAC (digital / digital). An analog converter) 25 and an arithmetic unit 29.

  The liquid crystal display panel 28 includes a liquid crystal display unit 281 that alternately displays left and right parallax images, and a light source (not shown) that focuses the left eye when displaying an image for the left eye in synchronization with the left and right parallax images. And when displaying the image for right eyes, it has two types of light sources of the light source (not shown) which condenses on the right eye.

<Basic operation>
Next, the basic operation of the stereoscopic image display apparatus 100 will be described.
The communicator unit 11 of the communicator module 1 receives the stereoscopic image data composed of the right-eye image and the left-eye image from the sender, gives it to the decoder 131 of the CPU unit 12, and decodes it. Right-eye image data and left-eye image data are obtained. Here, the frame input rate of the input image data is limited by the processing capacity and communication speed of the CPU, and here it is 24 times per second on the left and right.

  In the CPU unit 12, the right eye image data and the left eye image data decoded by the decoder 131 are given to the encoder 13, and the encoder 13 performs processing such as run length encoding, Huffman encoding, and discrete cosine conversion again. After each data compression encoding, it is recorded in the VRAM 14 together with data decoding parameters.

  Here, the image data for the right eye and the image data for the left eye displayed on the same display position, that is, on the same gate line on the liquid crystal display panel 28, are compressed as one group and recorded in the VRAM 14 as compressed image data. To do. At this time, if a common parameter is used as a compression / decoding parameter for the left and right image data, the amount of data can be reduced.

  Next, the compressed image data recorded in the VRAM 14 is transferred to the frame memory 23 of the display module 2 together with the data decoding parameters and recorded.

  In the display module 2, it is desirable to display the left and right images at a rate of at least 40 times per second in order to suppress flicker, and the left and right images given 24 times (frames) per second in synchronization with the clock of the timing controller 22. By displaying the input parallax image data alternately and twice in each field within one frame period, each of the left and right images is displayed at a rate of 48 fields / second, for a total of 96 fields / second flicker. Display images without

  Here, in order to suppress flicker, at least each of the left and right images only needs to be 40 fields / second, and display of the left and right images at 48 fields / second satisfies this condition.

  When the right eye image is displayed, the recording data is read from the frame memory 23 by reading the right eye image data one gate line at a time and using the decoding parameters recorded in the frame memory 23. To obtain image data for the right eye.

  The decoded right-eye image data is stored in a line memory (not shown). The data stored in the line memory is sequentially D / A converted in the DAC 25 and stored in a latch circuit (not shown) of the source driver 27. The clock from the timing controller 22 and the gate line selection by the gate driver 26 are performed. Synchronously, it is applied as a gradation voltage to the pixels on the gate line. The above operation is sequentially repeated for each gate line to display the right eye image field.

  Next, the same processing is performed on the left-eye image data to display the left-eye image field, and the same right-eye and left-eye image fields are repeatedly displayed, so that a pair of left and right input image data is displayed. Are alternately displayed in two fields for a one-frame image display.

  In the above description, when the left and right image data is compressed, an example in which each image data is compressed as complete parallax image data and recorded in the VRAM 14 has been described. For example, right-eye image data is treated as complete parallax image data, The left-eye image data may be compressed and recorded only for the difference from the right-eye image data.

  In this case, the image data for the right eye and the image data for the left eye displayed on the same display position, that is, on the same gate line on the liquid crystal display panel 28, are compressed as one group with the same parameters, and used for the right eye. The image data for the left eye is recorded in the VRAM 14 for the difference between the image data for the left eye and the image data for the right eye.

  Further, the memory reading from the frame memory 23 is performed by reading the compressed image data for the right eye and the compressed image data for the left eye displayed on the same gate line together and decoding parameters recorded in the frame memory 23. And the right eye image data and the difference data between the right eye image and the left eye image are obtained.

  When displaying the right-eye image, the right-eye image data is stored in the line memory as it is, and when displaying the left-eye image, the difference data is added to the right-eye image data to the left. The image data for the eye is stored in the line memory.

  The above description has been made on the assumption that the right eye image data and the left eye image data decoded by the decoder 131 are compressed again by the encoder 13, but the data is compressed again in this way. In other words, the storage capacity of the image data storage memory such as the frame memory 23 can be reduced. In other words, by compressing the received data again, the storage capacity of the image data storage memory can be reduced. An inexpensive stereoscopic image display device can be obtained. However, if the image data storage memory has a sufficient storage capacity, or if there is no problem in cost even if a memory with a huge storage capacity is prepared, it is not necessary to compress the received data again. There is no need for compression encoding or decoding processing of the received data.

<Ghost and outline blur prevention>
In the method of displaying stereoscopic images by alternately displaying left and right parallax images, the right-eye image and the left-eye image are displayed at positions slightly shifted in the left-right direction even if they are the same display target. Is done. This is a parallax image , but when displaying a display object whose position is shifted in this way, even if it is a still image, switching between a right eye image and a left eye image is performed as in the case of a moving image. Each time, a change in luminance is required at each pixel, and if the response speed of the liquid crystal is insufficient, ghosts and blurring of the outline may occur.

  In the stereoscopic image display device 100, as described above, the number of times of display in one frame is doubled to prevent flicker, so that the frame display speed is increased and the liquid crystal response speed is likely to be insufficient.

  Therefore, the input image data of the latest field is compared with the gradation value of the image data of the field displayed immediately before, and the latest field to be displayed next from the previous field as the gradation voltage for image display of the latest field. By creating a gradation voltage emphasizing the gradation change to be applied to the liquid crystal display panel 28, the response speed of the liquid crystal with respect to the gradation change is accelerated, and the response delay is compensated.

Hereinafter, compensation processing for accelerating the response speed of the liquid crystal with respect to a change in gradation and compensating for a response delay will be described.
Specifically, as a means for creating a gradation voltage in which gradation change is emphasized, a gradation value conversion table as shown in FIG. 2 is prepared in advance in a predetermined memory (not shown). The calculator 29 shown in FIG. 1 creates an optimum gradation voltage for changing from the current liquid crystal display state to the gradation to be displayed next.

  As shown in FIG. 2, the gradation value conversion table includes gradation values (0 to 255) of image data of the current frame (latest field) and gradation values (0 to 255) of image data of the previous frame (previous field). ) Is set to a gradation value to be given to the liquid crystal display panel 28, and a gradation voltage corresponding to the gradation value is recorded as output data.

  For example, when the gradation value of a pixel in the previous field is “1” and the gradation value to be displayed on the same pixel in the latest field is “2” on the image data, based on the conversion table, The liquid crystal display panel 28 outputs a gradation voltage corresponding to the gradation value “3”. Thus, by setting the gradation voltage that is actually applied to the liquid crystal display panel 28 to be higher than the gradation value on the image data, it is possible to compensate for a delay in the response of the liquid crystal. explain.

<Tone value compensation procedure>
The above-described gradation value compensation is performed using the gradation value conversion table before the decoded left and right image data is stored in the line memory.

Specifically, the process proceeds according to the following procedure.
As described above, in the encoder 13, the image data for the right eye and the image data for the left eye displayed on the same gate line are grouped into one gate line, compressed with the same parameters, and recorded in the VRAM 14. To do.

  The left and right compressed image data is transferred to the frame memory 23 of the display module together with the decoding parameters. From the frame memory 23, the compressed image data for the right eye and the compressed image data for the left eye to be displayed on the same gate line are read out in pairs, and decoded by the decoder 24 to complete complete image data for the right eye and image data for the left eye. Get.

  Then, before the image data for the right eye and the image data for the left eye are stored in the line memory (not shown), the arithmetic unit 29 uses the gradation value conversion table to compensate the gradation value. At this time, the left-eye image data is used as the image data of the previous field in order to compensate the gradation value of the right-eye image data, and the right-eye is used in order to compensate the gradation value of the left-eye image data. The image data can be used as the image data of the previous field.

  That is, when the input image data is a moving image, when the compressed image data recorded in the VRAM 14 is transferred to the frame memory 23, the compressed image data for one field for the right eye is first written in the frame memory 23, and thereafter The compressed image data for one field for the left eye is written with a predetermined time difference. This time difference is determined by using the left-eye image data displayed immediately before in the frame memory 23 in order to use it as left-eye image data at the same display position that is read as a pair with the right-eye image data when decoding the image data. It is for leaving it in.

  As a result, the left-eye image data displayed immediately before and the latest right-eye image data are read as a pair, and the left-eye image data displayed immediately before is used as the image data of the previous field. As a result, the tone value of the right-eye image data can be compensated, so that tone compensation for accelerating the response speed of the liquid crystal can be executed without delay.

  Note that, after reading out one field of the compressed image data for the right eye from the frame memory 23, the compressed image data for the left eye is written in the frame memory 23 and the data is updated. In this case, the previously input compressed image data for the right eye for one field is used as the image data for the previous field.

  Here, the timing of writing compressed image data to the frame memory 23 and reading from the frame memory 23 when the input image data is a moving image is shown in FIG.

  In FIG. 3, the compressed image data for the right eye for n lines and the compressed image data for the left eye for n lines are written in the frame memory 23 during one frame period and displayed on the same gate line. The state in which the compressed image data for the right eye and the compressed data for the left eye are read in pairs is schematically shown.

  In FIG. 3, the compressed image data for the left eye is input first and the compressed image data for the right eye is input later, but the input order may be reversed.

<Preventing uneven brightness and ghost>
<Operation of the entire LCD panel flashing simultaneously>
Here, the configuration of the illumination device of the liquid crystal display panel 28 will be described with reference to FIG.

  As shown in FIG. 4, the liquid crystal display panel 28 has a lighting device called a backlight 50. The backlight 50 includes light sources 52 a and 52 b such as LEDs, and a light guide plate 51 that guides light from the light sources to the liquid crystal display unit 281. The light guide plate 51 has a size corresponding to the size of the entire surface of the liquid crystal display unit 281 and is made of a resin such as plastic or acrylic and has translucency.

  Further, the same number of light sources 52a and 52b are arranged on two opposite sides of the liquid crystal display panel 28, respectively. Here, the light source 52a disposed on the right edge toward the liquid crystal display panel 28 is referred to as a left eye light source, and the light source 52b disposed on the left edge is referred to as a right eye light source. To do.

  The backlight 50 of the liquid crystal display panel 28 is controlled to blink simultaneously on the entire surface of the liquid crystal display unit 281 in synchronization with the frame.

  Here, the blinking control of the backlight 50 is controlled by the backlight blinking driver 20.

  That is, the timing signal from the timing controller 22 to the gate driver 26 is supplied to the gate driver 26. This timing signal is also supplied to the backlight blinking driver 20, and the light sources 52a and 52b are combined with the gate line scan. Blinks.

  More specifically, when scanning a gate line based on right-eye image data, only the right-eye light source 52b is turned on, and when scanning a gate line based on left-eye image data. Control is performed so that only the light source 52a for the left eye is lit.

  In displaying a stereoscopic image, when the above-described simultaneous flashing method of the liquid crystal display panel as described above is employed, the selection time of the gate line, the number of gate lines, and the response characteristics of the liquid crystal must be taken into consideration. Therefore, the response characteristics of the liquid crystal will be described with reference to FIG.

  FIG. 5 is a conceptual diagram showing the relationship between the backlight lighting period for stereoscopic image display and the response characteristics of the liquid crystal, with the horizontal axis representing time and the vertical axis representing liquid crystal transmittance. .

  In the liquid crystal display panel 28 having N gate lines, the liquid crystal display unit 281 has a uniform transmittance L1 on the entire surface as a left eye image, and a transmittance L2 (L1 <L2) on the entire surface as a right eye image. Explained.

  As shown in FIG. 5, the liquid crystal display panel 28 has a transmittance for displaying a left eye image in the entire liquid crystal display unit 281 until time t <b> 0 when the lighting period of the left eye light source ends in the left eye image display period. L1 and the liquid crystal has a luminance corresponding to the transmittance L1. Note that the luminance of the liquid crystal is represented by multiplication of the transmittance of the liquid crystal and the brightness of the backlight.

  From time t0, in order to display a right eye image, an image signal corresponding to the liquid crystal transmittance L2 is sequentially applied from the first gate line by gate scanning. After the gate scan is completed, the right eye light source is turned on for a period from time t1 to time t2.

<Compensation for liquid crystal response delay>
When the response of the liquid crystal is slower than the frame display switching speed, the compensation process for compensating for the response delay described above is performed.

  That is, FIG. 2 is used based on the gradation values of the input image data of the latest field (for example, image data for right eye) and the image data of the field that was displayed immediately before (for example, image data for left eye). Using the gradation value conversion table (compensated gradation data) described above, the gradation voltage for image display in the latest field (in this case, the gradation voltage for image display for the right eye) is emphasized ( Higher), the compensated gradation voltage is given to the liquid crystal display panel 28 to accelerate the response speed of the liquid crystal with respect to the gradation change and compensate for the response delay.

  Here, a mechanism that can compensate for the delay in the response of the liquid crystal by emphasizing the gradation voltage will be described below with reference to FIG.

  FIG. 6 is a conceptual diagram showing changes in the response characteristics of the liquid crystal when the voltages applied to the gate lines (gradation voltage) are V2, V3, V4 and V5 (V2 <V3 <V4 <V5). Yes, the horizontal axis represents time, and the vertical axis represents liquid crystal transmittance. In parallel with this, the timing of boosting from the state of the voltage V1 to the voltage V2 is also shown.

  From FIG. 6, it can be seen that increasing the voltage to V2, V3, V4, V5 increases the response speed in the direction of increasing the transmittance of the liquid crystal, and improves the transmittance in a shorter time.

  Therefore, by increasing the gradation voltage for image display in the latest field higher than the actual image data value, the response speed of the liquid crystal with respect to the gradation change can be accelerated, and the response delay can be compensated.

<About brightness unevenness prevention operation>
As described above, if a characteristic that can increase or decrease the response characteristic of the liquid crystal by changing the voltage (gradation voltage) applied to the gate line is used, the liquid crystal display panel 28 is generated in the gate scan direction. It is also possible to prevent luminance unevenness.

  FIG. 5 illustrates a case where the response of the liquid crystal is slower than the frame display switching speed in order to explain the luminance unevenness that occurs in the gate scan direction.

  For example, it is assumed that one gate line is selected and the time spent until new data (gray scale voltage) is written to the gate line is the gate selection time, and the gate selection time is tg.

  In this case, a time difference of N · tg occurs between the pixels on the first gate line and the pixels on the Nth gate line before the image data is updated. Therefore, at time t1 in FIG. 5, the pixel on the first gate line has passed (t1-t0) time from the start of the response of the liquid crystal, that is, the liquid crystal transmittance starts to change, but the Nth gate Only (t1−t0−N · tg) passes through the pixels on the line. Therefore, at time t1, the elapsed time after the liquid crystal transmittance of the pixel on the first gate line starts to change and the elapsed time after the liquid crystal transmittance of the pixel on the Nth gate line starts to change. There will be a difference.

  Therefore, when the response time of the liquid crystal is longer than (t1−t0−N · tg), that is, in the case of the response characteristics A and B shown in FIG. 5, the liquid crystal of the pixel on the first gate line at time t1. Even if the response is completed and the transmittance is L2, the pixel on the Nth gate line does not complete the response of the liquid crystal, and the transmittance is a value L3 between L1 and L2.

  In this state, when the light source is turned on during the period from time t1 to time t2, the luminance on the pixels on the first gate line is different from that on the Nth gate line. This phenomenon occurs continuously over the entire surface of the liquid crystal display unit 281 and luminance unevenness occurs in the gate scan direction.

  In order to prevent this, it is desirable that the predetermined transmittance L2 is obtained over the entire area of the liquid crystal display unit 281 in the time from the writing time of new data to each gate line to the light source lighting time.

  Here, paying attention again to FIG. 6, V4 is earlier than the case where the voltage applied to the gate line is V3 to reach the transmittance L2 which is the average transmittance during the effective lighting period. This means that the lighting period of the light source can be shortened by using the voltage V4. FIG. 6 also shows a pattern in which the voltage V2 is applied.

  That is, in FIG. 6, the lighting period of the light source in the case of the voltage V3 is indicated by the symbol b, the lighting period of the light source in the case of the voltage V4 is indicated by the symbol a, and by increasing the voltage applied to the gate line, It can be seen that the lighting period of the light source can be shortened.

  In other words, if the voltage applied to the gate line is increased, the lighting period can be set to an early time after the voltage is applied after the gate line is selected. This means that even if the time from the time to the lighting time of the light source is different, the same transmittance, that is, the same screen luminance can be realized if the applied voltage is changed in each gate line corresponding to each time.

  FIG. 7 shows response characteristics A and B ′ when the applied voltage is changed between the first gate line and the Nth gate line, with the horizontal axis representing time and the vertical axis representing liquid crystal. The transmittance is shown.

  In FIG. 7, as in the case of FIG. 5 described above, the time difference of N · tg between the pixel on the first gate line and the pixel on the Nth gate line is updated before the image data is updated. At time t1, the pixel (characteristic A) on the first gate line has passed (t1-t0) time after the liquid crystal transmittance has started to change, but the Nth gate In the pixel (characteristic B ′) on the line, only (t1−t0−N · tg) has passed.

  However, by applying a voltage higher than that of the first gate line to the Nth gate line so that the response is quickened by the time until the light source is turned on, the response characteristic B ′ rises. Is steeper than the response characteristic A, and is close to the transmittance L2 at time t1 (right-eye light source lighting start time), and is transmitted at time t2 (right-eye light source lighting end time). It can be seen that the transmittance L4 is higher than the rate L2.

  Therefore, the average transmittance of the pixels on the first gate line during the right-eye light source lighting period (defined by the area surrounded by the region indicating the lighting period and the curve of the characteristic A in the figure), and the Nth The average transmittance (defined by the area surrounded by the region indicating the lighting period and the curve of the characteristic B ′ in the drawing) of the pixels on the gate line during the right eye light source lighting period is substantially the same, and the liquid crystal display Luminance unevenness that occurs in the gate scan direction of the panel 28 can be prevented.

  In order to compensate the gradation value so that the applied voltage is changed in accordance with the time from the data writing time to the light source lighting time in each gate line of the liquid crystal display panel 28, the gradation value shown in FIG. A conversion table is required for each gate line.

However, in this method, as the gradation value conversion table, when the number of gradations of each pixel is K bits and the number of gate lines is N, the data amount is N · K · 2 ^2K bits. A large memory capacity is required for the memory to be stored.

  Here, since the in-plane state of the liquid crystal display panel 28 continuously changes from the first gate line to the Nth gate line, the gradation value conversion table (compensated gradation data) is 1 It is possible to prepare two of the first gate line and the Nth gate line and obtain the gate line between them by, for example, interpolation processing in the arithmetic unit 29.

  As an interpolation method, for example, weighting in proportion to the gate line number is performed, and proportional interpolation is performed from the gradation value conversion table D1 of the first gate line and the gradation value conversion table DN of the Nth gate line. A gradation value conversion table Dm for the mth gate line is determined (1 <m <N). More specifically, interpolation is performed using an interpolation formula represented by Dm = D1 · (m / N) + DN · (m / N). As a result, the data capacity of the memory for the gradation value conversion table can be reduced.

  Needless to say, the reference data may be prepared not only for two lines of the first gate line and the Nth gate line but also for three or more lines, and interpolation processing may be performed between the respective reference data. Yes. In this case, it is expected that the accuracy of the data created by the interpolation process will increase.

<Variation of brightness unevenness prevention operation>
In the luminance unevenness prevention operation described with reference to FIGS. 6 and 7, a method of changing the applied voltage in accordance with the time from the data writing time to the light source lighting time in each gate line of the liquid crystal display panel 28. However, if the applied voltage is increased, the response speed of the liquid crystal can be increased, but the transmittance may be increased too much. Therefore, the method described below may prevent the transmittance from increasing excessively.

  FIG. 8 is a conceptual diagram showing changes in the response characteristics of the liquid crystal when the voltages applied to the gate lines (gradation voltage) are V2, V3, V4 and V5 (V2 <V3 <V4 <V5). Yes, the horizontal axis represents time, and the vertical axis represents liquid crystal transmittance.

  From FIG. 8, by increasing the voltage to V2, V3, V4, V5, the response speed in the direction of increasing the transmittance of the liquid crystal is increased, and the transmittance is improved in a shorter time. However, at voltages V3, V4, and V5, the transmittance continues to increase past the transmittance L2, which is the average transmittance during the effective lighting period.

  On the other hand, the response characteristic S indicated by the solid line shows the characteristic when the voltage V3 is applied until the transmittance L2 is reached, and maintains the transmittance L2 after reaching the transmittance L2. FIG. 8 also shows an example of a voltage application pattern for obtaining such a response characteristic S.

  As shown in FIG. 8, until the time t0 when the lighting period of the left-eye light source ends in the left-eye image display period, the liquid crystal display panel 28 transmits the transmittance for displaying the left-eye image in the entire liquid crystal display unit 281. L1 and the liquid crystal has a luminance corresponding to the transmittance L1.

  From time t0, an image signal corresponding to the transmittance L2 for displaying the right eye image is sequentially applied from the first gate line by gate scanning. At this time, the first applied voltage to each gate line is V3, which is referred to as a first write voltage, and the application of the first write voltage is referred to as a first write. After the first writing is continued for a predetermined period, the applied voltage is lowered to V2. This is called a second write voltage, and giving the second write voltage is called a second write.

  When this voltage application pattern is compared with the response characteristic S, the transmittance is set to reach L2 from L1 in the period from the start of the first write to the start of the second write (the period of the first write). The first writing period is defined by N · tg.

  In order to obtain such a voltage application pattern, first, the input image data of the latest field is compared with the gradation value of the image data of the field displayed immediately before to obtain the gradation voltage for image display of the latest field. By generating a gradation voltage emphasizing the gradation change from the previous field to the latest field to be displayed next, and applying it to the liquid crystal display panel 28 as the first writing voltage, the response speed of the liquid crystal to the gradation change is increased. Accelerate and compensate for response delays. As shown in FIG. 9, the first write voltage is common to the first gate line and the Nth gate line, and it is not necessary to prepare a gradation value conversion table for each gate line. This is because, in all the gate lines, the gradation value that provides the first writing voltage that reaches L2 within the first writing period is set in the gradation value conversion table.

Thereby, luminance unevenness and ghost intensity unevenness in the gate scan direction can also be prevented.

  Here, as means for creating a gradation voltage in which gradation change is emphasized, the current liquid crystal display is performed by the arithmetic unit 29 shown in FIG. 1 using a gradation value conversion table as shown in FIG. An optimum gradation voltage is created for changing from the state to the gradation to be displayed next.

  Next, when performing the second writing, the input image data for the right eye in the latest field is not emphasized and used in an uncompensated state.

  Thus, since the first writing voltage is set using the gradation value conversion table and the second writing voltage uses the image data of the latest field in an uncompensated state, the liquid crystal transmittance is unnecessarily high. Can be prevented from continuing. Further, the period during which the first writing voltage is applied is easily affected by variations in the liquid crystal and the environment. However, since the first writing voltage is set using the gradation value conversion table, the occurrence of ghost can be suppressed. it can.

  FIG. 9 shows the relationship between the backlight lighting period for displaying a stereoscopic image and the response characteristics of the liquid crystal when the voltage application pattern as described above is used.

  FIG. 9 shows response characteristics A1 and B1 when a voltage application pattern composed of first and second write voltages is applied to the first gate line and the Nth gate line. The axis represents time, and the vertical axis represents liquid crystal transmittance.

  In FIG. 9, the response characteristic A1 is the response characteristic of the pixel on the first gate line, and the response characteristic B1 is the response characteristic of the pixel on the Nth gate line and is on the first gate line. A time difference of N · tg occurs between the pixel and the pixel on the Nth gate line until the image data is updated, and the first writing period in the response characteristic A1 corresponds to the time difference of N · tg. Is set to In this period, the first write voltage is set so as to reach the transmittance L2.

  As a result, when the second writing is started, the desired transmittance L2 is reached, and then when the first writing voltage is lowered to the second writing voltage, the transmittance L2 is maintained.

  In the pixel on the Nth gate line (response characteristic B1), the first writing period starts at the timing when the second writing period starts in the pixel on the first gate line (response characteristic A1). Thus, the first write voltage in the pixel on the Nth gate line is set to a voltage that reaches the transmittance L2 at time t1 (right eye light source lighting start time).

  By using the voltage application pattern as described above, the time during which the transmittance almost reaches the desired transmittance L2 is maintained over the entire surface of the liquid crystal panel 28, so that data writing is performed on each gate line. Even if the time from the time to the lighting time of the light source is different, the same luminance can be realized on the entire surface of the liquid crystal panel 28.

<A. Embodiment 1>
<A-1. Device configuration>
A stereoscopic image display device 100A according to the first embodiment of the present invention will be described with reference to FIGS.

  FIG. 10 is a block diagram showing a device configuration when the present invention is applied to a mobile phone capable of displaying a stereoscopic image. In addition, the same code | symbol is attached | subjected about the structure same as the stereoscopic image display apparatus 100 shown in FIG. 1, and the overlapping description is abbreviate | omitted.

  A stereoscopic image display device 100A illustrated in FIG. 10 includes a communication device module 1 and a display module 2A.

The display module 2A includes a control circuit 21A, a source driver 27A, a liquid crystal display panel 28, and a temperature sensor 40. The control circuit 21A includes a timing controller 22, a frame memory 23, a calculator 29, an FFD conversion table memory 30, and a voltage setting. A circuit 31 is provided. Under the control of the timing controller, the voltage setting circuit 31 provides a predetermined voltage to the source driver 27A, and the temperature sensor 40 is configured to provide a temperature detection result to the timing controller 22. Note that the backlight flashes driver or gate driver, etc., shown in FIG. 1 is omitted.

  The source driver 27A resistively divides the predetermined voltage supplied from the voltage setting circuit 31 to generate a gradation voltage of 256 levels and supply it to the voltage determination circuit 271 and the operation voltage from the arithmetic unit 29. The decoder 273 that decodes the gradation data to be supplied to the voltage determination circuit 271, the buffer 274 that buffers the output of the voltage determination circuit 271, receives the output of the buffer 274, and sequentially applies to each source line of the liquid crystal display panel 28. And a shift register 275 for giving.

<A-2. Device operation>
When stereoscopic image display is performed using the FFD described in the item “Preventing uneven brightness and ghost”, the response speed becomes slow due to an increase in the viscosity of the liquid crystal when the environmental temperature in which the liquid crystal display device is used is low. After the first writing to the gate line, the time until the second writing to the gate line, for example, 1/2 when writing the right eye twice and the left eye twice in a cycle of 60 Hz. The second writing is performed at (60 × 2 × 2) = 4.16 ms, but the liquid crystal state may not reach the target transmittance at this time.

  For example, in the case of a normally white TN (Twist Nematic) mode liquid crystal panel, it is likely to occur when an image changes from black to white where a voltage for accelerating the voltage to 0 V or higher cannot be set. For this reason, in a low temperature environment of about 0 ° C., left and right parallax images are mixed to generate a ghost image, resulting in difficulty in stereoscopic viewing.

To solve this problem, the width of change in the liquid crystal state to be used for display, and Turkey use narrowed to the extent that can be varied within 4.16ms is valid.

Here, the following three methods can be considered to determine the narrowing range.
First, as a first method, the contrast is emphasized, a method of selecting from a state where the transmittance of the liquid crystal is 0 to a responsive state, and as a second method, the brightness is emphasized and the maximum transmittance of 0V is selected. As a third method, there is a method of selecting a region where the liquid crystal can respond in the middle region between the first method and the second method. FIG. 11 schematically shows these.

  FIG. 11 shows the relationship between the transmittance and the gradation voltage in the case of a normally white TN mode liquid crystal panel, where Vo is the minimum transmittance and Vh is the maximum transmittance. In this case, in the first method, the transmittance that can change in 4.16 ms in the environment of 0 ° C. is a transmittance corresponding to between 4 V and 2 V in the steady state (25 ° C.), so Vo = 4V Vh = 2V, and the gradation voltage is set by dividing the voltage between 0 and 255 gradations in 256 steps.

  In the second method, a voltage (0 V) that provides the maximum transmittance is set as the gradation adjustment voltage Vh, and a voltage that corresponds to the transmittance that can be reached in this state from 4.16 ms is defined as Vo. The gradation voltage is set by dividing the voltage into 256 steps from 0 to 255 gradations.

  In the third method, an intermediate voltage between the case of emphasizing contrast and the case of emphasizing brightness, for example, 1 V is set as the voltage Vh and 3.5 V is set as the voltage Vo. The gradation voltage may be set in 256 steps.

  Whichever method is used, the number of gradations that can be expressed in the image is reduced because the range of the liquid crystal state to be used is narrowed. For this reason, when a gradation image is displayed, a gentle color or luminance change cannot be displayed, and a staircase image may appear.

  In order to prevent this, in the second write drive, the field for the first write is the acceleration voltage application field, the field for the second write is the gradation adjustment field, and the voltage setting circuit 31 is between the two fields. It is effective to change the voltages Vo and Vh to be applied to the gradation voltage generation circuit 272 from FIG. 10 so that the number of gradations in the voltage region used for liquid crystal display is substantially equal to room temperature.

  The voltage in the acceleration voltage application field is represented by Vo = 4.5V and Vh = 0V in FIG. 11, and the gradation voltage is set by dividing this voltage into 256 steps from 0 to 255 gradations.

  Hereinafter, taking the case of using the first method as an example, an operation for preventing the occurrence of a ghost in a low temperature environment will be described with reference to the stereoscopic image display device 100A shown in FIG.

  The acceleration voltage field FFD data conversion table (first data conversion table) and the gradation adjustment field FFD data conversion table (second), which are predetermined for each temperature based on the environmental temperature detected by the temperature sensor 40. Are read from the FFD conversion table memory 30 and recorded in an SRAM (Static Random Access Memory) (not shown) in the timing controller 22.

  The acceleration voltage field FFD data conversion table and the gradation adjustment field FFD data conversion table have, for example, the same configuration as the gradation value conversion table described with reference to FIG. 2, and the image data of the current frame (latest field). The gradation value to be given to the liquid crystal display panel 28 is set for the combination of the gradation value (0 to 255) and the gradation value (0 to 255) of the image data of the previous frame (previous field). A gradation voltage corresponding to the gradation value is recorded as output data.

  For example, when the gradation value of a pixel in the previous field is “1” and the gradation value to be displayed on the same pixel in the latest field is “2” on the image data, based on the conversion table, The liquid crystal display panel 28 outputs a gradation voltage corresponding to the gradation value “3”. In this way, since more appropriate data is set based on current and past data, this is referred to as feedforward control. The acceleration voltage field FFD data conversion table and the gradation adjustment field FFD data conversion table are experimentally obtained for each environmental temperature in accordance with the physical property values of the liquid crystal display panel 28.

  Further, the timing controller 22 determines voltages Vo and Vh that determine the voltage width for the acceleration voltage field and voltages Vo and Vh that determine the voltage width for the gradation adjustment field. The timing controller 22 includes a device having a function of a CPU (Central Processing Unit). If the device is programmed on the assumption that the first method is used in advance, the environment of 0 ° C. The voltages Vo and Vh are determined in accordance with the voltage width for the acceleration voltage field and the voltage width for the gradation adjustment field suitable for the above. Needless to say, the environment is not limited to 0 ° C.

  Next, the acceleration voltage field is written as the first writing operation. First, based on the acceleration voltage field voltages Vo and Vh determined by the timing controller 22, the voltage setting circuit 31 generates the voltages Vo and Vh. These voltages are supplied to the resistance dividing circuit of the gradation voltage generating circuit 272 and divided into 256 to set the applied voltage for each gradation of 0 to 255.

  Next, corresponding to the first gate line of the liquid crystal display panel 28, the arithmetic unit 29 reads the gradation data of the previous image and the gradation data of the current image stored in the frame memory 23 via the timing controller 22, Based on the FFD data conversion table for the acceleration voltage field corresponding to the environmental temperature, the gradation data to be actually sent to the voltage determination circuit 271 is determined and supplied to the voltage determination circuit 271 to convert it into a voltage to be applied to each source line. The voltage is sent to the source line via the buffer 274 and the shift register 275.

  This series of operations is performed from the first gate line to the final gate line. During this time, the same value is used for the FFD data conversion table for the acceleration voltage field and the voltages Vo and Vh. However, adjustment may be made for each gate line as necessary.

  Next, the gradation adjustment field is written as the second writing operation. First, the voltages Vo and Vh are generated in the voltage setting circuit 31 based on the voltages Vo and Vh for the gradation adjustment field determined by the timing controller 22. These voltages are supplied to the resistance dividing circuit of the gradation voltage generating circuit 272 and divided into 256 to set the applied voltage for each gradation of 0 to 255.

  Next, corresponding to the first gate line of the liquid crystal display panel 28, the arithmetic unit 29 reads the gradation data of the previous image and the gradation data of the current image stored in the frame memory 23 via the timing controller 22, Based on the FFD data conversion table for the gradation adjustment field corresponding to the environmental temperature, gradation data to be actually sent to the voltage determination circuit 271 is determined, and is supplied to the voltage determination circuit 271 to be converted into a voltage to be applied to each source line. . The voltage is sent to the source line via the buffer 274 and the shift register 275.

  This series of operations is performed from the first gate line to the final gate line. During this period, the same value is used for the FFD data conversion table for the gradation adjustment field and the voltages Vo and Vh.

<A-3. Action and Effect>
FIG. 12 is a diagram showing a change in the transmittance of the liquid crystal panel with respect to the applied gradation voltage, with the horizontal axis indicating time (ms) and the vertical axis indicating the transmittance. The time change of transmittance at 0 ° C., 10 ° C. and 25 ° C. is shown, and the upper part of the figure shows the acceleration voltage for accelerating the response speed of the liquid crystal and the level for gradation adjustment performed after the acceleration. The application state of the adjustment voltage is schematically shown for each temperature.

  As shown in FIG. 12, in the acceleration voltage field writing, which is the first writing operation, the transmittance that can be reached at the ambient temperature detected by the temperature sensor 40 is reached in 4.16 ms by the overdrive technique. To accelerate rapidly. The acceleration voltage suitable for each temperature is different, and therefore the acceleration voltage is determined using an acceleration voltage field FFD data conversion table predetermined for each temperature.

  At an environmental temperature of 0 ° C., in the acceleration voltage field, the voltages Vo and Vh are set to 4.5 V and 0 V, respectively, in order to increase the voltage width. The change in the liquid crystal state from black (0 gradation) to white (255 gradation), which is the slowest response in the TN mode liquid crystal panel, is steady even when a minimum voltage of 0 V is applied at 4.16 ms, as shown in FIG. It only reaches 20% of the transmittance reached in the state (25 ° C.). This transmittance corresponds to a voltage application state of 2 V in a steady state.

  Therefore, at an environmental temperature of 0 ° C., white is defined as 20% of the maximum transmittance, and the voltages Vo and Vh are set so that the applied voltage in the gradation adjustment field is 2V at which 255 gradations is 20% of the transmittance. Set to 4V and 2V respectively.

  Thus, even in the low temperature environment of about 0 ° C., even if the reaction speed of the liquid crystal is slow, it is assumed that the target transmittance is virtually reached, and thereafter, 0 to 255 gradations are obtained based on the transmittance. As shown, since the conversion is performed using the FFD data conversion table for the gradation adjustment field, the ghost image is generated by mixing the left and right parallax images due to the transmittance not reaching the target value. It is possible to prevent the problem that it is difficult to remove.

  In the gradation adjustment field, gradation display with a fine voltage width is possible, and the number of gradations that can be expressed in an image does not decrease. Therefore, even when a gradation image is displayed, it is possible to display a gentle color and luminance change.

  On the other hand, at an environmental temperature of 25 ° C. (steady state), in the acceleration voltage field, the voltages Vo and Vh are set to 4.5 V and 0 V, respectively, in order to increase the voltage width. As shown in FIG. 11, the voltage width used for actual gradation display is 4V to 0V, but the voltage Vo is set to be large in order to realize acceleration by overdrive.

  With this voltage width, an acceleration gradation voltage is determined by the FFD data conversion table for acceleration voltage field, a voltage is generated by the voltage determination circuit 271 (FIG. 10), and sequentially applied to the pixels of the liquid crystal display panel 28. In this case, the change in the liquid crystal state from black (0 gradation) to white (255 gradation), which is the slowest response in the TN mode liquid crystal panel, is achieved by applying the acceleration voltage as shown in FIG. A value close to is reached in 4.16 ms.

  Therefore, at an environmental temperature of 25 ° C., white is defined as the maximum transmittance, and the voltages Vo and Vh are 4 V and 4 V, respectively, so that the applied voltage in the gradation adjustment field is 0 V where 255 gradation is the maximum transmittance. Set to 0V. This is a value suitable for generating a gradation voltage when a still image is displayed. Since a value close to the target transmittance has already been achieved in the acceleration voltage field, the voltage to be applied in the gradation adjustment field may be a voltage that maintains the target transmittance in a steady state, and is close to 0V. is there.

  In the above description, the case where the current image data to be displayed has the maximum gradation is taken as an example, but the same applies to the case where the data is intermediate gradation.

  Further, in the above description, although one of the left and right parallax images is not specified, data is written twice in the acceleration voltage field and the gradation adjustment field for the left parallax image, and then Thus, the ghost of the stereoscopic image can be prevented by writing data to the right parallax image twice in the acceleration voltage field and the gradation adjustment field.

<A-4. Setting method of FFD data conversion table>
Next, a method for setting the acceleration voltage field FFD data conversion table and the gradation adjustment field FFD data conversion table will be described with reference to FIG.

  FIG. 13 is a diagram showing evaluation parallax image data for optimally adjusting the voltage setting in the acceleration voltage field and the voltage setting in the gradation adjustment field, and left-eye image data is shown on the left side in the drawing. The right eye image data is shown on the right side.

  In FIG. 13, the right eye image data is expressed as a plurality of horizontal gradation bars indicating the 0 to 255 gradation steps, and the left eye image data is represented by the width and gradation of the horizontal gradation bar of the right eye image data. In addition to the same horizontal gradation bar, the image is expressed as an image in which a plurality of vertical gradation bars indicating 0 to 255 gradations in stages are added so as to be orthogonal thereto.

  In the adjustment operation, these left and right images are alternately displayed at the same position on the liquid crystal panel. Note that the size of the image is arbitrary.

  When these left and right image data are displayed alternately, the left eye image data area without the vertical gradation bar displays the same image as the left and right images, and the area with the vertical gradation bar differs depending on the location. Tone images are displayed alternately. Therefore, when the FFD data conversion table is optimized, the right-eye image data horizontal gradation bar (gray bar) should be visible to the right eye, but when the FFD data conversion table is not optimized. At the evaluation point R of the image actually viewed by the right eye, a difference in brightness can be seen in the intersecting area due to the influence of the vertical gradation bar of the gradation 159 of the left-eye image on the horizontal gradation bar of the gradation 223. Become.

  Therefore, by adjusting the value of the FFD data conversion table so that a monotonous horizontal gradation bar can be seen by the right eye, it is possible to realize an easy-to-see stereoscopic image display without a double image (ghost).

  In practice, the image data in FIG. 13 is adjusted again by changing the left and right, and this is repeated, and the value of the FFD data conversion table in the most balanced state is set to the optimum value, so that the double image is obtained. It is possible to realize a stereoscopic image display that is not easy to see.

  Note that the check pattern is not limited to the pattern shown in FIG. 13, and there are two adjacent areas of the same gradation on one of the left and right images, and the same gradation as that of one image is located at the opposite position of the other image. The same effect can be obtained if a set of images in which a region and a region having different gradations exist adjacent to each other. Further, the crosstalk value of the stereoscopic image display device can be evaluated by measuring the difference in luminance between the actual two image areas from the direction in which the image of the same gradation can be seen.

<A-5. Modification>
In the above description, in order to simplify the description, the polarity inversion of the applied voltage has not been mentioned, but it goes without saying that the same effect can be obtained even if this is performed.

  In the above description, the stereoscopic image display device that alternately displays the left and right parallax images on the liquid crystal panel in synchronization with the blinking of the left and right backlight light sources has been described. However, a normal 60 FPS (field / second) or 120 FPS is used. A similar effect can be expected to suppress the generation of a double image in a low temperature environment of a liquid crystal display that displays a moving image.

  In the above description, the TN liquid crystal mode of normally white (the transmittance is higher as the absolute value of the electric field intensity applied to the liquid crystal cell is smaller) has been described as an example. The transmittance is lower as the absolute value of the electric field strength applied to is smaller.

  FIG. 14 shows the relationship between the transmittance and the voltage in the case of a normally black liquid crystal panel. When the voltage for the minimum transmittance is Vo and the voltage for the maximum transmittance is Vh, In the method, the transmittance which can be changed in 4.16 ms in the environment of 0 ° C. is a transmittance corresponding to between 0.5 V and 2.5 V in the steady state (25 ° C.), so Vo = 0.5 V Vh = 2.5V, and the gradation voltage is set by dividing this voltage into 0 to 255 gradations in 256 steps. As a result, smooth gradation can be realized even at a temperature of 0 ° C.

  In the above description, in order to increase the contrast of the display image, a voltage for realizing the minimum transmittance is set as the gradation adjustment voltage Vo, and an overdrive acceleration voltage of 4.5 V is used from this liquid crystal state. Thus, the voltage corresponding to the transmittance that can be reached in 4.16 ms was defined as Vh. This has an advantage that a moving image with high contrast can be displayed.

<B. Second Embodiment>
In the first embodiment described above, in order to compensate for the response delay of the liquid crystal particularly in a low temperature environment, the gradation range of displayed white and / or black is narrowed, and gradation display is skipped ( In order to prevent (crushing), the method of manipulating the gradation voltage input to the source driver was shown.

  In the second embodiment, a method of obtaining the same effect by signal processing without operating the gradation voltage will be described.

<B-1. Device configuration>
FIG. 15 is a block diagram showing a device configuration when the present invention is applied to a mobile phone capable of displaying a stereoscopic image. In addition, the same code | symbol is attached | subjected about the structure same as the stereoscopic image display apparatus 100A shown in FIG. 10, and the overlapping description is abbreviate | omitted.

  A stereoscopic image display device 100B illustrated in FIG. 15 includes a communication device module 1 and a display module 2B.

  The display module 2B includes a control circuit 21B, a source driver 27A, a liquid crystal display panel 28, and a temperature sensor 40. The control circuit 21B includes a timing controller 22, a frame memory 23, a calculator 29A, and a voltage setting circuit 31. .

  A major difference from the stereoscopic image display device 100A shown in FIG. 10 is that the voltage setting circuit 31 is independent and does not receive control from the timing controller 22. Further, in the stereoscopic image display apparatus 100A, the acceleration voltage field FFD data conversion table and the gradation adjustment field FFD data conversion table similar to the gradation value conversion table shown in FIG. 2 are provided as LUTs (look-up tables). Although the result of conversion using them is output to the source driver 27A, the calculator 29A has the following functions in this embodiment.

FIG. 16 is a block diagram showing the internal configuration of the calculator 29A.
As the source driver has a higher resolution (the number of input digital bits is larger), the gradation collapse is less likely to occur when the gradation range is narrowed. A case where the key is 8 bits (each RGB) will be described. In addition, this block diagram describes only one of RGB, and it is assumed that there are actually three similar blocks.

  As shown in FIG. 16, the arithmetic unit 29 </ b> A includes an LUT 291, an interpolation block 292, and an FRC (frame rate control) block 293. First, the data 8 bits of the previous image video signal and current image video signal sent from the timing controller 22 (FIG. 15) are separated into upper bits and lower bits by a separation block (not shown). Here, the upper 3 bits (8 ways) and the lower 5 bits (32 ways) are separated.

  The upper 3 bits of current image data and previous image data are used as addresses of the LUT 291.

  The configuration of the LUT 291 is shown in FIGS. The LUT 291 is 8-bit data stored in the memory, and includes an acceleration voltage field conversion table shown in FIG. 17 and a gradation adjustment field conversion table shown in FIG.

  The possible range of 3 bit data is 0 to 7, but 0 to 8 are described in the table. The LUT 291 is characterized in that, in addition to the intersection of the values of the current image and the previous image, a total of four values obtained by adding +1 to each value are obtained.

  Here, taking the case where the previous image is 4 and the current image is 3 in the acceleration voltage field as an example, the following four are output as outputs from the LUT. That is, (3,4) = 65, (4,4) = 110, (3,5) = 45, (4,5) = 85. The value of the LUT is rewritten during a blanking period in which no image needs to be output, according to the value of the temperature sensor.

  The four values acquired by the LUT 291 and the lower 5 bits of the previous image and the current image are sent to the interpolation block 292. The interpolation block 292 outputs 9-bit data from these values by two-dimensional linear interpolation. A specific calculation method is as follows.

  For convenience, the data output from the LUT 291 is a, b, c, d (a = 65, b = 110, c = 45, d = 85 in the above example), and the lower 5 bits of the current image data and the previous image data are X [4: 0] and Y [4: 0].

  First, Qab and Qcd are calculated based on Equations (1) and (2). A 13-bit value is obtained by multiplication from the subtraction value of data a, b, c, and d (8 bits each) and X (5 bits). Thereafter, the higher 9 bits of the calculated value and the doubled data a and c are added to obtain a 9 bit value. Next, as shown in Formula (3), a 14-bit value is obtained by multiplying the subtraction value of the 9-bit value obtained in Formulas (1) and (2) and Y (5 Bit), respectively. 9Bit and Qab are added to obtain 9Bit Qabcd. This value is sent to the next FRC block 293.

  Here, since simple two-dimensional linear interpolation using values of four points is performed, interpolation can be performed relatively easily. The interpolation method of the present invention is not limited to linear interpolation, and other interpolation methods can be used.

  In the FRC block 293, a 6-bit output signal to be supplied to the source driver 27A (FIG. 15) is generated from 9-bit data (Qabcd), and its internal block is shown in FIG.

  The frame rate control in the FRC block 293 is a method of temporally changing a dither pattern for generating a so-called pseudo gradation, so that a desired output gradation can be obtained even if a single pixel is temporally averaged. It is configured.

  As shown in FIG. 19, 9-bit data input from the interpolation block 292 is separated into upper 6-bit data and lower 3-bit data by a separation block (not shown).

  The upper 6-bit data is input to one input of a MUX (multiplexer) 62 that selects an output signal, and the data obtained by adding +1 by the adder 61 is input to the other input.

  Here, the addition processing in the adder 61 does not add when the 6-bit data is the maximum (63), and adds +1 otherwise.

  The MUX 62 outputs the upper 6 bits as it is when the selection signal supplied from the selector 63 is 0, and outputs data obtained by adding +1 when the selection signal is 1.

  On the other hand, the lower 3 bits of data are used to generate a selection signal of the selector 63 for the MUX 62.

  The selector 63 is connected to a 1/5 LUT 65, a 1/4 LUT 67, a 1/3 LUT 69, and a 1/2 LU 71, and a non-inverted signal and an inverted signal output from each LUT are selected corresponding to a lower 3 bit data signal. Output as a signal.

  That is, from the MUX 62, when the 3 bit data signal is 0, 0 is output, when the data signal is 1, the output of the 1/5 LUT 65 is output, and when the data signal is 2, the output of the 1/4 LUT 67 is output. When the data signal is 3, the output of the 1/3 LUT 69 is output. When the data signal is 4, the output of the 1/2 LUT 71 is output. When the data signal is 5, the inverted output of the 1/3 LUT 69 is output. When the data signal is 6, the 1/4 LUT 67 is output. When the data signal is 7, an inverted output of 1/5 LUT 65 is output. These signals are 1 bit.

  Each LUT includes counters F, V, and H of respective decimal numbers, and is configured such that 0 or 1 is selected according to the value of the counter. That is, a quinary counter 64 including counters F, V, and H is connected to the 1/5 LUT 65, and a quaternary counter 67 including counters F, V, and H is connected to the ¼ LUT 67. Is connected to a ternary counter 69 including counters F, V and H, and to the 1/2 LUT 70 is connected to a binary counter 20 including counters F, V and H.

  In the case of the quinary counter 64, it counts from 0 to 4 and then returns to 0. In the case of the quaternary counter 66, it counts from 0 to 3 and then returns to 0. Others are the same. Here, the counter H is counted for each pixel in the horizontal direction, and is reset when one row is completed. The counter V counts for each row and is reset when the last row is finished. The counter F is continuously counted for each frame. In the case of the present invention, one main frame is composed of a right eye frame, a left eye frame, and an acceleration voltage field and an adjustment voltage field, respectively, for a total of 4 subframes. Therefore, it is assumed that the counter F operates every four subframes (one main frame).

  Although signals for incrementing and resetting these counters are separately required, they are not shown as being supplied from the timing controller 22 (FIG. 15).

  1 / n (n = 2, 3, 4, 5) LUT is the number of times the ratio of 1 in the horizontal direction is 1 / n, the ratio of 1 in the vertical direction is 1 / n, and the same pixel in n frames is 1. The data is set so that is once. Specific tables are shown in FIGS.

  20 to 23 show a 1/5 LUT 65, a 1/4 LUT 67, a 1/3 LUT 69, and a 1/2 LU 71, respectively, and a table is constituted by outputs from the respective counters. In the figure, counters F, V, and H are represented as an n-adic F counter, an n-adic V counter, and an n-adic H counter, respectively.

  Thus, in the same frame, the ratio of 1 in terms of area is 1 / n, and 1 / n gradation luminance is displayed. In addition, since the position of a pixel that becomes 1 in time for each frame is switched, a gradation of 1 / n can be expressed on a time average even for the same pixel. In this example, the gradation between the upper 6 bits is 0, 1/5, 1/4, 1/3, 1/2, 2/3, 3/4 and 4 due to the lower 3 bits of the data input to the FRC block 293. / 5. Originally, it is ideal that gradations of 0, 1/8, 1/4, 3/8, 1/2, 5/8, 3/4 and 7/8 are output, but gradation 1 When / 8 is created by the above method, the cycle in which the same pixel is +1 in a still image is 8 frames, and the display is rough overall. Therefore, in this example, the display performance is improved by reducing the number of denominators as much as possible. Of course, the method of taking the denominator and numerator is not limited to this, and it goes without saying that the resolution (number of bits) of the source driver and the number of bits output by the interpolation block 292 can be designed to arbitrary values.

<B-2. Action and Effect>
Next, functions and effects will be described. In the acceleration field, a value to be output is acquired by the acceleration field LUT shown in FIG. 17 based on the current image data and the previous image data.

  That is, the diagonal element (hatching part) of the LUT is a table value when the previous image and the current image are the same, but in the maximum gradation (8, 8) cell, 210 gradations instead of the maximum value of 255 gradations. A slightly low value is set. On the other hand, the minimum gradation (0, 0) cell has 10 gradations instead of the minimum 0 gradation, and is set to a slightly higher value. However, for example, the (8, 0) cell has 255 gradations and is set to a larger value than the (8, 8) cell. The (0,8) cell has 0 gradation, which is smaller than that of the (0,0) cell. The target gradation to be output is determined by the diagonal element portion, and other elements are for overvoltage.

  That is, the diagonal component is a value used when the previous image gradation = the current image gradation, and this is the reference of the output gradation. This is because only this value is theoretically used in the still image of the previous image = current image, and this value is within the gradation range to be displayed. When the response time of the liquid crystal is ideally 0 (infinitely fast response speed), it is not necessary to set an acceleration voltage even when the previous image and the current image are different, so each column of the tables of FIGS. Will have the same value as the diagonal component of the column.

  However, in an actual liquid crystal, due to the response delay, a cell in which the previous image and the current image are different in cells other than the diagonal component is different from the diagonal component (overvoltage is applied). As a method for determining the value, for example, the visual adjustment method using the image described with reference to FIG. 13 is the easiest. Note that the diagonal component is determined before adjustment, but if the desired characteristics (image similar to FIG. 13) cannot be obtained after adjustment, the diagonal component range (gradation 10 to 210) is narrowed and adjusted again. I do.

  Further, in the adjustment field LUT shown in FIG. 18, substantially the same value is set in the column direction, and the same value as the diagonal element for the acceleration field is set in the diagonal element. However, values are set in directions in which the upper right and lower left of each diagonal element accelerate slightly. This slightly different point is for further acceleration when the liquid crystal cannot respond even in the acceleration field. If the response is almost complete in the acceleration field, the same value is used in the column direction. It is set.

  As a result, the gradation range (0-9, 211-255) above and below the diagonal component gradation range (10-210) for the acceleration voltage is originally displayed for the gradation of 0-255. The diagonal components are adjusted so that they can be responded to by their overvoltage if they are used in reverse, that is, the diagonal range of the diagonal components is narrowed to 10 to 210, so that the usable levels of the diagonal components are reduced. The logarithm has decreased. This is solved by performing bit extension (1 bit = 2 times in this example) in the interpolation block 292, and further performing gradation control on the display by the FRC block 293, and the liquid crystal response is slow, such as in a low temperature environment. However, a good display close to the original number of gradations can be obtained.

<B-3. Modification>
The stereoscopic image display device 100B shown in FIG. 15 has a configuration including the frame memory 23. However, using the VRAM of the communication module 1 shown in FIG. 1, the previous image and the current image are alternately or at short time intervals. If it is transmitted to the frame memory, the frame memory becomes unnecessary.

  Further, as in the stereoscopic image display device 100A of FIG. 10, the gradation voltage generation circuit 31 is controlled by the timing controller 22, different voltages are set in the acceleration field and the adjustment field, and as in the present embodiment. Further, when gradation control is performed by FRC, finer settings are possible and display quality is improved.

  That is, when the gradation voltage is also controlled by the gradation voltage generating circuit 31, the gradation voltage can be adjusted so as to suppress the amount of reduction in the range of the diagonal component values shown in FIGS. , Display quality is improved.

  In the above description, it is assumed that the present invention is applied to a liquid crystal stereoscopic image display device that alternately displays left and right parallax images using a liquid crystal display panel. However, the present invention is applied to a moving image-compatible LCD or a field sequential color LCD. Even so, it is effective in suppressing the generation of a double image due to the response delay of the liquid crystal at a low temperature.

  Further, the on-board electronic device is not limited to a mobile phone, but can be applied to a personal computer, a portable game machine, a PDA (Personal Digital Assistant), and the like.

It is a figure which shows the structure of the stereo image display apparatus which concerns on the premise technique of this invention. It is a figure which shows the gradation value conversion table used for the stereo image display apparatus based on the premise technique of this invention. It is a figure explaining the timing of the moving image data processing of the stereo image display apparatus which concerns on the premise technique of this invention. It is a figure explaining the structure of the illuminating device of the liquid crystal display panel which concerns on the premise technique of this invention. It is a conceptual diagram which shows the relationship between the lighting period of the backlight for a three-dimensional image display, and the response characteristic of a liquid crystal. It is a schematic diagram explaining the relationship between the response characteristic of a liquid crystal, and a gate line voltage. It is a conceptual diagram which shows the relationship between the lighting period of the backlight of the stereo image display apparatus which concerns on the premise technique of this invention, and the response characteristic of a liquid crystal. It is a schematic diagram explaining the relationship between the response characteristic of the liquid crystal of the three-dimensional image display apparatus which concerns on the premise technique of this invention, and a gate line voltage. It is a conceptual diagram which shows the relationship between the lighting period of the backlight of the stereo image display apparatus which concerns on the premise technique of this invention, and the response characteristic of a liquid crystal. It is a block diagram which shows the structure of the three-dimensional image display apparatus of Embodiment 1 which concerns on this invention. It is a figure which shows the relationship between the gradation voltage and the transmittance | permeability of a liquid crystal panel in the twice write drive in the three-dimensional image display apparatus of Embodiment 1 which concerns on this invention. It is a figure which shows the time change of the transmittance | permeability of the liquid crystal panel in the twice writing drive in the three-dimensional image display apparatus of Embodiment 1 which concerns on this invention. It is a figure which shows the parallax image for evaluation for adjusting the voltage setting in an acceleration voltage field, and the voltage setting in a gradation adjustment field optimally. It is a figure which shows the relationship between the gradation voltage in the two-time write drive in the three-dimensional image display apparatus of Embodiment 1 which concerns on this invention, and the transmittance | permeability of a liquid crystal panel about the case of a normally black liquid crystal panel. It is a block diagram which shows the structure of the three-dimensional image display apparatus of Embodiment 2 which concerns on this invention. It is a block diagram which shows the internal structure of a calculating unit. It is a figure which shows the table for acceleration voltage fields. It is a figure which shows the table for gradation adjustment fields. It is a block diagram which shows the internal structure of a FRC block. It is a figure which shows 1/5 LUT. It is a figure which shows 1 / 4LUT. It is a figure which shows 1 / 3LUT. It is a figure which shows 1 / 2LUT.

Claims (4)

In a liquid crystal display device having a plurality of gate lines and a plurality of source lines, and a pixel is selected by a combination of the gate lines and the source lines,
A temperature sensor for measuring the ambient temperature;
A memory for storing the previous image picture data,
First and second data conversions for converting the gradation values of the previous image data and the current image data into gradation data predetermined to suit the environmental temperature from the gradation values of the current image data A conversion table memory for storing the table;
An arithmetic unit that reads the first and second data conversion tables corresponding to the environmental temperature from the conversion table memory and determines an output gradation;
A voltage setting circuit for setting a maximum gradation voltage and a minimum gradation voltage;
A gradation voltage generating circuit that divides a voltage width defined by the maximum gradation voltage and the minimum gradation voltage at an interval of one gradation;
A voltage determination circuit that receives an output of the gradation voltage generation circuit and determines a source voltage to be applied to the source line of the pixel based on the output gradation determined by the computing unit;
The arithmetic unit is controlled so that data is written twice to the pixel every frame, and the transmittance corresponding to the current image data is reached in the first data writing. The first output gradation determined by using the first data conversion table is written so as to be a voltage, and the second data conversion table is maintained so as to maintain the transmittance in the second data writing. A liquid crystal display device including a control device for writing a second output gradation determined using
In the second data writing, the control device sets the minimum transmittance of the liquid crystal at the ambient temperature to the minimum transmittance, and the transmittance of the liquid crystal that can be reached within a predetermined time from the minimum transmittance. Set as maximum transmittance,
In the second data writing, the voltage setting circuit sets voltages that realize the maximum transmittance and the minimum transmittance as the maximum gradation voltage and the minimum gradation voltage, respectively, and A liquid crystal display device, wherein a voltage between an adjustment voltage and the minimum gradation voltage is a voltage assigned to each gradation of the current image data. A liquid crystal display device having a plurality of gate lines and a plurality of source lines, wherein a pixel is selected by a combination of the gate lines and the source lines,
A temperature sensor for measuring the ambient temperature;
A memory for storing previous image data;
The first and second data conversion tables for converting the gradation values of the previous image data and the current image data into gradation data determined in advance so as to conform to the environmental temperature, and measured by the temperature sensor An arithmetic unit that reads out the gradation data from the first and second data conversion tables corresponding to the environmental temperature and determines an output gradation;
A control device for controlling the computing unit based on an environmental temperature measured by the temperature sensor;
A voltage setting circuit for setting a maximum gradation voltage and a minimum gradation voltage for realizing the maximum transmittance and the minimum transmittance of the liquid crystal, respectively;
A gradation voltage generating circuit that divides a voltage width defined by the maximum gradation voltage and the minimum gradation voltage at an interval of one gradation;
A voltage determining circuit that receives an output of the gradation voltage generating circuit and determines a source voltage to be applied to the source line of the pixel based on the output gradation determined by the computing unit;
The control device controls the computing unit to write data twice for each pixel for each frame,
The computing unit is
The first output gradation is determined using the first data conversion table, the first data writing is performed, and the second data writing is performed using the second data conversion table. Determines the output gradation of
In the first data writing, the first output gradation is determined so that the voltage reaches the maximum transmittance that can be reached within a predetermined time at the environmental temperature measured by the temperature sensor,
In the second data writing, the second output gradation is determined so as to maintain the maximum transmittance,
The first and second output gradations are:
By interpolating the read first and second gradation data from the first and second data conversion tables, respectively, and further generating a pseudo gradation by changing the dither pattern with time by frame rate control. A liquid crystal display device to be set.   3. The liquid crystal display device according to claim 2, wherein the first and second gradation data are interpolated by the arithmetic unit using two-dimensional linear interpolation. A time-division type stereoscopic image display device for performing stereoscopic display by displaying left and right parallax image data alternately left and right,
The liquid crystal display device according to claim 1 or 2 is used for displaying the left and right parallax image data,
The control device is a stereoscopic image display device that controls the arithmetic unit and writes data twice for each pixel for each field in which one parallax image is displayed.