KR20010103510A - Energy recovery circuit for data drive in a Plasma Display Panel - Google Patents

Abstract

The present invention relates to an energy recovery circuit, comprising: a power supply unit for supplying power to a data driving circuit; A capacitor accumulating energy discharged through the data driving circuit; An inductor coupled between the capacitor and the data driving circuit to form an LC resonant circuit; A first switching element for selectively connecting the capacitor and the inductor; A second switching element for selectively connecting the power supply unit and the data driving circuit; And an energy amount adjusting means for adjusting the amount of energy accumulated in the capacitor.

In addition, according to the present invention as described above, it is possible to reduce the number of switching elements and to increase the data addressing time by eliminating the Sus_down process, and to control the amount of energy recovered by the energy recovery capacitor of the energy recovery circuit. have.

Description

PD recovery data drive energy recovery circuit {Energy recovery circuit for data drive in a Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data driving energy recovery circuit of a PDP. In particular, in a plasma display panel (PDP), a PDP capable of optimally controlling the amount of energy charged in an energy recovery circuit without reducing the number of switching elements and without affecting operation. The data driving energy recovery circuit of the present invention.

In general, a plasma display panel is a light emitting device that displays an image by using a gas discharge phenomenon occurring in each discharge cell. The manufacturing process is simple, the screen is easy to be enlarged, and the response speed is fast. In particular, the image display device has been in the spotlight as a display element of an image display device for the HDTV (High Definition Television) era.

Referring to the configuration, the plasma display panel includes a pair of sustain electrodes and one address electrode (X electrode), each pixel cell comprising a scan / hold (sustain) electrode (Y electrode) and a common sustain (sustain) electrode (Z electrode). M x n pixel matrix.

In addition, the plasma display panel includes an electrode, a dielectric layer, a discharge gas, and the like, which acts as a capacitive, that is, a capacitor, which functions as a charge and a discharge.

On the other hand, the plasma display panel consumes a lot of power during driving, that is, when the panel capacitor is charged and discharged, and such power consumption increases as the inch of the panel increases, which is a major obstacle to the popularization of the plasma display panel.

Therefore, in order to reduce the power consumption of the driving circuit for driving the plasma display panel, it is common to recover and use the energy supplied to the panel. The energy recovery circuit is applied to the sustain waveform to be universally applied to the sustain electrode. In recent years, it has been used for data electrodes.

1 is a diagram schematically illustrating a configuration of a data driving energy recovery circuit of a conventional PDP.

Referring to FIG. 1, a data driving energy recovery circuit of a conventional PDP includes an energy recovery capacitor 101 having one end connected to ground, four switching elements 102, 103, 104, and 105 inductor connected in parallel and in parallel. And an energy recovery unit 100 including a power supply unit (not shown), a logic processing unit 201 for small signal processing, and a gate of an output of the logic processing unit 201 for a field effect transistor (FET) switching operation. It consists of a high voltage processing section 206 composed of two FETs 202 and 203 connected in series as inputs of the parasitic diodes 204 and 205 of the FETs 202 and 203. In addition, the logic processor 201 and the high voltage processor 206 are configured as a data driver IC 200 connected to the same ground.

First, the operation of the energy recovery unit in the data drive energy recovery circuit of the conventional PDP having the above configuration will be described in detail.

When the power of the entire system is turned on at the initial operation of the conventional energy recovery unit 100 and a plurality of discharges continue to occur at the data electrode (not shown), the discharge current of the data electrode is transferred to the energy through the inductor 106. The recovery capacitor 101 is charged, at which time the energy recovery capacitor 101 is charged with the voltage Vs / 2.

The reason why the voltage of Vs / 2 is charged is because energy is supplied and recovered by the balanced switching operation of the second switching element 103 and the fourth switching element 104.

Thereafter, the first switching device 102 is turned on to supply the voltage charged in the energy recovery capacitor 101 to the data driver IC 200 through the inductor 106, and the second switching device 103 is turned on to supply the voltage. Supply (Vs).

Then, the third switching device 104 is turned on to recover the voltage supplied to the data electrode to the energy recovery capacitor 101, and finally, the fourth switching device 105 is turned on to set the ground level. Hold it.

Next, the operation of the data driver IC 200 will be described in connection with the energy recovery unit 100.

2 is a view showing the switching operation and output waveforms of the internal FETs 202 and 203 of the data driver IC 200 constituting the data driving energy recovery circuit of the conventional PDP.

1 and 2, the Vs voltage is supplied from the energy recovery unit 100 only when data is supplied, and the energy recovery operation is performed by recovering the voltage at the data electrode after the voltage supply. That is, data switching is performed according to the scan time.

In more detail, when the operation of the data driver IC 200 is described, the first FET 202 is turned on and started to be supplied from the energy recovery circuit 100 by inputting a high signal of the logic processing unit 201 ( The first FET 202 is turned on until a section (a) and a section (b) maintaining high data, and a voltage is continuously supplied from the energy recovery unit 100.

At this time, the second FET 203 is turned off. Section (c) of FIG. 2 is an operation when data is changed from high to low, and a period for recovering energy supplied to the data electrode to the energy recovery unit 100 through the first FET 202 and the parasitic diode 204. to be.

Referring to this from the side of the energy recovery unit 100, (a) is an ER (Energy Recovery) _up period corresponding to the ON of the first switching device 102 of the energy recovery unit 100 of FIG. (b) is a Sus (Sustain) _up period corresponding to the second switching element 103 turned on.

In addition, (c) is an ER_down section corresponding to the third switching device 104 on, and (d) is a Sus_down section corresponding to the fourth switching device 105 on.

Referring to FIG. 2, the section that actually functions as a data voltage is (b), and the remaining sections (a) (c) and (d) are energy supply and recovery operation sections for efficiently supplying voltage.

Therefore, in order to perform data fast addressing, the sections other than the section (b) should be reduced to the minimum.

However, the energy recovery unit used in the conventional data processing has a large number of switching elements, and there is a problem in the size of the system and the high speed data addressing because of the Sus_down operation, that is, the grounding process.

The present invention has been made to solve the above-mentioned problems, and can optimally control the amount of energy charged in the energy recovery circuit without reducing the number of switching elements in the plasma display panel (PDP) and without affecting the operation. The purpose is to provide a data driving energy recovery circuit of a PDP.

1 is a diagram schematically showing a configuration of a data driving energy recovery circuit of a conventional PDP.

Fig. 2 is a view showing the switching operation and the output waveform of the internal FET of the data driver IC constituting the data driving energy recovery circuit of the conventional PDP.

3 is a diagram schematically showing a configuration of a data driving energy recovery circuit of the PDP of the present invention.

4A to 4C show driving waveforms for driving the data driving energy recovery circuit of the PDP of the present invention.

<Description of the symbols for the main parts of the drawings>

100,300 ... energy recovery unit 101,301 ... energy recovery capacitor

102,103,104,105,302,303,305 ... switching elements

106,304 ... Inductors 200,400 ... Data Driver ICs

201 ... logic processing section

202,203,402,403 ... FET 204,205,404,405 ... parasitic diode

206,406 ... High Pressure Treatment

The data drive energy recovery circuit of the PDP of the present invention for achieving the above object,

A power supply for supplying power to the data driving circuit;

A capacitor accumulating energy discharged through the data driving circuit;

An inductor coupled between the capacitor and the data driving circuit to form an LC resonant circuit;

A first switching element for selectively connecting the capacitor and the inductor;

A second switching element for selectively connecting the power supply unit and the data driving circuit; And

And an energy amount adjusting means for adjusting the amount of energy accumulated in the capacitor.

3 is a diagram schematically showing a configuration of a data driving energy recovery circuit of the PDP of the present invention.

Referring to FIG. 3, the energy recovery circuit of the PDP of the present invention includes an energy recovery capacitor 301, first, second, and third switching elements 302, 303, 305, an inductor 304, and a power supply unit (not shown). The retrieval unit 300, the logic processor 401 for small signal processing, and two FETs 402 and 403 connected in series with an output of the logic processor 401 as a gate for a field effect transistor (FET) switching operation. And a high voltage processing unit 406 including parasitic diodes 404 and 405 of the FETs 402 and 403. In addition, the logic processor 401 and the high voltage processor 406 include a data driver IC 400 connected to the same ground.

4A to 4C are diagrams showing driving waveforms for driving the data driving energy recovery circuit of the PDP of the present invention having the above configuration.

Hereinafter, an operation of the energy recovery circuit of the PDP of the present invention will be described in detail with reference to FIGS. 3 and 4A to 4C.

As shown in the structure of FIG. 3, the data driving energy recovery circuit of the PDP of the present invention omits the Sus_down operation of grounding the node Q as compared with the conventional energy recovery circuit. Therefore, the charge recovery value is automatically changed in the energy recovery capacitor 301 in accordance with the changing data amount.

However, when the energy recovery circuit is driven without the Sus_down operation, the energy level charged in the energy recovery capacitor 301 tends to increase because there is no period in which the node Q point goes down to the ground.

If the data driver IC 400 has a lot of low data, the potential of the node Q point may be low, but it is not more efficient than directly grounding the node Q point.

Therefore, the energy recovery capacitor 301 is required for an adjustment function for initializing the value charged in the energy recovery capacitor 301 or maintaining an arbitrary bias in the energy recovery capacitor 301 while driving the energy recovery circuit. One end is provided with a third switching element 305 connected to the ground.

As mentioned in the conventional problem, the method of directly grounding at the node Q point requires a separate time during the energy recovery circuit driving time. Therefore, in the present invention, the charging value of the energy recovery capacitor 301 is changed from the energy recovery circuit operation. Adjustments were made for periods of no need.

In more detail, in the energy recovery circuit of the present invention, the energy charged in the energy recovery capacitor 301 is drawn out to the ground through the third switching element 305, and in this case, the third switching device extracts the charged energy into the ground. Operation 305 allows the second switching element 303 to be located within the on period, as shown in FIG. 3C.

As described above, in the situation where the voltage Vs is applied to the data driver IC 400, since the charged energy of the energy recovery capacitor 301 is extracted while the first switching element 302 is open, normal energy recovery is performed. The amount of charged energy of the energy recovery capacitor 301 can be adjusted without any additional time while maintaining the operation of the circuit.

In fact, since the time when the third switching element 305 is operated (on) is only about several tens of ns, it has a sufficient time margin to adjust the amount of charged energy of the energy recovery capacitor 301.

In addition, the operating time of the third switching element 305 should be determined in consideration of the amount of change in data. Therefore, the optimal operation time of the third switching element 305 corresponding to the data is determined in consideration of the amount of change in data after system implementation.

In the present invention

According to the data driving energy recovery circuit of the PDP of the present invention as described above,

By eliminating the Sus_down process, the number of switching elements can be reduced, the data addressing time can be increased, and the amount of energy recovered in the energy recovery capacitor of the energy recovery circuit can be adjusted.

Claims (5)

A power supply for supplying power to the data driving circuit; A capacitor accumulating energy discharged through the data driving circuit; An inductor coupled between the capacitor and the data driving circuit to form an LC resonant circuit; A first switching element for selectively connecting the capacitor and the inductor; A second switching element for selectively connecting the power supply unit and the data driving circuit; And And an energy amount adjusting means for adjusting the amount of energy accumulated in the capacitor. The method of claim 1, And the energy amount adjusting means selectively subtracts the energy charged in the capacitor to the ground. The method of claim 1, And said energy amount adjusting means is operated (on) during the period of operation (on) of said second switching element. The method of claim 3, wherein The operation time of the energy amount adjusting means is adjusted according to the amount of energy accumulated in the capacitor PD data recovery energy recovery circuit. The method of claim 1, The amount of energy charged in the capacitor is determined in accordance with the amount of data PDP data driving energy recovery circuit.