KR20010092895A - Family radio service circuit - Google Patents

Abstract

PURPOSE: A family radio service(FRS) circuit is provided to decrease volume and size by composing internal circuits as an ASIC and mount additional functions. CONSTITUTION: A radio receiving unit(10) demodulates a radio wave received from the outside. A radio transmitting unit(20) modulates a signal and transmits the modulated signal to the outside. A frequency synthesizing unit(90) generates a requested frequency for modulating and demodulating a voice signal and data. A voice input unit(30) receives a voice of a user as an electric signal. A power unit(40) supplies power with a certain level. A button input unit(50) receives a value selected by the user as an electric value. An LCD(60) displays state and function of a device. A voice output unit(70) outputs a voice of a call object. An ASIC circuit unit(80) controls a radio communication and each composition element.

Description

Household Radio Circuitry {FAMILY RADIO SERVICE CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a family radio service circuit, and more particularly, to a family radio service circuit in which main circuits are composed of an ASIC to reduce volume and size, and have additional functions.

In general, the Family Radio Service (hereinafter referred to as FRS) is a radio that can be used freely without paying radio bills, although it does not require permission or notification even though it varies from country to country. The frequency of the FRS is 27MHz short-wave frequency (HF) is used, but recently 448MHz (Korea) or 462MHz microwave (UHF) is mainly used.

The FRS using 448MHz or 462MHz microwaves (UHF) uses FM modulation, 0.5W maximum allowable power, 15 channels, and maximum communication distance based on a flat surface without obstacles.

If you frequently communicate wirelessly to friends and colleagues in the outdoors or nearby areas, such as university campuses, you do not have to pay a separate communication fee.

These radios are classified into European-type PMR and US-type FRS, but the electrical specifications (SPEC.) Such as frequency of use (PMR: 446MHz) and communication output are slightly different, and are almost identical in function.

On the other hand, the conventional FRS and PMR is not convenient to use because it is not widely used compared to other mobile communication terminals, such as PCS, city phones or digital mobile communication terminals, and has a disadvantage in that it is inconvenient to carry because of its large volume and weight.

The present invention is to improve the disadvantages described above, it is an object to provide a radio having a small volume and weight consisting of a single chip.

1 is a block diagram showing the configuration of a family radio service circuit according to an embodiment of the present invention.

Figure 2 is a graph showing the waveform when the backlight is turned on in the family radio service circuit according to the present invention.

3 is a graph showing a waveform when a silent signal is output in a family radio service circuit according to the present invention;

4 is a graph illustrating waveforms of a silent signal and a backlight signal in a family radio service circuit according to the present invention;

5 and 6 are graphs showing waveforms when two beeps are output in a family radio service circuit according to the present invention;

7A is a circuit diagram illustrating a power supply unit for detecting a battery low state in a family radio service circuit according to the present invention;

7B and 7C are graphs for explaining waveforms according to FIG. 7A.

8 is a circuit diagram illustrating a method of controlling volume in an ASIC circuit unit according to the present invention.

9 and 10 are graphs for explaining the waveform of a single beep tone in the ASIC circuit section of the present invention.

11 is a graph for explaining the waveform of the double beep tone in the ASIC circuit section of the present invention.

12 is a graph illustrating waveforms related to channel scanning in an ASIC circuit unit of the present invention.

13 is a graph showing an associated waveform when a high tone occurs at the maximum volume level in the ASIC circuit section of the present invention.

14 is a graph showing an associated waveform when low tone occurs at the minimum volume level in the ASIC circuit section of the present invention. 15 is a graph showing an associated waveform when generating three consecutive aftone in the ASIC circuit section of the present invention.

16 is a graph showing the condition of the signal waveform applied in the power saver mode in the ASIC circuit section of the present invention.

17 is a graph showing input timing and related waveforms in an ASIC circuit section of the present invention.

18 is a graph for explaining a method for removing chattering according to an input in an ASIC circuit part of the present invention.

19 is a graph showing a waveform associated with pressing a call button of the family radio service circuit of the present invention.

20 is a graph showing an associated waveform after pressing a call button of a family radio service circuit of the present invention.

Fig. 21 is a graph for explaining the voltage controlled oscillator waveform of the family radio service circuit of the present invention.

FIG. 22 is a graph showing a waveform related to a lock performed in a transmission state in the family radio service circuit of the present invention. FIG.

23 is a graph showing waveforms according to channel changes in a family radio service circuit of the present invention.

24 is a graph showing an associated waveform of a channel scanning mode in the family radio service circuit of the present invention.

25 is a graph showing an associated waveform for explaining a calling function in a family radio service circuit of the present invention.

Fig. 26 is a graph showing an associated waveform for explaining the frequency fixed display function in the family radio service circuit of the present invention.

Fig. 27 is a graph showing a waveform related to a case where a family radio service circuit of the present invention presses a call button in a frequency fixed state. Fig. 28 is a graph showing a waveform related to a case where a family radio service circuit of the present invention presses a call button when a frequency unstable state passes a fixed frequency time;

29 is a block diagram showing a control flow when frequency instability occurs during transmission in the family radio service circuit of the present invention.

30 is a block diagram showing a control flow when frequency instability occurs during reception in a family radio service circuit of the present invention.

FIG. 31 is a graph showing a waveform related to an external disturbance input when a family radio service circuit of the present invention is fixed in frequency; FIG.

32 is a graph showing a waveform associated with an external disturbance input when the family radio service circuit of the present invention is frequency unstable during reception.

33 is a block diagram showing an appearance of an LCD display unit in a family radio service circuit of the present invention.

34 is a block diagram illustrating an appearance of an ASIC circuit unit according to another exemplary embodiment of the present invention.

35 is a block diagram showing a detailed configuration of a family radio service circuit according to another embodiment of the present invention.

36 is a block diagram illustrating a configuration of a sub audio squelch system applied to an ASIC circuit unit according to another exemplary embodiment of the present invention.

37 is a block diagram illustrating a CTCSS tone generator configuration applied to an ASIC circuit unit according to another embodiment of the present invention.

38 is a block diagram illustrating a CTCSS tone detector configuration applied to an ASIC circuit unit according to another exemplary embodiment of the present invention.

39 is a block diagram illustrating a configuration of a power on / off controller applied to a family radio service circuit according to another embodiment of the present invention.

<Explanation of symbols for main parts of drawing>

10: wireless receiver 20: wireless transmitter

30: voice input unit 40: power supply unit

50: button input unit 60: LCD display unit

70: audio output unit 80: ASIC circuit unit

90: frequency generator

A feature of the present invention for achieving the above object is an ASIC circuit unit for controlling each of the components in the wireless radio comprising a wireless communication unit, voice input and output unit, a button input unit, a power supply unit, a display unit, wireless communication A memory for storing data on channel frequencies to be allocated at time of reception; A control block outputting a control signal according to an internal program; A display driver for driving the display unit; An output level control block for controlling the output level of the received voice signal; In order to provide a frequency synthesizer, a divider for dividing an input frequency into a predetermined level, a phase detector for detecting a phase of an input signal, and a charge pump for controlling the oscillation frequency of an external oscillator according to the phase detection result And a frequency fixed detector for detecting whether the frequency is stable and fixed, a buffer for buffering the input clock signal, a reference divider for providing a reference of the phase comparator, and a fan which receives a predetermined clock. Providing a clock driver for releasing it; In addition, a continuous tone coded squelch system for improving call quality such as problems caused by crosstalk; A serial interfacing function to provide system scalability; A family radio service circuit is further characterized by providing a power control function by an electrical signal.

Hereinafter, with reference to the accompanying drawings to explain in detail the life radio circuit according to the present invention.

First embodiment

The first embodiment discloses a case in which the ASIC circuit unit is configured in a 28-pin form according to the present invention.

1 is a block diagram showing the configuration of an FRS circuit according to the present invention, the FRS circuit is a radio receiver 10 for demodulating radio waves received from the outside, and a radio transmitter for modulating a signal and transmitting to the outside 20, a frequency synthesizer 90 for generating a desired frequency, a voice input unit 30 for receiving a user's voice as an electrical signal, and a predetermined level of power for modulating and demodulating voice signals and data. A power supply unit 40, a button input unit 50 for inputting a value selected by the user as an electrical signal, a liquid crystal display unit 60 for displaying the state and function of the device, and a voice output for outputting the voice of the other party And a unit 70, and an ASIC circuit unit 80 for controlling wireless communication and each of the above components.

Each of the above-described components will be described in more detail as follows.

The wireless receiver 10 is connected to an antenna and is connected to a pre-selector filter 12a for impedance matching and to select a predetermined band frequency, and is connected to the line selector filter to amplify a signal without increasing the amount of noise. A low-noise amplifier 14a, a post-selector filter 12b connected to the low-noise amplifier 14a for selecting a predetermined band frequency, and a post-selection filter for improving the selectivity, and a signal A mixer 16 for converting to the first intermediate frequency through matching, an intermediate frequency band pass filter 12c connected to the intermediate frequency band filter 12 for removing unnecessary frequency components, and the intermediate frequency band pass filter ( 12C), an intermediate frequency IC 18 connected to the second intermediate frequency conversion and separating the speech signal therefrom, and the effective signal weak or present in connection therewith. Squelch (SQ) circuitry is included to block the speaker output of unwanted noise signals if not.

In addition, the wireless transmitter 20 receives a voice signal modulated by the carrier from the frequency synthesizer 90 and transmits the signal as a high output signal. 24b, a power amplifier 24a for raising the power level required for the wireless output, and an output low pass filter 22 for transmitting signals only in an available band without affecting other frequency bands. .

The frequency synthesizer 90 is a negative feedback system consisting of a phase comparator, a loop filter, and a voltage controlled oscillator, and synthesizes a desired frequency by adding a programmable frequency divider thereto. That is, the frequency input from the temperature compensated crystal oscillator (TCXO) to the ASIC is divided into a reference frequency by a reference divider inside the ASIC, which is input from the voltage controlled oscillator 28 to divide the frequency inside the ASIC. The frequency divided by the frequency divider is compared with the phase comparator. At this time, the division ratio of the reference divider and the frequency divider is determined from the control block so that a desired frequency is synthesized. When the phase comparator detects a phase difference between two inputs, an input is applied to the charge pump by this difference to generate a control voltage capable of determining the oscillation frequency of the voltage controlled oscillator. Since the control voltage generated by the charge pump is output in the form of a square wave, in order to stabilize the frequency of the voltage controlled oscillator 28, the integrated value is output using the loop filter 29 configured as the low pass filter. That is, by continuously adjusting the charge pump output until there is no phase difference between the two inputs, the correct output frequency is synthesized. When the frequency synthesizer is used in this way, the output of the voltage controlled oscillator is generated in multiples of the reference frequency (for example, 6.25 kHz) divided from the temperature compensated crystal oscillator output providing a stable frequency. A stable result can be obtained. In the circuit, other blocks besides the voltage controlled oscillator 28, the loop filter 29, the temperature compensated frequency oscillator are configured inside the ASIC, and the frequency synthesizer output generates the microwave FRS frequency directly. When the microwave frequency cannot be generated due to the limitation of the technology, the frequency multiplier 26 is used to generate the FRS frequency.

The voice input unit 30 includes a microphone 32 for converting a user's voice into an electrical signal, a voice amplifier 34 for amplifying the voice signal, and a control signal transmitted from the ASIC circuit unit 80. And a first transistor Q1 for allowing or blocking the output of the voice amplifier 34. At this time, in order to minimize unnecessary power consumption in the voice amplifier 34 and to minimize the influence on the peripheral circuit, it is determined whether the operation is activated or deactivated by the reception permission signal from the ASIC.

In addition, the power supply section 40 is for the purpose of detecting the power switch (Power Switch) and the battery voltage level for determining a battery (V_ _BATT), and a supply of the battery power, whether or not to supply power at a predetermined level, First and second resistors R1 and R2 configured as a power sampling circuit, and a constant voltage element for fixing and outputting a voltage level input through the power switch to a predetermined level.

In addition, the button input unit 50 has nine switches in a 3 × 3 matrix form, that is, a signal output terminal for detecting a key input of three columns and an input terminal of three rows cross each other. Input to the ASIC circuit section. At this time, the ASIC circuit unit outputs a key scan signal by sharing the fifteenth to seventeenth terminals which are used as a common output of the LCD driving driver in the ASIC circuit unit in order to detect which of the nine buttons is pressed.

Meanwhile, the LCD display unit 60 receives the control signal and data signal from the ASIC circuit unit 80 to display predetermined data, and the LCD display unit 60 according to the control signal from the ASIC circuit unit 80. And a sixth transistor Q6 for turning on the backlight D3 of the LCD 62.

In addition, the voice output unit 70 includes an amplifier 72 for amplifying and outputting the voice signal of the other party, whose signal level is adjusted and transmitted from the ASIC circuit unit 80, and a speaker 74 for outputting the amplified voice signal. ) And a fourth transistor (Q4) and a fifth transistor for deactivating the operation of the amplifier. In addition, a signal for controlling the amplifier to determine the active and inactive state of the amplifier to detect the power save and transmission mode, or receives the audio mute control signal from the ASIC circuit portion, and includes a diode for correctly delivering.

Meanwhile, the FRS ASIC circuit unit will be described in detail.

The ASIC circuit part according to the present invention is composed of a single chip having 28 pins, and the pin assignment for each pin is as follows.

The first pin is a port to which a busy signal for inputting a valid signal is input, depending on whether a valid signal is input. A high logic level is input when a valid signal is present, and a low logic level is input when there is no valid signal. To generate the correct frequency at the synthesizer, it is an analog port that receives a feedback input of the VCO frequency.

The third pin is the ASIC power supply port, the fourth pin is the analog port to which the phase detector output result in the ASIC is output, the fifth pin is the ground port for the entire ASIC circuit, and the sixth pin is the result of PLL frequency lock. This port outputs a high logic level when the desired frequency is stably fixed, and a low logic level when the desired frequency is fixed.

Pin 7 is a port to which a 12.8 MHz clock signal is input in order to provide a reference frequency for the PLL in the ASIC, Pin 8 is a test port for testing whether an ASIC chip is abnormal, and Pin 9 is an antenna in a transmission mode. This port allows the transmission of the output signal through a low logic level.

The tenth pin is a reset signal input port for resetting the ASIC circuit part during an initial operation, and when the low signal is inputted, the ASIC circuit part is reset, and the eleventh pin is an analog signal input for detecting whether the battery voltage is below an allowable level. Used.

The 12th to 14th pins are ports for receiving a user's key input, and the 15th to 16th pins are ports for outputting a common signal for LCD display, and they are also used as detection signal outputs for key input detection by sharing them. , Pins 18 to 22 are ports for outputting a selection signal for selecting each segment on the LCD.

The twenty-third pin is a port through which a control signal for driving the LCD backlight is output. When a user key input is present, the twenty-third pin turns on the backlight by outputting a high logic level. The 24th pin is a port for outputting a power save control signal. When there is no valid signal input for a predetermined time in the reception mode, the 24th pin is powered every predetermined time so as not to interfere with the effective signal input detection in order to minimize unnecessary power consumption of the receiver. The 25th pin is a port for muting the speaker on reception and muting the microphone on transmission, and is muted when a high logic level is output.

The twenty-sixth pin is a port for outputting a tone or beep sound in pulse form, and the twenty-seventh pin is a port through which an audio signal is input to the volume control block to adjust the speaker output level of the audio signal. This port is for outputting audio signal.

The FRS ASIC circuit having the above-described configuration requires input signals such as power on / off, PTT, channel up, channel down, volume up, volume down, call, voice monitor and lamp on / off, and key lock. For each input, the following operations are performed.

1) Power Key The power key performs the function to turn on / off the power of the FRS circuit. When the power is turned on, ① initial beep sound is output ② the LCD backlight turns on for 5 seconds ③ all the icons on the LCD for 3 seconds ④ Volume control level is set to middle. ⑤ Call channel is adjusted to channel 1.

2) Volume up / down key

The volume up / down keys function to increase or decrease the audio volume level, respectively, and the total volume level is 8 steps, and the level is increased or decreased by about 3.5 dB for each key input. At this time, the lowest volume level is set to have a silence. In addition, two high tones (2 ms) are generated when the volume up key is pressed at the highest volume level and two low tones (500 ms) when the volume down key is pressed at the lowest volume level.

The above-described keys are designed to be operated in all cases except the transmission mode, and have a medium level as the initial level at the time of power-on, and then a single level increase or decrease is performed for a single input of 500 mu s or less. On the other hand, if there is a key input of 500㎳ or more, the volume level decreases or increases every 300㎳ until the key input is interrupted. At this time, the beep sound is generated only when the first key is pressed, and the volume level is maximum / When the minimum level is reached, the volume level remains at the last level even if key input continues.

When the volume up / down key is input, the switching speed of the volume level is 50 ms or less, and there is no noise caused by switching.

3) Channel up / down key

The channel up / down key increases or decreases the transmit / receive frequency, respectively, and increases or decreases by one channel for a single key input of 500 Hz or less, and a channel until another key input exists for a key input of 500 Hz or more. Performs a scanning operation on the valid signal input while switching the signal, and detects the valid signal input during scanning and stops for 7 seconds on this channel to output an audio signal. After the audio signal is output, if no other key input is performed until 7 seconds has elapsed, the scanning continues to the next channel. The channel scanning mode ends when the channel up / down key is pressed, when the PTT key is pressed, when the Call key is pressed, and when the power is turned off.

In addition, volume and ramp key input is allowed in the channel scanning mode, even in this case.

When the channel up key on the last channel or the channel down key on the first channel is pressed, it moves to the first channel and the last channel, respectively. That is, in case of FRS, if there is a channel up signal in channel number 14, it moves to channel 1, and when the channel down signal input is input in channel number 1, it becomes channel number 14, and in case of RMR, channel in channel 8 When the up signal input comes in, it moves to channel number 1, and when the channel down input comes in in channel number 1, the channel number becomes 8.

The first starting channel number is 1 at power up.

4) Call key

The call key can be used in all cases other than the transmission mode. When the call key is pressed, the call key is switched to the transmission mode in the current channel. At this time, only the call signal is transmitted for 2 seconds without transmitting the microphone input signal, that is, the audio signal. do. The call signal consists of two tone frequencies, and the transmit icon is displayed on the LCD while the call signal is being transmitted. 5) Push TO Talk (PTT) key

Pressing the call key switches from a receive or standby mode to a transmit mode, while holding down the call key, a transmission icon is displayed, a transmission path for transmitting an audio signal is connected, and the reception path is disconnected.

If the call key input is interrupted, the audio input path through the microphone is first broken, and the transmission ends after the Roger Beep sound is transmitted.

6) Monitor / light key

The monitor and light keys are operable in all cases except for the transmission mode while the power is turned on, and as shown in FIG. 2, the LCD light is turned on for 10 seconds for a key input of 500 ㎳ or less, and the continuous light Keystrokes will toggle the current state. That is, when the light is turned on, when the light key is input again, the light is turned off at that moment. When the LCD light is turned on, if there is a key input related to transmission (e.g. call button, call button) and other inputs except for the light key input, the LCD light will be turned off for 10 seconds from the moment this key is input. Is extended.

If there is a key input of 500㎳ or more, it switches to monitor mode, and the receiver's audio path opens with or without a valid signal input until the key is released. Hold down to switch to auto monitor mode.

During the monitor mode, the reception icon is displayed on the LCD, and the automatic monitor mode ends when the channel up / down key is pressed, when the monitor key is pressed again for 500 ms or more, and when the power is turned off.

In addition, when the monitor key is pressed below 500 ms again in the automatic monitor mode, it recognizes only the light key input, and in the monitor mode, the LCD backlight is turned on for 10 seconds.

7) lock key

If the lock key is pressed for more than 1 second, the input for the channel up / down key is ignored, and when the key is locked, the channel movement including channel scan is prohibited, and the user can confirm the key lock state. Display a lock key icon on the LCD.

When there is a channel up / down input in the key lock state, two high tones (2㎑) are generated by the alarm beep as shown in FIG. 5, and the key lock input is reset for more than 1 second to release the key lock state. On the other hand, the ASIC circuit unit 80 provides a PLL block for a frequency synthesizer, and excites from internal ROM for inputs such as model selection, call, channel up / down, and channel scan. After selecting the corresponding PLL data, set the value on the programmable counter to determine the VCO output frequency, and its contents are displayed as a channel on the LCD display. Same as 1.

Table 1 shows the frequencies required for PMR and FRS when the intermediate frequency is 21.4 MHz and low injection.

In addition, if there is a limit of the VCO frequency feedback input in the configuration of the ASIC circuit, the VCO frequency can be multiplied by two, and in this case, the VCO frequencies of the PMR and FRS are shown in Table 2, and accordingly, data for controlling the programmable counter. Is stored in the ROM.

PMR FRS No. frequency First Receive Local Frequency frequency First Receive Local Frequency One 446.00625MHz 424.60625MHz 462.5625MHz 441.1625MHz 2 446.01875 MHz 424.61875MHz 462.5875MHz 441.1875MHz 3 446.03 125 MHz 424.63 125 MHz 462.6125MHz 441.2125MHz 4 446.04375 MHz 424.64375 MHz 462.6375MHz 441.2375MHz 5 446.05625MHz 424.65625MHz 462.6625MHz 441.2625MHz 6 446.06875 MHz 424.66875MHz 462.6875 MHz 441.2875MHz 7 446.08 125MHz 424.68 125 MHz 462.7125MHz 441.3125MHz 8 446.09375MHz 424.69375MHz 467.5625MHz 446.1625MHz 9 467.5875MHz 446.1875MHz 10 467.6125MHz 446.2125MHz 11 467.6375MHz 446.2375MHz 12 467.6625MHz 446.2625MHz 13 467.6875MHz 446.2875MHz 14 467.7125MHz 446.3125MHz

In addition, the operating frequency of PMR and FRS is selected according to the key input. In the case of the call key, the transmission frequency corresponding to the current channel is selected. In the case of the channel up key, the channel interval is higher than the frequency used by the current channel. , FRS: selects a channel of increased frequency by 25 kHz), and returns to the first channel for the last channel, for example, for PMR 8 and FRS 14.

PMR FRS No. Transmission frequency Receiving frequency Transmission frequency Receiving frequency One 223.003125MHz 212.303 125 MHz 231.28 125 MHz 220.58125MHz 2 223.009375MHz 212.309375 MHz 231.29375 MHz 220.59375MHz 3 223.015625MHz 212.315625MHz 231.30625MHz 220.60625MHz 4 223.021875MHz 212.321 875 MHz 231.31875MHz 220.61875MHz 5 223.028125MHz 212.328 125 MHz 231.33 125 MHz 220.63125MHz 6 223.034375MHz 212.334 375MHz 231.34375MHz 220.64375MHz 7 223.040625MHz 212.340625MHz 231.35625MHz 220.65625MHz 8 223.046875MHz 212.346875MHz 233.78 125 MHz 223.08 125 MHz 9 233.79375 MHz 223.09375MHz 10 233.80625MHz 223.10625MHz 11 233.81875MHz 223.11875MHz 12 233.83 125 MHz 223.13125 MHz 13 233.84375 MHz 223.14375MHz 14 233.85625MHz 223.15625MHz

In the case of channel down, a channel having a frequency reduced by the channel interval is selected from the current channel. In case of the first channel, the channel is returned to the last channel, for example, 8 for PMR and 14 for FRS.

The channel scan mode, which searches for valid signal input while sequentially changing channels at regular intervals, starts when the channel up key or the channel down key is pressed for 500 ms or more.

In particular, when the channel up key is pressed, the channel is scanned in the increasing direction, and when the channel down key is pressed, the channel is scanned in the decreasing direction. Check

If a channel busy signal is detected, the system stops for 7 seconds on the current channel and outputs an audio signal. If there is no key input until 7 seconds have elapsed after the audio output, it moves to the next channel again and resumes scanning. When the call key is input, the scanning mode ends after transmission in the current channel (the channel displayed on the LCD), and when the call key is input, the scanning mode is also terminated after transmission on the current channel. When the volume and lamp keys are entered, the scanning mode continues and the volume and ramp functions are executed, when the channel up / down key is pressed, the scanning mode is terminated on the current channel, and when the monitor key is pressed. Do not allow key entry.

If there is no busy signal, scanning continues to the next channel. At this time, if there is a channel up / down key input, the scanning mode is terminated in the current channel. If a call key or a call key is input, the key is pressed. It does not accept input and outputs two high tone alarm beeps, as in FIG. Even in this case, when the volume and lamp keys are entered, the scanning mode continues, the volume and lamp functions are performed, and the monitor key does not allow key input.

In addition, the conditions for ending the channel scanning mode are when the channel up / down key is pressed regardless of the presence or absence of the busy signal, when the call key and the call key are pressed when there is a busy signal, and when the power is turned off.

In such a case, the frequency generator for generating the desired frequency is composed of a reference divider, a programmable frequency divider, a phase detector, a charge pump, and a frequency fixedness detector in an ASIC circuit. It is made, including.

In frequency selection, the ASIC internal charge pump is configured to have sufficient current drive capability for fast frequency settling times.

The FRS ASIC circuit according to the present invention includes a circuit portion for an additional function, which will be described.

1) Battery low voltage detection

As shown in FIG. 7A, the voltage level of the battery is input for a predetermined time, for example, every 500 mA and compared with a predetermined reference voltage. When the battery voltage level is lower than the reference voltage, the battery low icon on the LCD blinks at an interval of 500 mA. Is displayed. That is, when 1 / n V _DD > V _r , there is no change on the LCD.

When 1 / n V _DD <V _r , the battery low icon blinks at 500 ms intervals on the LCD. In this case, n is a voltage division ratio determined by a predetermined resistor for the ASIC input of the battery voltage, r is the first letter of the reference voltage (Reference Voltage), V _r is the reference voltage.

In addition, as shown in FIGS. 7B and 7C, the reference voltage inside the ASIC chip for detecting the battery low voltage state is used by internally distributing the output of the constant voltage device, so that the battery has a tolerance within ± 50 kV. When the input voltage of the constant voltage device drops below a certain level due to the voltage drop, the output voltage of the device also decreases, thereby minimizing the effect of detecting the battery low voltage.

If the low battery icon is displayed on the LCD, there should be no confusion caused by battery voltage fluctuations. That is, when a battery low voltage state is temporarily detected at the time of transmission or output of the maximum audio signal, the low battery output state is maintained even if the battery voltage is recovered from the maximum transmission and audio output.

2) volume control

The audio signal output from the intermediate frequency IC is adjusted at the volume control block configured inside the ASIC circuit, and the volume control block is composed of selectable resistors and amplifiers, and has a total of 8 steps including silence. Is designed. At this time, each step should be increased or decreased by about 3.5dB depending on the resistance value.

When the beep is output, the audio amplifier input is made through the volume control block so that the speaker output is made according to the current audio volume level. At this time, the beep tone level output from the control block has the same level as the intermediate frequency output audio level. It is designed to have. The audio level input to the ASIC typically has a maximum value of 130dB _rms . If there is no busy input signal, there is an audio output control circuit according to the busy signal in order to prevent noise present in the audio output pin of the intermediate frequency IC through the audio path when the beep is output.

① If there is busy signal: Audio output at the current volume level, there is no beeptone output,

② If there is no busy signal: Only the tone is output at the current volume level without audio output (mute).

3) Beeftone Output Control

When outputting a beep tone in the reception state, it checks for the presence of a busy signal to determine the beep output.If the audio path is open, it does not output the beep tone, but only when the threshold tone, that is, the audio level is at the maximum or minimum, If an error input, such as increasing or decreasing the audio level, is received, the beep tone is output with the audio path open.

In addition, a single beep tone of 1 ms and 100 ms is generated when there is no busy signal for all key inputs except for a call key and a call key.

As shown in FIG. 9, other inputs except for the ramp key generate a beep tone when a key input is input, and in the case of channel up / down, mute the audio regardless of the busy signal, and generate a beep tone. As in the case of the ramp key, a beep tone is generated when the key input is terminated.

As shown in FIG. 11, when the double beep tone is output twice, the tone of 1 ㎑ and 100 ㎳ is output twice, when the channel scanning mode is started, as shown in FIG. 12, when switching from the manual monitor mode to the automatic monitor mode. . As shown in FIG. 13, a double beep tone in which 2 tones and 100 tones are output twice is outputted at the maximum volume level. As shown in FIG. The double beep tone is generated when the volume down key is pressed at the minimum volume level.

As shown in FIG. 15, triple tones are generated during power up.

4) Silence / Power Save Control

When there is no valid signal input in the reception mode, a power save signal is output for audio muting and power saving, and a power save signal is output in the transmission mode and the power saving mode to prevent power consumption. When there is no valid signal at the time of reception, the audio mute signal is outputted, and when the end of transmission is loaded with a Roger beptone on the carrier, a transmission mute signal is output to prevent audio input through the microphone. The audio mute control proceeds as follows:

If there is no busy signal input in the receiving state, the unit enters the call waiting mode and removes the audio output of the intermediate frequency IC through the volume control block of the ASIC to prevent audio output. Prevents speaker output and disables audio amplifiers by using silent signal output.

When switching to the monitor mode, an audio signal is output from the volume control block at the current volume level regardless of the busy signal input until the end, and the audio amplifier is activated by terminating the silent signal output.

When the beep tone is output in the reception state, if there is no busy signal, only the silent signal output is terminated in the absence of the audio signal output through the volume control block, the audio amplifier is activated, and the tone output is performed.

Meanwhile, the power save control will be described as follows.

If the call standby mode is held for more than 10 seconds, the power save icon blinks on the LCD until any key input or signal is detected, and there is no signal and key input for 10 seconds or longer in the standby mode. The whole set goes from call waiting mode to power saving mode.

In addition, in the power saving mode, the power of the receiving circuit is controlled through the power save pin output to minimize battery consumption. In this case, the power save output is turned on / off at an appropriate timing so as not to lose a valid signal newly received in the power saving state. Should be off.

In order to prevent unnecessary power consumption and malfunction during transmission, the power of the receiving circuit is controlled by using the power save pin output.

Here, as shown in FIG. 16, after 10 seconds of the call waiting time, the power saving time condition is 300 ms in the on time and 700 ms in the off time. Proceed according to.

Meanwhile, the main timing used in the FRS ASIC circuit according to the present invention will be described in detail as follows.

1) general specification

As shown in FIG. 17, since input is received in a key scan method using a 3 × 3 key matrix due to limitations of the ASIC input port at the input timing, three signals are sequentially scanned and input for each input port. It is necessary to determine the scan timing for each signal. Since the key scan signal output is made by the output pin of the LCD driving circuit, the key scan signal is output in conjunction with this to determine the scan timing.

As shown in FIG. 18, since chattering occurs when the external key is turned on or off, a chattering prevention circuit is required to prevent malfunctions. Alternatively, if it recognizes only at the high level, it is necessary to determine the timing accordingly, and the definition of the minimum key detection time, that is, the time constraint according to the input scanning timing, should also be considered. This timing is determined by the performance of each block provided during ASIC fabrication.

2) special key function

The call key is an input for transmitting / receiving switching.When the call key is input, the call key is switched from the receive mode to the transmit mode.When the call key input is completed, the transmission mode is terminated after the Roger beep is transmitted. The timing of the main circuit is shown in FIG.

As shown in FIG. 20, the transmission allowance signal should be output at 100 kHz after the call key input. In this case, if the frequency stabilization and the fixed time become longer, the output transient time will be affected. The power should reach (final output power-1dB). In this case, as shown in Fig. 21, there should be no frequency instability, and the VCO frequency must be sufficiently stable before outputting a transmission permission signal to satisfy such a condition.

Therefore, the PLL frequency lock time must be fast enough, and the VCO frequency must be fully stabilized before the transmit permission signal is output (within 100 Hz), and the timing of detecting the frequency lock state must be correctly processed. If, as shown in Figure 22, the frequency lock is not performed for 100 kHz after the PLL data output, the system should be switched to the receiving state, and continues to check the presence or absence of the frequency fixed for 100 kHz even in the receiving state.

In this case, if the frequency is not fixed, the current channel on the LCD display blinks every 500 ms to indicate that the frequency is unlocked.

Here, if frequency stabilization and fixation are performed in the transmission state, the transmission permission signal must be output after 100 kHz after the PLL data output.

In addition, the channel up / down key is used to up or down the call channel, and is defined as a short input and a long input according to a key input condition. As shown in FIG. 23, the short input is a single input of 500 dB or less. And increase or decrease by one channel for a key input, and as shown in FIG. 24, the long input is a single input of 500 Hz or more, and channel scanning is performed for the key input.

On the other hand, as shown in Figure 25, the calling function performs the operation of transmitting two different beepstone in the current channel to call the other party.

And, as shown in FIG. 26, the frequency stable and fixed detection function is used as an output for indicating whether the PLL frequency is stable or fixed when a key input occurs, and as shown in FIG. 27, when the PLL is fixed in frequency, as shown in FIG. When the signal level is unstable, a low level signal is output as shown in FIG. The function indicates frequency stabilization for calls, channel up / down, calls, scan inputs or external disturbances. In addition, the transmit key such as call key, call key, and receive key such as channel up / down, scan should be frequency stabilized and fixed within 100㎳ after PLL data release.If frequency instability occurs, process as follows. .

First, if frequency instability occurs during transmission

After outputting the transmission frequency data, if the frequency is not fixed within 100 kHz, it is converted to the receiving state.If the frequency is not fixed within 100 kHz again after outputting the receiving frequency data, the current channel part on the LCD is displayed. Flashes at 500 ㎳ cycle to indicate frequency instability and continuously performs frequency fixed detection. Subsequently, when frequency fixing is made, the frequency instability indication is removed from the stable point of time. In this case, when the frequency is unstable, switching to the call standby mode or the power saving mode cannot be performed. If the frequency is fixed in the reception state thereafter, the reception state is maintained on the current channel until another input is made. When unlocking occurs on reception

First, in case of frequency instability during reception, after receiving frequency data again, if the frequency is not stable within 100Hz from this point, the current channel part on the LCD blinks at 500㎳ period to indicate frequency instability. After frequency lock detection is performed, the frequency instability indication is then removed at this point if frequency lock is performed. At this time, when the frequency is unstable, no call waiting or power saving operation is performed. After that, when frequency stabilization is performed in the reception state, the reception state is maintained in the current channel until another input is present. Here, in order to satisfy the transient time when the transmission mode is switched, it must have a sufficiently stabilized frequency within 100 kHz. Therefore, a fast frequency fixed time is required, and even when the frequency is unstable in the reception mode, when a call key or a call key is input, the transmission is switched first. If the frequency is fixed, the transmission is normally performed. If the frequency is unstable, the same process as described above is performed.

When frequency instability occurs due to an external disturbance input during transmission and reception, if the frequency instability is 100 Hz or more, the same process as described above is ignored.

That is, FIG. 29 is a flowchart for processing a frequency instability during transmission.

30 is a flowchart for processing a frequency instability during reception.

On the other hand, the phase difference and the waveform of the lock detection signal when the external disturbance input in the frequency fixed state is as shown in Figure 31, when the frequency instability is detected, the frequency stability detection signal falls to a low level, the phase difference thereafter is an acceptable range If it decreases within, it indicates that the frequency is fixed again by outputting a high level signal. As shown in FIG. 32, when the frequency is unstable due to external disturbance input, the PLL data continuously outputs a value for the current channel. When the frequency is not stabilized again within 100 Hz, a signal indicating that the frequency is unstable is applied to the LCD display. The above-described LCD display unit is the same as in FIG. 33, and the battery status icon flashes according to the battery low state, the currently used channel display icon, the scanning status icon indicating whether the current channel is scanned, the lock status display icon, the transmission status icon, and the reception. Status icons, antenna tower icons, and power saver mode icons are provided.

However, the above-described ASIC circuit part has a 32-pin implementation in addition to the 28-pin implementation in the package configuration, and the differences are as follows.

FIG. 34 shows the pin arrangement in the ASIC circuit part of the FRS according to the 32-pin configuration. In addition to the first, eighth, seventeenth, and twenty-fourth pins configured in a Not Connect (NC) state, the basic pins are also shown in FIG. The configuration is the same as the 28-pin type. That is, in the 28-pin configuration, the pin arrays from the first pin to the 28th pin are allocated in the 32-pin configuration in a counterclockwise direction starting from the 25th pin.

Second embodiment

The second embodiment is newly configured to participate in the high performance FRS market by adding new functions based on the above basic block, and provides expanded performance using the entire 44-pin package.

First, the internal configuration of the above-described ASIC circuit portion and the peripheral circuit portion thereof will be described in detail.

FIG. 35 is a block diagram illustrating a circuit configuration including an ASIC circuit part of an FRS according to a second embodiment of the present invention. The FRS includes a wireless receiver 110 for receiving wireless data from the outside and wireless data to a desired caller. A wireless transmitter 120 for transmitting, a frequency generator 190 for generating a required frequency for demodulating and demodulating voice signals and data, a voice input unit 130 for receiving voice and converting it into an electrical signal, A power supply unit 140 for supplying a predetermined level of power, a button input unit 150 configured in a three-row and three-column matrix form and selected by a user to press, and an LCD display unit 160 for displaying operation states and functions. And, an audio output unit 170 for outputting the other party's voice at an audible frequency, and an ASIC circuit unit 180 for providing various functions and overall control according to the FRS system configuration. It is. The ASIC circuit unit 180 further includes an EEPROM 182 for storing predetermined data, a clock generator TCXO for receiving a predetermined clock, and a transistor for controlling the transmission / reception circuit block. do.

Compared to the first embodiment described above, the second embodiment not only has a different pin arrangement, but also has newly added components and added functions, which will be described in detail as follows.

First, a second embodiment according to the present invention provides a tone generating function and a tone detection function to configure a continuous tone coded squelch system (hereinafter referred to as CTCSS). In addition to the filtering circuit portion, a serial interfacing function and a power control function are further provided.

First, the frequency of CTCSS is well known as the "subaudio frequency" because it is just below the human audible frequency, which requires the use of a CTCSS tone when connected to other systems in a transmit / receive system. interference) Often used as a means to solve or prevent problems. In addition, since the system output generates CTCSS tones, users of systems equipped with equipment capable of decoding tones below the audible frequency cannot hear other sources of interference on the channel, but for users who do not have it, the system's Squelch Will be opened.

36 is a basic block diagram of a squelch system using a CTCSS applied to a second embodiment of the present invention, in which a voice signal is input from an external device through a microphone, amplified through an amplifier, and through a pre-emphasis in this process; Passed to the pass filter.

Meanwhile, the tone signal supplied from the CTCSS tone generator is mixed with the output signal of the band pass filter and wirelessly transmitted.

In wireless reception, it is amplified by an amplifier and passed to an audio band pass filter and a sub audio low pass filter, respectively, wherein the audio band pass filter filters only signals having a frequency of 300 Hz to 3 Hz, and the sub audio. The low pass filter filters out only signals with frequencies below 300kHz.

The signal transmitted from the audio band pass filter is output through the speaker through de-emphasis, and the signal transmitted to the CTCSS detector through the sub audio low pass filter is output to the control block as a CTCSS tone detection signal.

Sub audio low pass filter

The subaudio low pass filter is used to separate a tone signal from an audio signal generated from an intermediate frequency IC or to remove a high frequency component from a signal generated by the CTCSS tone generator. In the low pass filter applied to the present invention, the cut-off frequency is composed of a switchable capacitor filter of 4th order or more, which can vary the cutoff frequency from 10 kHz to at least 500 kHz.

The clock applied to the low pass filter to determine the cutoff frequency is supplied from a control block of the ASIC circuit part according to the tone frequency currently set, and the cutoff frequency at this point is the frequency at which the signal level drops to 3 dB or less.

2) CTCSS tone generator

There are a total of 38 tones in the standard CTCSS generated from the CTCSS tone generator, as shown in Table 3 below. It has a range of 250.3 ms.

In addition, as shown in FIG. 37, since the CTCSS tone is added to the voice signal during transmission and then modulated to the carrier, high frequency components of 300 kHz or more must be sufficiently filtered in order not to affect the voice signal.

Therefore, in order to minimize these components, a step wave form is more advantageous than a rectangular wave, and high frequency components are removed through the sub audio low pass filter.

No. Frequency No. Frequency No. Frequency No. Frequency 01 67.0 11 97.4 21 136.5 31 192.8 02 71.9 12 100.0 22 141.3 32 203.5 03 74.4 13 103.5 23 146.2 33 210.7 04 77.0 14 107.2 24 151.4 34 218.1 05 79.7 15 110.9 25 156.7 35 225.7 06 82.5 16 114.8 26 162.2 36 233.6 07 85.4 17 118.8 27 167.9 37 241.8 08 88.5 18 123.0 28 173.8 38 250.3 09 91.5 19 127.3 29 179.9 10 94.8 20 131.8 30 186.2

The step wave has 8 steps and 5 levels per cycle, and the allowable frequency error of the CTCSS is about 0.05% at maximum, and a passband of up to 280 kHz at the low pass filter. Have

3) CTCSS tone detector

When the CTCSS is set, in order to detect this in the transmission signal, first, only the sub-audio portion, i.e., the sub-audio portion, below 300 kHz of the audio output signal of the IF IC is filtered. The output of the low pass filter is again converted to a logic level by a comparator, which is used to measure the period of the CTCSS tone. That is, when the edge portion of the converted CTCSS tone, that is, the rising or falling portion is detected and the sampling time of the automatically reloaded timer is set, the number of samplings between the two edges is determined. By measuring, the CTCSS tone frequency can be determined. At this time, it is necessary to reset the cutoff frequency of the sub-audio low pass filter according to the CTCSS tone frequency, to prevent audio blocking according to the quality of the received data, that is, the CTCSS frequency, and to mute the audio without the squelch tail. The passing range is within 2.73%. 4) serial interface

In addition to the operation state and initial set value of the ASIC circuit part, an external data storage means such as an EEPROM is required to obtain data necessary for operation, and high-speed communication using a serial interface is required to reduce space occupancy caused by input / output pins. Do. ASIC circuitry can be used for both high and low end systems, and the use of CTCSS is a representative example of the two systems. In order to determine whether to use the CTCSS as described above, data can be additionally configured externally using the serial interface.

When the system is powered on, data previously used to determine an initial start channel, a volume level, and the like are retrieved from the EEPROM, and thus the data is stored in the EEPROM at the end of the system.

5) power on / off controller

The power on / off controller controls the power of the entire system using an output voltage control port, which will be described with reference to FIG. 8.

FIG. 39 is a block diagram illustrating a power on / off controller in an FRS ASIC according to the present invention, which is divided into a case in which the power is switched from an off state to an on state and a case in which the power is switched from the on state to the off state. Do it.

First, since pin 43 of the ASIC circuit of the present invention, that is, the power on / off recognition terminal is pulled down internally, it is maintained at a "logically low level" when the power switch is not pressed.

① When the power turns on from off

When the power switch is pressed, a voltage is applied to the control terminal of the constant voltage element through the diode D1, and the constant voltage element outputs a voltage of a predetermined level. At this time, power must be supplied for a sufficient time (about 2 seconds) to drive the ASIC circuit, and during this time, the power switch must be kept pressed.

After driving the ASIC circuit unit, when the power-on input is confirmed through pin 43, which is a power on / off recognition terminal, the ASIC circuit unit outputs a logically high voltage through pin 44, which is a constant voltage element control terminal. Control the operation.

② When the power is turned off from on

When the power switch is pressed for a certain time while the power is on, the power off input is recognized through pin 43, a power on / off detection terminal, and the constant voltage IC is operated by removing the output voltage of pin 44, a constant voltage control terminal. Will end.

Here, the time taken for the ASIC circuit unit to recognize the power on / off signal is 2 seconds.

Finally, in the first embodiment (28-pin structure) and the second embodiment (44-pin structure) when comparing the pin arrangement according to the input and output signals of the ASIC, it is shown in Table 4.

The present embodiment as described above is for illustrative purposes only, and the central idea of the present invention can be mass-produced as a single ASIC chip, whether it is a US type or a European type, a product with additional functions, or a product with basic functions. The main idea is to reduce the volume and weight with hardwired programming and improve the call quality by applying the tone squelch system. Therefore, it is obvious that the embodiments modified to be inferred by the present invention also fall within the scope of the claims.

According to a preferred embodiment of the present embodiment disclosed as described above has the following advantages.

First, the same ASIC circuit for the European or American lifestyle radios has the advantage of improving productivity.

Second, because there are many additional functions, the high value-added products and the basic functions are the same as the ASIC circuit part for inexpensive products, so it is not only easy to upgrade in the future, but also has the advantage of providing additional function upgrades to customers.

Third, by not using a general-purpose microprocessor, and providing a self-designed chip, it not only wastes the resources of the microprocessor, but also provides a margin to reduce the volume or weight more than the product employing the microprocessor.

Claims (13)

In the household radio comprising a wireless communication unit, audio input and output unit, button input unit, power supply unit, display unit, ASIC circuit unit for controlling each component, A memory for storing data on channel frequencies to be allocated during wireless communication; A control block outputting a control signal according to an internal program; A display driver for driving the display unit; An output level control block for controlling an output level of a received voice signal, and the like, comprising: a divider for dividing an input frequency into a predetermined level to provide a frequency synthesizer; A phase detector for detecting a phase of an input signal; A charge pump for controlling the oscillation frequency of the external oscillator according to the phase detection result; A frequency fixed detector for detecting whether the frequency is stable or fixed; A buffer for buffering the input clock signal; A reference divider for providing a reference of said phase comparator; And a clock driver configured to receive a predetermined clock and to fan out a predetermined clock. The method of claim 1, The ASIC circuit section includes a communication busy signal input port, a VCO frequency input port, a power input port, a PLL signal output port, a ground signal input port, a fixed frequency display port, a clock input port, a test port, and a transmission port. On / off control signal output of the enable port, the reset signal applying port, the battery voltage sensing port, the switching input port, the first to eighth ports for driving the LCD display, and the backlight of the LCD display. And a port, a power save or reception permission port, a beep output port, and an input and output port for controlling speaker volume, respectively. The method of claim 1, The LCD display unit is driven by receiving a 5-bit segment input and a 3-bit control signal input as a control command to distinguish the display data, and displays the battery low, the current channel, the frequency stability, and the power save mode in a predetermined graphic. Life walkie-talkie circuit characterized in that. The method of claim 1, And said control block comprises a plurality of logic elements programmed in a hardwired manner. The method of claim 1, Signals input to the ASIC circuit are power on / off signals, call button signals, channel up and down button signals, volume up and down button signals, call button signals, monitor / backlight, and button lock signals. Life walkie-talkie circuit characterized in. The method of claim 1, VCO transmission frequency stored in the memory is 231MHz-233MHz, VCO receiving frequency life radio circuit, characterized in that 220MHz-223MHz. VCO transmission frequency stored in the memory is 462MHz-467MHz, VCO reception frequency is 441MHz-446MHz life radio circuit. The method of claim 1, The VCO transmission frequency stored in the memory is multiplied by two, and the PMR VCO transmission frequency is 223 MHz, and the PMR VCO reception frequency is 212 MHz. The method of claim 1, And the PMR VCO transmission frequency stored in the memory is in the 446 MHz band and the receiving frequency is in the 424 MHz band. The method of claim 1, And a transmission frequency of the FRS input to the ASIC circuit unit is 462-467 MHz, a reception frequency is 441-446 MHz, a transmission frequency of the PMR is 446 MHz, and a reception frequency is 424 MHz. In the household radio comprising a wireless communication unit, voice input / output unit, button input unit, power supply unit, display unit and control unit, The control unit is hardwired and configured in an ASIC chip having a plurality of terminals, and includes an audio band pass filter for selecting only an audio signal band, a sub audio low pass filter for removing noise below an audible frequency, and a plurality of CTCSS. With a CTCSS tone generator to generate tone. CTCSS tone detector for detecting the CTCSS tone generated by the CTCSS tone generator, a serial interface for serial communication with the outside, and a power on / off controller for controlling the power of the entire device Life walkie-talkie circuit. The method of claim 11, The CTCSS tone is 67 dB ?? Life radio circuit, characterized by 38 tone frequencies selected in the range of 250.3 GHz. The method of claim 11, Wherein said low pass filter is a fourth order or more variable, switched capacitor low pass filter capable of varying a cutoff frequency from 10 kHz to at least 500 kHz.