KR20010091429A - Electro Static Discharge Protection Circuit and Method For Fabricating the Same - Google Patents

Abstract

The present invention relates to an electrostatic discharge (ESD) protection circuit capable of lowering a triggering voltage of a field plate diode (FPD) and a method of manufacturing the same. In addition to the second conductivity type deep well formed in one region of the first conductivity type semiconductor substrate, the first conductivity type well and the first conductivity type well formed in the first conductivity type semiconductor substrate on the second conductivity type deep well. A second conductivity type well formed in the first conductivity type semiconductor substrate in a region of the first conductivity type, a high concentration first conductivity type first impurity diffusion region formed at a predetermined depth in a predetermined region of the first conductivity type well, and the first conductivity type A high concentration second conductivity type second impurity diffusion region formed in a gate electrode formed on one region of the well and the first conductivity type well on one side of the gate electrode and the first conductivity type on the other side of the gate electrode A transistor comprising a high concentration second conductivity type third impurity diffusion region formed on a surface of an interface between the well and the second conductivity type well, and the second conductivity type well adjacent to the high concentration second conductivity type third impurity diffusion region And a high concentration first conductivity type fourth impurity diffusion region formed therein and a high concentration second conductivity type fifth impurity diffusion region formed in the second conductivity type well in contact with the first conductivity type fourth impurity diffusion region.

Description

Electrostatic Discharge Protection Circuit and Method For Fabricating the Same H01L

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an ESD protection circuit capable of lowering a triggering voltage of a field plate diode (FPD) and a method of manufacturing the same.

Hereinafter, an ESD protection circuit of the related art will be described with reference to the accompanying drawings.

1 is a structural cross-sectional view of a conventional ESD protection circuit.

As shown in FIG. 1, an n well 102 is formed in a region within the p-type semiconductor substrate 101 at a predetermined depth, and a predetermined depth is formed in the p-type semiconductor substrate 101 except for the region in which the n well 102 is formed. The p well 103 is formed.

A high concentration p-type impurity diffusion region 104 is formed in one region of the p well 103.

In addition, a gate electrode 110 is formed on the p well 103 spaced apart from the high concentration p-type first impurity diffusion region 104, and a high concentration n-type is formed on one side of the gate electrode 110. A second impurity diffusion region 105 is formed, and a high concentration n-type third impurity diffusion region 106 is formed in the surface of the interface between the other p well 103 and the n well 102 of the gate electrode 110.

Here, the high concentration n-type second impurity diffusion region 105 and the high concentration n-type third impurity diffusion region 106 are source / drain, and are active transistors composed of the gate electrode 110. Plate Diode) is formed.

A high concentration p-type fourth impurity diffusion region 107 is formed in a predetermined region of the n well 102 in contact with the high concentration n-type third impurity diffusion region 106, and the high concentration p-type fourth impurity diffusion region 107 is formed. ), A high concentration n-type fifth impurity diffusion region 108 is formed in a predetermined region of the n well 102 in contact with the N well 102.

In addition, the high concentration p-type first impurity diffusion region 104, the high concentration n-type second impurity diffusion region 105, and the gate electrode 110 are connected to a ground voltage GND or Vss and the high concentration fourth impurity. The diffusion region 107 and the high concentration fifth impurity diffusion region 108 are connected to the pad 109.

Although not shown in the figure, the pad 109 is connected to an internal circuit.

In the conventional ESD protection circuit configured as described above, when static electricity is applied to the pad 109, the potential of the high concentration p-type fourth impurity diffusion region 107 is increased to thereby increase the concentration n-type third impurity diffusion region 106. The carrier moves.

At the interface between the high concentration n-type third impurity diffusion region 106 and the p well 103, electrons move to the high concentration n-type third impurity diffusion region 106 having a high potential, and the holes are p-well 103. ), A high potential voltage (snapback voltage) is applied to the p well 103 and the FPD operates as a parasitic npn transistor.

Accordingly, carriers applied due to static electricity are discharged to the ground terminal GND through the path ① of FIG. 1.

However, the conventional ESD protection circuit as described above has the following problems.

First, as the oxide thickness of the gate becomes thinner due to high integration, the oxide breakdown voltage is also lowered, so the triggering voltage of the ESD protection circuit is higher than the gate oxide breakdown voltage, thereby destroying the internal circuit before discharging the ESD.

Second, an additional protection circuit is needed because the trigger voltage is higher than the gate oxide breakdown voltage.

Third, when the doping concentration of the p well is lowered, the trigger voltage is lowered, but a latch-up problem occurs.

The present invention has been made to solve the above problems, and an object thereof is to provide an ESD protection circuit and a method of manufacturing the same, which can lower the triggering voltage of the FPD.

1 is a structural cross-sectional view of a conventional ESD protection circuit

2 is a structural cross-sectional view of an ESD protection circuit according to an embodiment of the present invention.

3A to 3D are cross-sectional views of a manufacturing process of an ESD protection circuit according to an embodiment of the present invention.

Explanation of symbols for the main parts of drawings

201: p-type semiconductor substrate 202: n well

203: p well

204 high concentration p-type first impurity diffusion region

205: high concentration n-type second impurity diffusion region

206: high concentration n-type third impurity diffusion region

207: high concentration p-type fourth impurity diffusion region

208: high concentration n-type fifth impurity diffusion region

209: Pad

210: gate electrode

211: deep n well

The ESD protection circuit of the present invention for achieving the above object is a first conductivity type semiconductor substrate, a second conductivity type deep well formed in one region inside the first conductivity type semiconductor substrate, and the second conductivity type dip A first conductivity type well formed in the first conductivity type semiconductor substrate on the well, a second conductivity type well formed in the first conductivity type semiconductor substrate in a region other than the first conductivity type well, and the first conductivity type well A high concentration first conductive impurity diffusion region formed at a predetermined depth in a predetermined region, a gate electrode formed on one region of the first conductivity type well, and a high concentration agent formed on the first conductivity type well on one side of the gate electrode The second conductivity type second impurity diffusion region and the high concentration second conductivity type third impurity diffusion region formed on the surface of the interface between the first conductivity type well and the second conductivity type well on the other side of the gate electrode. And a high concentration first conductivity type fourth impurity diffusion region formed in the second conductivity type well adjacent to the high concentration second conductivity type third impurity diffusion region, and the first conductivity type fourth impurity diffusion region. And a high concentration of the second conductivity type fifth impurity diffusion region formed in contact with the second conductivity type well.

The method of manufacturing an ESD protection circuit of the present invention configured as described above may include forming a second conductive deep well below a predetermined depth of a region of a first conductive semiconductor substrate, and forming an upper portion of the second conductive deep well. Forming a first conductivity type well in the first conductivity type semiconductor substrate and a second depth having the same depth as the second conductivity type deep well in the first conductivity type semiconductor substrate except for the first conductivity type well formation region Forming a conductive well, forming a gate electrode on one region of the first conductive well via an oxide film, and forming a first high concentration in a predetermined region of the first conductive well on one side of the gate electrode Forming a first conductivity type impurity diffusion region and simultaneously forming a high concentration first conductivity type fourth impurity diffusion region in a predetermined region of the second conductivity type well on the other side of the gate electrode; A high concentration second conductivity type agent is formed in the first conductivity type well on one side of the electrode, and the second conductivity type second impurity diffusion region is formed on the surface of the interface between the first conductivity type well and the second conductivity type well on the other side of the gate electrode. Forming a third impurity diffusion region and forming a high concentration second conductivity type fifth impurity diffusion region in the second conductivity type well in contact with the high concentration first conductivity type fourth impurity diffusion region.

Hereinafter, an ESD protection circuit and a method of manufacturing the same according to an embodiment of the present invention will be described with reference to the accompanying drawings.

2 is a cross-sectional view illustrating an ESD protection circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 2, an n well 202 is formed in a region within the p-type semiconductor substrate 201 at a predetermined depth, and a predetermined depth is formed in the p-type semiconductor substrate 201 except for the region in which the n well 202 is formed. The p well 202 is formed.

The high concentration p-type first impurity diffusion region 204 is formed in a predetermined region of the p well 203.

In addition, a gate electrode 210 is formed on the p well 203 spaced apart from the high concentration p-type first impurity diffusion region 204 by a predetermined distance, and the high concentration n-type is formed in the p well 203 on one side of the gate electrode 210. The second impurity diffusion region 205 is formed, and a high concentration n-type third impurity diffusion region 206 is formed in the surface of the interface between the other p well 203 and the n well 202 of the gate electrode 210.

Here, the high concentration n-type second impurity diffusion region 205 and the high concentration n-type third impurity diffusion region 206 are source / drain and are formed of the gate electrode 210. Field Plate Diode) is formed.

A high concentration p-type fourth impurity diffusion region 207 is formed in a predetermined region of the n well 202 in contact with the high concentration n-type third impurity diffusion region 206, and a high concentration in a predetermined region of the n well 202 in contact with the high concentration n-type third impurity diffusion region 206. An n-type fifth impurity diffusion region 208 is formed.

A deep n well 211 is formed on the p-type semiconductor substrate 201 to include a lower portion of the p well 203.

In addition, the high concentration p-type first impurity diffusion region 204, the high concentration n-type second impurity diffusion region 205, and the gate electrode 210 are connected to a ground voltage GND or Vss and the high concentration p-type agent. The four impurity diffusion region 207 and the high concentration n-type fifth impurity diffusion region 208 are connected to the pad 209.

Although not shown in the figure, the pad 209 is connected to an internal circuit.

Referring to the accompanying drawings, a method of manufacturing an ESD protection circuit according to an embodiment of the present invention configured as described above is as follows.

3A to 3D are cross-sectional views illustrating a manufacturing process of an ESD protection circuit according to an exemplary embodiment of the present invention.

As shown in FIG. 3A, a deep n well 211 is implanted under a predetermined depth of the first conductivity type semiconductor substrate 201 by implanting impurity ions having high energy into one region of the p-type semiconductor substrate 201. Form.

The depth of formation of the deep n well 211 may be controlled by the size of impurity ion implantation energy.

The p-type semiconductor substrate 201 on the deep n well 211 is used as the p well 203 and implants impurity ions into the p well 203 to change the doping concentration of the p well 203. Can be.

Thereafter, a photoresist is applied on the p-type semiconductor substrate 201 and the photoresist is patterned to cover the p well 203 by an exposure and development process.

The n well 202 is formed by implanting n-type impurity ions using the photoresist as a mask.

As shown in FIG. 3B, an oxide film is formed over the p-type semiconductor substrate 201 including the p well 203 and polysilicon is deposited on the oxide film.

The polysilicon and the oxide film are etched by a photo and etching process to form a gate electrode 210 with an oxide film in one region on the p well 203.

As shown in FIG. 3C, a photoresist is coated on the entire surface of the p-type semiconductor substrate 201 including the gate electrode 210, and a predetermined region of the p well 203 and the exposure process are performed using an exposure and development process. The photoresist is patterned to reveal a predetermined area of n well 202.

Subsequently, the high concentration p-type first impurity diffusion region 204 and the high concentration p-type fourth impurity diffuse into the predetermined surfaces of the p well 203 and the n well 202 through ion implantation using the patterned photoresist as a mask. Regions 207 are formed respectively.

As shown in FIG. 3D, after the photoresist is coated on the entire surface of the p-type semiconductor substrate 201 including the gate electrode 210, the p well on one side of the gate electrode 210 is exposed and developed. The photoresist is patterned so that the surface of the interface between the p well 203 and the n well 202 and the predetermined region of the n well 202 is exposed.

Forming a high concentration n-type second impurity diffusion region 205 at a predetermined depth in the p-well 203 on one side of the gate electrode 210 by implanting n-type impurity ions using the patterned photoresist as a mask; At the same time, a high concentration n-type third impurity diffusion region 206 is formed on the surface of the interface between the p well 203 and the n well 202 on the other side of the gate electrode 210, and the predetermined region of the exposed n well 202 is formed. A high concentration n-type fifth impurity diffusion region 208 is formed at a constant depth in the.

Here, the high concentration n-type third impurity diffusion region 206, the high concentration p-type fourth impurity diffusion region 207, and the high concentration n-type fifth impurity diffusion region 208 are formed by joining one after another.

In addition, the high concentration n-type second impurity diffusion region 205 is formed at regular intervals from the high concentration p-type first impurity diffusion region 204.

The high concentration p-type first impurity diffusion region 204, the high concentration n-type second impurity diffusion region 205, and the gate electrode 210 are connected to a ground voltage GND or Vss. The fourth impurity diffusion region 207 and the high concentration n-type fifth impurity diffusion region 208 are connected to the pad 209.

Although not shown in the figure, the pad 209 is connected to an internal circuit.

In the operation of the ESD protection circuit according to the embodiment of the present invention as described above, when the static electricity is applied to the pad 209, the potential of the high concentration p-type fourth impurity diffusion region 207 is increased, thereby increasing the concentration n-type third. The carrier moves to the impurity diffusion region 206.

At the interface between the high concentration n-type third impurity diffusion region 206 and the p well 203, electrons move to the high concentration n-type third impurity diffusion region 206 having a high potential, and the holes are p-well 203. ), The p well 203 is subjected to a high potential (snapback voltage), and the FPD operates as a parasitic npn transistor.

Accordingly, carriers applied due to static electricity are discharged to the ground terminal GND through the path ② of FIG. 2.

In the ESD protection circuit according to the embodiment of the present invention as described above, the thickness of the p well 203 is reduced and the resistance is increased by introducing the deep n well 211 into the body region of the FPD, thereby increasing the snapback of the FPD. The voltage is lowered.

In addition, the ion implantation energy and the doping concentration of the deep n well 211 may be adjusted to control the trigger voltage of the ESD protection circuit and the resistance of the p well 203.

As described above, the ESD protection circuit of the present invention and a method of manufacturing the same have the following effects.

First, a deep n well is introduced into the body region of the FPD to reduce the FPD snapback voltage, thereby lowering the trigger voltage of the ESD protection circuit.

Second, since the trigger voltage of the ESD protection circuit can be adjusted below the gate oxide breakdown voltage by controlling the deep n well ion implantation energy and doping concentration, an additional protection circuit is not required, thereby reducing the area of the protection circuit.

Third, the resistance of the p well can be selectively controlled by using a deep n well layer, thereby solving the latch-up problem.

Fourth, the present invention can be configured without an additional process in a product using a triple well process such as DRAM.

Claims (4)

A first conductivity type semiconductor substrate; A second conductivity type deep well formed in one region of the first conductivity type semiconductor substrate; A first conductivity type well formed in the first conductivity type semiconductor substrate on the second conductivity type deep well and a second conductivity type well formed in the first conductivity type semiconductor substrate in a region other than the first conductivity type well; A high concentration first conductivity type first impurity diffusion region formed at a predetermined depth in a predetermined area of the first conductivity type well; A gate electrode formed on one region of the first conductivity type well, a second highly conductive second impurity diffusion region formed in the first conductivity type well on one side of the gate electrode, and the first conductivity on the other side of the gate electrode A transistor comprising a high concentration second conductivity type third impurity diffusion region formed on a surface of an interface between the type well and the second conductivity type well; A high concentration first conductivity type fourth impurity diffusion region formed in the second conductivity type well adjacent to the high concentration second conductivity type third impurity diffusion region; And a high concentration second conductivity type fifth impurity diffusion region formed in the second conductivity type well in contact with the first conductivity type fourth impurity diffusion region. The high concentration second conductivity type fifth impurity diffusion region and the high concentration first conductivity type fourth impurity diffusion region are connected to a pad connected to an internal circuit, and the high concentration second conductivity type second impurity diffusion region. And the high concentration first conductivity type first impurity diffusion region and the gate electrode are connected to a ground voltage. Forming a second conductivity type deep well below a predetermined depth of one region of the first conductivity type semiconductor substrate; Forming a first conductivity type well on the first conductivity type semiconductor substrate on the second conductivity type deep well; Forming a second conductive well having the same depth as the second conductive deep well in the first conductive semiconductor substrate except for the first conductive well forming region; Forming a gate electrode through an oxide film on one region of the first conductivity type well; A first concentration type first conductivity type impurity diffusion region is formed in a predetermined region of the first conductivity type well on one side of the gate electrode, and a first concentration type first conductivity type agent is formed in a predetermined region of the second conductivity type well on the other side of the gate electrode. Forming an impurity diffusion region; A second high concentration second conductivity type impurity diffusion region is formed in the first conductivity type well on one side of the gate electrode, and a high concentration second conductivity is formed in the surface of the interface between the first conductivity type well and the second conductivity type well on the other side of the gate electrode. And forming a high concentration second conductivity type fifth impurity diffusion region in the second conductivity type well in contact with the high concentration first conductivity type fourth impurity diffusion region. Method for manufacturing an ESD protection circuit. The method of claim 3, wherein the high concentration second conductivity type third impurity diffusion region, the high concentration first conductivity type fourth impurity diffusion region and the high concentration second conductivity type fifth impurity diffusion region are formed adjacent to each other. Method for manufacturing an ESD protective circuit.