KR20010087491A - Method of fabricating semiconductor device using SOG film - Google Patents

Abstract

PURPOSE: A manufacturing method of a semiconductor device is to conveniently performing a gap-fill process on a fine pattern and to suppress generation of a crack, thereby improving reliability of the device. CONSTITUTION: A plurality of conductive layer pattern(14) are formed on a lower layer(12) with a constant space therebetween. The first oxide(16) and an SOG(spin-on glass) layer(18) are formed on the resultant structure in this order, followed by curing them at 500 to 700 deg.C. The second oxide(20) is then formed on the SOG layer. A portion of an interlayer dielectric composed of the first oxide, the SOG layer and the second oxide is etched off to form a contact hole exposing the lower layer between the conductive layer patterns. An annealing process is performed on the resultant structure at 300 to 550 deg.C to remove an out-gassing source. Thereafter, the second conductive layer(24) covering the contact hole is formed on the entire surface.

Description

Method of fabricating semiconductor device using SOH film {Method of fabricating semiconductor device using SOG film}

The present invention relates to a method for manufacturing a semiconductor device using a spin-on glass (SOG) film, and more particularly, to a method for manufacturing a semiconductor device using an esot film as an interlayer insulating film.

As semiconductor devices become more integrated in semiconductor integrated circuits, the size of the pattern becomes smaller. Therefore, the lithography process for forming such a fine pattern is becoming more and more difficult, and the gap-fill process of filling the space between the fine patterns also requires a very difficult technique. In particular, since the lithography process is greatly influenced by the flatness and uniformity of the lower layer, the planarization problem in the semiconductor device manufacturing process has emerged as an important factor for stabilization of the subsequent lithography process.

In the fabrication process of a semiconductor device, a conventional general technique for filling and planarizing an insulating planarization material between fine conductive patterns formed on a specific underlayer is performed by chemical vapor deposition (CVD) on the entire surface of a substrate having a fine pattern formed thereon. After the planarization insulating film was formed by physical vapor deposition (PVD), an etching process such as chemical physical polishing (CMP) was performed to planarize the surface of the substrate.

However, as the integration increases, the size of the lines and spaces forming the pattern decreases, and the gap fill process by the conventional CVD method or the PVD method is gradually showing its limitations. In particular, an ultra-high density semiconductor which is subject to a design rule of 0.2 µm or less. For devices, the limits are approaching and new gap fill technologies are required.

An object of the present invention is to provide a method for manufacturing a semiconductor device using an SOH film that can perform a gap fill process of a fine pattern smoothly.

Another object of the present invention is to provide a method of manufacturing a semiconductor device which can improve the reliability by suppressing the occurrence of cracks while performing the gap fill process of the fine pattern smoothly.

1 to 5 are process cross-sectional views illustrating a process of manufacturing a semiconductor device according to an embodiment of the present invention.

6 is a cross-sectional view illustrating a semiconductor device manufactured in accordance with another embodiment of the present invention.

※ Explanation of code for main part of drawing

10, 30; Semiconductor substrate 12; Base layer

14; First conductive layers 16 and 46; First oxide film

18, 48; Ezekiel 20, 50; Second oxide film

22; Contact hole 24; Second conductive layer

31; Impurity region 32; Device isolation area

34; Gate insulating film 36; Gate electrode

38; Insulating film 40; Spacer

42; Pad layer 43; Interlayer insulation film

44; Bitline 54; Storage electrode

In the method of manufacturing a semiconductor device according to the present invention for achieving the object of the present invention, the step of forming a plurality of first conductive layer patterns arranged at regular intervals on the base layer, the temperature of at least 500 ℃ or more on the front surface of the resultant Forming an insulating layer including a spin-on glass (SOG) film accompanied by a curing process, and etching a portion of the insulating layer to expose the underlying layer between the first conductive layer patterns. Forming a hole, performing heat treatment on the resultant under a vacuum condition, degassing, and forming a second conductive layer filling the contact hole.

The insulating layer including the SOG film may be formed on the oxide film formed by the CVD method in consideration of the adhesion between the SG film and the underlying layer or between the SG film and the resist used in the subsequent lithography process. After forming the SOH film on the resultant material on which the plurality of conductive layer patterns are formed, an insulating film such as an oxide film or the like may be formed, or may be formed in a sandwich structure composed of an oxide film / Esuji film / oxide film.

Meanwhile, before performing the degassing process, the ammonia plasma treatment may be performed on the resultant in which the contact hole is formed to harden the exposed film to prevent out-gassing and to improve the contact resistance.

According to the present invention, an Suji film having excellent planarization capability is used as a main material of the gap fill process, and at the same time, a sufficient curing process at a temperature of at least 500 ° C. or more at the initial stage of the formation of the Suji Film to solve the problems caused by outgassing of the Suji Film. The contact resistance is reduced by performing ammonia plasma treatment process and degassing process after forming contact holes between the fine patterns, thereby realizing a semiconductor device having improved reliability and electrical characteristics of the device.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 to 5 are process cross-sectional views illustrating a manufacturing process of a semiconductor device according to an embodiment of the present invention, in which a contact pattern is formed in a gap fill process of a fine pattern and a space of a fine pattern to which the principles of the present invention are specifically applied. The process is shown intensively.

Referring to FIG. 1, an interlayer insulating film is formed as a base layer 12 on a semiconductor substrate 10, and a first conductive layer 14 is formed on a base layer 12 while maintaining a constant space. . The base layer 12 may be formed of a single layer such as an oxide film or a nitride film or a composite film thereof, and various types of conductive or insulating patterns may be formed in the base layer 12, for example, a gate electrode structure is formed. Although detailed illustration and description are omitted. On the other hand, the first conductive layer 14 as described above may be a gate electrode formed directly on the semiconductor substrate 10 without the intervention of the base layer 12 as an interlayer insulating film. In this case, the underlying layer below the first conductive layer may be defined as a semiconductor substrate.

The first conductive layer 14 is formed by forming a conductive material such as polysilicon, tungsten, or tungsten silicide doped with impurities on the base layer 12 and then performing a conventional photolithography process. The space between the first conductive layers 14 is further reduced according to the high integration of the semiconductor device, and may be, for example, 0.2 μm or less, but the present invention is not limited thereto.

Referring to FIG. 2, the first oxide layer 16 and the SOH layer 18 are sequentially formed on the entire surface of the resultant in which the first conductive layer 14 having the fine pattern shape is formed. The first oxide layer 16 is formed thin so that voids by a bridge or the like are not formed between the first conductive layers 14 having a fine pattern form by a CVD method having excellent step coverage characteristics. Subsequently, an inorganic SOG film 18 such as HSQ (Hydrogen Silsesquioxane) or HSSQ is formed on the first oxide film 16.

The SOH film 18 is a material having a flattening property capable of filling a narrow space more smoothly than a CVD interlayer insulating film without forming voids, and has excellent step coverage characteristics, simplicity of process, low defect density, relatively low cost, and There are advantages such as no use of harmful gas. The sedge film 18 has a siloxane type and a silicate type mixed with an alcoholic solvent, and the sedge material supplied to the workpiece in the liquid phase through the dispersion nozzle of the spinner is subjected to a subsequent curing process. As a result, the solvent and the water evaporate to form an insulating material similar to the silicon oxide film. Curing process of the present embodiment is carried out at a temperature of 500 to 700 ℃ under vacuum, or at the same temperature of oxygen or nitrogen atmosphere. As described above, the curing process is performed at a high temperature of 500 ° C. or higher to sufficiently remove outgassing sources such as solvents and water contained in the SOH membrane in the initial stage after formation of the SOH membrane. This is because these components are outgassed by a subsequent heat treatment process in a state in which the solvent or moisture contained in the SOH membrane is not sufficiently removed, causing stresses in the membrane quality as well as shrinkage of the material, causing cracks. On the other hand, such a high temperature curing process is to ensure that the SOH film is sufficiently firm for the heat treatment process of 500 ℃ or more subsequent in the manufacturing process of the semiconductor device.

As shown in FIG. 2, it can be seen that the gap fill 18 of the space between the first conductive layers 14 is sufficiently formed because the SOH film 18 is supplied in the liquid phase, and further, the flatness of the SOH film is very excellent. Subsequently, there is an advantage that a planarization process such as chemical physical polishing (CMP) does not need to be added. In this embodiment, although the entire etch back process is not performed after the formation of the SOH film 18, the SOH film is formed after considering the thickness of the entire interlayer insulating film formed on the first conductive layer 14. The thickness of the interlayer insulating film may be controlled by performing a front etch back process so that the surface of the first oxide film 16 on the first conductive layer 14 is exposed.

Referring to FIG. 3, a second oxide film 20 is further formed on the SOH film 18 as an insulating film. In the case of using the SOH film 18 as an interlayer insulating film for the purpose of insulation between the conductive layers while filling the fine pattern, the SOH film is used alone, or after forming the CVD oxide film on the conductive layer pattern, the SOH film is formed thereon. Alternatively, a CVD oxide film may be formed on the SG film after forming the SG film, and in consideration of the possibility of cracking due to evaporation of a solvent or moisture, or the adhesion between the SG film and the metal film, or the SG film and the resist film, As in the embodiment, it may be formed in a sandwich structure consisting of the first oxide film 16, the esoteric film 18, and the second oxide film 20. As the second oxide film 20, for example, silicon oxide (SiO ₂ ) or silicon oxide fluoride (SiOF) may be used.

Referring to FIG. 4, a contact hole may be formed in a space between the first conductive layer 14 with respect to a product in which an interlayer insulating film including the first oxide film 16, the SOH film 18, and the second oxide film 20 is formed. 22). That is, after forming a photoresist pattern (not shown) defining a contact hole on the entire surface of the substrate on which the second oxide film 20 is formed, the etching process is performed to form the second oxide film 20, the Suji film 18, and the first oxide film. 1 The oxide film 16 is sequentially removed by etching. An appropriate etching condition is selected according to each etching target layer, and the process is performed until the surface of the underlying layer 12 existing under the first conductive layer 14 is exposed. Although not shown in detail, the contact hole 22 is formed at a position connected to the conductive layer contained in the base layer 12. The contact hole 22 may be directly connected to the surface of the impurity region (not shown) of the semiconductor substrate 10 through the base layer 12.

Subsequently, a degassing process is performed on the substrate on which the contact hole 22 is formed for 60 to 180 seconds under a temperature condition of 300 to 550 ° C. and a pressure condition of 1.0 × 10 ⁻¹⁰ Torr. This degassing process removes the outgassing source from the inner wall of the contact hole 22, in particular, the SOH film 18, to form a stable contact and to improve the contact resistance characteristics. Temperature and time conditions of the degassing process are appropriately selected according to the type of film to be exposed in the contact hole 22.

Meanwhile, after forming the contact hole 22 and before performing the degassing process, an ammonia (NH ₃ ) plasma treatment may be performed on the entire surface of the resultant to improve contact resistance characteristics. The ammonia plasma treatment process also serves to strengthen each film quality exposed by the contact hole.

Referring to FIG. 5, after the degassing process is performed on the substrate on which the contact hole 22 is formed, the front surface of the second conductive layer 24 is filled in-situ so that the contact hole 22 is filled. To form. In this case, the second conductive layer 24 is formed of a conductive material such as polysilicon, aluminum, or tungsten doped with impurities, and is formed by chemical vapor deposition or physical vapor deposition.

In the case of the semiconductor device formed by the above embodiment, a planarized interlayer insulating film can be easily formed by performing a gap fill process using an SOH film having excellent flatness and workability in the space between the fine patterns, and outs generated from the SOH film. Curing process is performed initially at a high temperature of at least 500 ° C. or more after the formation of the Suji film to remove the gassing, and to remove the outgassing from the exposed Suji film on the sidewall of the contact hole even after the formation of the contact hole. By additionally performing an ammonia plasma treatment and degassing process, cracking is suppressed and contact resistance characteristics are also improved.

FIG. 6 is a cross-sectional view illustrating a semiconductor device manufactured in accordance with another embodiment of the present invention, and illustrates a structure in which a bit line is embedded in a DRAM, which is a semiconductor memory device, and a storage electrode is formed therebetween.

Referring to FIG. 6, a field oxide film 32 is formed on the surface of a semiconductor substrate 30 to form an isolation region for separating active regions, and a gate insulating film, a gate electrode material, and a capping insulating film are sequentially formed on the front surface of the substrate. Thereafter, a gate structure including a gate insulating film 32, a gate electrode 34, and an insulating film 38 formed by a conventional photolithography process is formed. An impurity region 31 of a source or a drain is formed on the surface of the semiconductor substrate 30 using the gate structure as an ion implantation mask. An insulating film, for example, an oxide film is formed on the entire surface of the substrate, and then the entire surface is etched back. The spacer 40 is formed on the sidewall of the gate structure.

Subsequently, an interlayer insulating film (not shown) is formed on the entire surface of the substrate, and then a contact hole for exposing the specific impurity region 31 of the semiconductor substrate 30 is formed. After the conductive layer is formed, the entire surface etching process is performed to form the pad layer 42.

Subsequently, after the interlayer insulating layer 43 is formed on the entire surface of the substrate, a contact hole for exposing a part of the pad layer 42 is formed, and then a bit line conductive layer is deposited and patterned on the entire surface of the bit line 44. To form.

Thereafter, as in the method described with reference to FIGS. 1 to 5, the first oxide film 46 by the CVD method is formed on the entire surface of the substrate on which the bit lines 44 are formed. Subsequently, the SOH film 48 is formed so thick that the space between the bit lines 44 is sufficiently filled, and the curing process is sufficiently performed within a temperature range of 500 to 700 ° C. Subsequently, after forming the second oxide film 50 by a CVD method on the sufficiently flattened Suji film 48 by a predetermined thickness, it passes between the bit lines 44, and the surface of the pad layer 42 A contact hole is formed to be exposed.

The second conductive layer material is formed on the entire surface where the contact hole is formed, and then patterned to form the storage electrode 54. After forming a dielectric film on the surface of the storage electrode, an upper electrode material is formed to form a semiconductor capacitor.

Also in this embodiment, after the contact hole for the storage electrode is formed, an ammonia plasma treatment may be additionally performed to improve the contact resistance characteristics, and to remove the outgassing from the SOH film exposed on the sidewall of the contact hole. Perform degassing process.

In the above, a preferred embodiment of the present invention has been described in detail, but the underlying layer of the first conductive layer pattern in which the gap fill is formed by the SOH film may have various structures, and is formed in a space between the first conductive layer patterns. The structure of the contact hole and the structure after the second conductive layer embedded in the contact hole may be variously expected, and various kinds and sizes of the film quality used in the present embodiments may be selected and applied. . Furthermore, the process conditions of the curing process, the ammonia plasma treatment process and the degassing process for the SOH film can also be performed in various ways depending on the characteristics of the film quality.

According to the present invention, a gap fill process is performed using an Suji film having excellent embedding and planarization capability between fine patterns, and at the same time, a sufficient curing process is performed at the initial stage immediately after the formation of the Suji film to solve the problems caused by the outgassing of the Suji film. In addition, by removing and further performing a plasma treatment process and a degassing process, cracks and defects can be reduced, thereby realizing a semiconductor device having improved reliability.

Claims (3)

Forming a plurality of first conductive layer patterns disposed on the underlying layer at regular intervals; Forming an insulating layer including a spin-on glass (SOG) film accompanied by a curing process at a temperature of at least 500 ° C. on the front of the resultant; Etching a portion of the insulating layer to form a contact hole exposing the underlying layer between the first conductive layer patterns; Performing degassing on the resultant by heat treatment under a predetermined vacuum condition; And Forming a second conductive layer to fill the contact hole; and manufacturing a semiconductor device using an SOG film. The method of claim 1, wherein the insulating layer including the SOG film has a sandwich structure formed of an oxide film, an ESG film, or an oxide film. The method of claim 1, further comprising performing an ammonia plasma treatment on a resultant product in which the contact hole is formed before performing the degassing.