KR20010084440A - Improved circular built-in self test circuit - Google Patents

Abstract

PURPOSE: An enhanced circular built-in self test(CBIST) circuit is provided, which generates a test pattern more randomly. CONSTITUTION: A CBIST circuit(200) includes n serially-connected CBIST cells(300_1-300_n) and a multiplexer(210). Signals being output from the CBIST cells are test patterns(TP1-TPn), and these test patterns are provided to a main assembly circuit(100). The multiplexer provides a signal(Sin) provided from the external as an input signal of the first CBIST cell(300_1) usually, but feeds back a signal being output from the last CBIST cell(300_n) as an input signal of the first CBIST cell during a BIST mode. That is, the multiplexer operates equally to a signature register by generating a feedback loop during the BIST mode.

Description

IMPROVED CIRCULAR BUILT-IN SELF TEST CIRCUIT}

The present invention relates to a circular built-in self test (CBIST) circuit that generates a test pattern every clock cycle. The present invention relates to a CBIST circuit having improved test reliability by increasing the number of cases.

Built-in self test (BIST) has been adopted in many semiconductor devices because it can minimize the cost of testing. As such a BIST method, a scan BIST and a circular BIST are commercially available. Scan BIST, which loads or extracts test data onto a scan chain, has a disadvantage in that test time is lengthened because a shift operation must be performed by the length of the scan chain in every test pattern. CBIST, on the other hand, generates test patterns automatically every clock cycle, resulting in very short test times.

1 is a block diagram schematically showing a conventional CBIST circuit.

Referring to FIG. 1, the conventional CBIST circuit 12 includes n CBIST cells 30_1 to 30_n and a multiplexer 20 connected in series. The signals output from the CBIST cells 30_1 to 30_n are test patterns TP1 to TPn, and the test patterns TP1 to TPn are provided to the main combination circuit 10.

The multiplexer 20 normally provides a signal Sin provided from the outside as an input signal of the first CBIST cell 30_1, but provides a signal output from the last CBIST cell 30_n during the BIST mode to the first CBIST cell. A device for feeding back an input signal of 30_1. In other words, the multiplexer 20 generates a feedback loop during the BIST mode and operates in the same manner as a signature register, which is a compressor that is generally used.

FIG. 2 is a detailed circuit diagram of the CBIST cell shown in FIG. 1.

Referring to FIG. 2, the CBIST cell 30_i includes first and second AND gates 32 and 34, an exclusive OR gate 326, and a D-flip flop 38.

The first AND gate 32 receives a signal Di provided from the main combination circuit 10 and a first mode signal B1 provided from the outside, and performs a logical multiplication operation. The second AND gate 34 receives a test pattern TPi-1 output from the previous cell 30_i-1 and a second mode signal B0 provided from the outside, and performs a logical multiplication operation. The exclusive OR gate 326 receives and computes output signals from the AND gates 32 and 34. The D-flip-flop 38 latches the output of the exclusive or gate 326 in synchronization with a clock signal CLK provided from the outside.

The CBIST cell 30_i having the configuration as described above is clocked every time while the first and second mode signals B1 and B2 are both at a high level (logic '1') (ie, while in the BIST mode). Each cycle combines the failure effect signal Di provided from the main combination circuit 10 and the test pattern TPi-1 output from the previous CBIST cell 30_i-1 to generate a new test pattern and at the same time the main Compress the fault effect of the previous test pattern through the combination circuit 10.

Such a CBIST circuit successfully performs a compression operation on a test pattern, but is inefficient in forming a random test pattern.

Accordingly, it is an object of the present invention to provide a circular built-in self test circuit which has been proposed to solve the above-mentioned problems and generates a test pattern more randomly.

1 is a block diagram schematically showing a conventional CBIST circuit;

FIG. 2 is a detailed circuit diagram of the CBIST cell shown in FIG. 1;

3 is a block diagram showing a CBIST circuit in accordance with a preferred embodiment of the present invention; And

4 is a circuit diagram showing in detail a CBIST cell according to a preferred embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

100: main combination circuit 200: CBIST circuit

210: multiplexer 300_1 to 300_n: CBIST cell

302 ~ 306 And Gate 308: Exclusive Oa Gate

310: D-flip-flop 312: inverter

According to a feature of the present invention for achieving the object of the present invention as described above, a circular built-in self test (CBIST) circuit for testing a main combination circuit includes a plurality of CBIST cells for generating a test pattern. . The CBIST cells are connected in series, and each of the CBIST cells is a fault provided from the main combination circuit and a test pattern output from a previous CBIST cell in response to a clock signal provided from an external source and first and second mode signals. The test signal is combined to generate the test pattern, and while in the test mode, the test pattern output from the previous CBIST cell, the fault effect signal provided from the main combination circuit, and the inverted signal of the test pattern output from the self are combined. Generate the test pattern.

In a preferred embodiment, the CBIST cell is provided from the main combination circuit in response to the first mode signal, the first logic circuit selectively outputting the inverted signal of the test pattern output from it while in the test mode. A second logic circuit for selectively outputting a failure effect signal, a third logic circuit for selectively outputting a test pattern output from a previous CBIST cell in response to the second mode signal, and an output from the first to third logic circuits And a latching means for latching a signal output from the pattern combining circuit in response to the clock signal.

In this embodiment, the first to third logic circuits are configured as end gates, respectively.

(Action)

By such a circuit, a circular built-in self test circuit which generates a more random test pattern can be implemented.

(Example)

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 3 to 4.

3 is a block diagram showing a CBIST circuit according to a preferred embodiment of the present invention.

Referring to FIG. 3, the CBIST circuit 200 includes n CBIST cells 300_1 to 300_n and a multiplexer 210 connected in series. The signals output from the CBIST cells 300_1 to 300_n are test patterns TP1 to TPn, and the test patterns TP1 to TPn are provided to the main combination circuit 100.

The multiplexer 210 normally provides a signal Sin provided from the outside as an input signal of the first CBIST cell 300_1, but provides a signal output from the last CBIST cell 300_n during the BIST mode to the first CBIST cell. A device for feeding back an input signal of 300_1. In other words, the multiplexer 20 generates a feedback loop while in the BIST mode, and operates in the same manner as a signature register, which is a compressor that is generally used.

The CBIST cells 300_1 to 300_n differ from the prior art in that they feed back a test pattern output from the CBIST cells 300_1 to 300_n.

4 is a circuit diagram showing in detail a CBIST cell according to a preferred embodiment of the present invention.

Referring to FIG. 4, the CBIST cell 300_i includes first to third AND gates 302 to 306, an exclusive_OR (XOR) gate 308, and a D-flip-flop ( 310 and an inverter 312.

The first AND gate 302 receives the inverted signal FB of the signal output from the first and second mode signals B1 and B2 and the D-flip-flop 310 and performs a logical multiplication operation. do.

The second AND gate 304 receives the first mode signal B1 and the failure effect signal Di provided from the main combination circuit 100 to perform a logical multiplication operation. The third AND gate 306 receives the second mode signal B2 and the test pattern TPi-1 output from the previous CBIST cell and performs a logical multiplication operation.

The exclusive-or-gate 308 receives and combines signals output from the first to third and gates 302 to 306. The D flip-flop 310 latches an output signal of the exclusive-or gate 308 in response to a clock signal CLK provided from the outside. The inverter 312 provides the inverted signal of the test pattern TPi output from the D-flip flop 310 to the first and gate 302.

Subsequently, the operation of the CBIST cell according to the preferred embodiment of the present invention will be described with reference to FIGS. 3 and 1. Table 1 summarizes the operation modes of the CBIST cell 300_i according to the states of the first and second mode signals B0 and B1.

TABLE 1

When the first and second mode signals B0 and B1 indicate a reset, scan or normal mode, the first and gate 302 may be connected to a state of a test pattern output from the D-flip-flop 310. Always outputs a low level signal regardless. Therefore, while in the reset, scan or normal mode, the CBIST cell 300_i of the present invention operates in the same manner as the conventional CBIST cell.

However, since the first and second mode signals B0 and B1 are both at high level while in the built-in self test (BIST) mode, the first AND gate 302 is output from the D-flip-flop. The inverted signal FB of the pattern is output as it is.

Therefore, the exclusive oar gate 308 is not only a failure effect signal Di output from the main combination circuit 10 but also a test pattern TPi-1 output from the previous CBIST cell 300_i-1. The inverted signal FB of the test pattern output from the combination is combined and output as a new test pattern. Here, the inverted signal FB of the test pattern output from the self is a previous test pattern output one time ahead of the current clock cycle.

In other words, the CBIST cell of the present invention uses the inverted signal of the test pattern generated in the previous cycle as the source signal for forming a new test pattern in the current cycle. By adopting such a method mainly for generating a logic '0' or only a logic '1', that is, a low randomness CBIST cell, a more random test pattern can be generated.

A method for replacing a low randomness CBIST cell with a CBIST cell of the present invention is as follows.

1. In the conventional CBIST circuit, the randomness of each CBIST cell is examined (ie, simulated every clock cycle to examine the ratio of logic '1' and logic '0' generation of each cell).

2. The CBIST cell with low randomness is replaced with the CBIST cell of the present invention.

In the above, the configuration and operation of the circuit according to the present invention are shown in accordance with the above description and drawings, but this is merely described, for example, and various changes and modifications are possible without departing from the spirit of the present invention. .

According to the present invention as described above, the CBIST cell generates a more random test pattern. Thus, test reliability is improved because the number of cases of test patterns for testing the main combination circuit is increased.

Claims (3)

In a circular built-in self test (CBIST) circuit for testing the main combination circuit: A plurality of CBIST cells for generating a test pattern; The CBIST cells are connected in series, and each of the CBIST cells is a fault provided from the main combination circuit and a test pattern output from a previous CBIST cell in response to a clock signal provided from an external source and first and second mode signals. The test signal is combined to generate the test pattern, and while in the test mode, the test pattern output from the previous CBIST cell, the fault effect signal provided from the main combination circuit, and the inverted signal of the test pattern output from the self are combined. And a circular built-in self test circuit for generating the test pattern. The method of claim 1, The CBIST cell, A first logic circuit for selectively outputting an inverted signal of a test pattern output from itself while in the test mode; A second logic circuit for selectively outputting a failure effect signal provided from the main combination circuit in response to the first mode signal; A third logic circuit selectively outputting a test pattern output from a previous CBIST cell in response to the second mode signal; A pattern combining circuit which receives and combines signals output from the first to third logic circuits; And And a latch means for latching a signal output from the pattern combination circuit in response to the clock signal. The method of claim 2, Wherein said first to third logic circuits are configured as end gates, respectively.