KR20010081844A - Decoder circuit in a semiconductor memory device - Google Patents

Abstract

PURPOSE: A decoder circuit is provided to prevent a malfunction of the circuit generated when word lines are inactive, by directly controlling an input voltage of a word line driving terminal when the word lines activated during the test are inactive. CONSTITUTION: The decoder circuit includes a plurality of word lines(WL1) and has a test operation. The test operation sequentially activates/inactivates the word lines(WL1). Decoders(100,110) decode an address for selecting a corresponding word line(WL1). A word line driver drives the corresponding word line in response to an output signal of the decoder. A decoder connection/separating circuit electrically connects the decoder and the driver when the word lines are sequentially activated and electrically separates the decoder and the driver when the word lines are sequentially inactivated.

Description

Decoder circuit of a memory semiconductor device {DECODER CIRCUIT IN A SEMICONDUCTOR MEMORY DEVICE}

The present invention relates to a memory semiconductor device, and more particularly, to a decoder circuit for driving a word line.

In general, memory semiconductor devices undergo various tests on finished products. During testing, high voltages can be applied for a long time, and multiple word lines can be activated simultaneously or sequentially. This is to examine the stability and reliability of the product operation by applying electrical stress from outside. In these tests, power supply noise may occur during word line deactivation, where the high voltage of a plurality of word lines transitions to the ground voltage, which may cause product operation problems.

1 is a circuit diagram showing a decoder circuit according to the prior art. The decoder is composed of a word line deactivation signal input terminal 10, a decoding terminal 20, and a word line driving stage 30.

The decoding stage 20 receives an input address and generates a signal for activating a corresponding word line. The decoding stage 20 includes a PMOS transistor MP1 and NMOS transistors MN2, MN3, MN4, and MN5. The drain of the PMOS transistor MP1 is connected to the power supply voltage Vcc terminal, the source is connected to the node N1, and the gate is connected to the word line activation signal WLE. The NMOS transistors MN2, MN3, MN4, and MN5 are connected in series with each other and the source of the NMOS transistor MN2 is connected to the node N1. The drain of the NMOS transistor MN5 is connected to the ground voltage Vss terminal. The input addresses DRA234, DRA56, DRA78, and DRA91011 are connected as shown in the gates of the NMOS transistors MN2, MN3, MN4, and MN5.

The word line driving stage 30 activates the word line when a signal for activating the word line is generated by the decoding stage 20. The word line driving stage 30 is composed of inverters I1 and I2 and NMOS transistors MN6, MN7 and MN8. An input terminal of the inverter I1 is connected to an output node N1 of the decoding terminal 20, and a gate of the NMOS transistor MN8 that deactivates a word line is connected. When the word line is inactivated, the source of the NMOS transistor MN8, which is a driver, is connected to the word line WLi and the drain is connected to the ground voltage Vss terminal. The output terminal of the inverter I1 is connected to one end of the NMOS transistor MN6. The other end of the NMOS transistor MN6 is connected to the gate of the NMOS transistor MN7 for the word line boost, and the gate of the NMOS transistor MN6 is connected to the power supply voltage Vcc terminal. The source of the NMOS transistor MN7 for the word line boost is connected to the word line boost signal PXi and the drain is connected to the word line WLi.

The word line deactivation signal stage 10 deactivates an activated word line in a test operation. The gate is composed of an NMOS transistor MN1 connected to a word line deactivation signal WLOFFD, and is connected between a power supply voltage Vcc terminal of the decoding terminal 20 and an N2 node.

In the operation of the circuit, when the word line activation signal WLE is activated at the beginning of the test operation, the PMOS transistor MP1 is turned off. When the addresses DAR234, DRA56, DRA78, and DRA91011 are inputted to activate the word line, the NMOS transistors MN2, MN3, MN4, and MN5 of the decoding stage 20 are turned on. The node N1 becomes the ground voltage Vss from the power supply voltage Vcc. When the NMOS transistor MN7 is turned on via the input terminal of the inverter I1, the word line WLi is activated.

Next, the word line deactivation signal WLOFFD is activated to deactivate the activated word line WLi. Addresses DRA234, DRA56, and DRA78 which deactivate the address DRA91011 input to the NMOS transistor MN5 and deactivate the word line are input. The NMOS transistors MN1, MN2, MN3, and MN4 are turned on and the node N1 becomes the power supply voltage Vcc. The NMOS transistor MN8 connected to the node N1 is turned on to deactivate the word line WLi.

When the NMOS transistors MN1, MN2, MN3, and MN4 are turned on in the process of deactivating the word line, voltage loss occurs due to the threshold voltages of the NMOS transistors MN1, MN2, MN3, and MN4. In fact, the node N1 becomes a voltage Vcc-Vt excluding the voltage loss caused by the threshold voltages of the NMOS transistors MN1, MN2, MN3, and MN4. The process of activating the word line is sequential, but the process of deactivating the word line fixes the address DRA91011 input to the NMOS transistor MN5 and changes only the addresses DRA234, DRA56, and DRA78 input to the NMOS transistor MN5. Therefore, a plurality of word lines are sequentially deactivated. When the word line transitions from the high voltage to the ground voltage Vss, power supply noise may occur and the node N1 may be lower than the voltage Vcc-Vt except for the voltage loss. In this case, when the voltage of the node N1 is lower than the operating voltage Vcc / 2 of the inverter I1, the word line cannot be inactivated. If the high potential Vcc + Vt is used as the power supply voltage Vcc in the decoder circuit, the inverter I1 does not operate properly because the operating voltage (Vcc + Vt) / 2 of the inverter I1 becomes high.

An object of the present invention is to provide a decoder that operates by separating an input address decoding stage and a word line driving stage of a decoder during a test operation.

1 is a circuit diagram showing a decoder according to the prior art;

2 is a block diagram showing a control relationship of a decoder according to the present invention;

3 is a preferred embodiment of the decoder circuit shown in FIG. 2;

4 is a circuit diagram showing the word line deactivation signal generation circuit shown in FIG.

FIG. 5 is a circuit diagram showing a word line activation signal generation circuit shown in FIG. 2; FIG.

FIG. 6 is a circuit diagram showing a word line boost signal generation circuit shown in FIG. 2; FIG. And

FIG. 7 is a timing diagram illustrating an operation of the decoder circuit shown in FIG. 2.

* Explanation of symbols on main parts of the drawings

10: word line deactivation signal stage 20: decoding stage

30: word line driving stage 100: predecoder circuit

110: decoder circuit 111: decoding stage

112: decoder connection / disconnection circuit 113: word line drive stage

120: word line inactivation signal generation circuit

130: word line activation signal generating circuit

140: word line boost signal generating circuit 150: mode register set circuit

160: sense amplifier 170: cell array

(Configuration)

According to a feature of the present invention, a decoder circuit having a plurality of word lines is provided and allows the word lines to be activated sequentially and the activated word lines to be sequentially deactivated in a test operation mode. The decoder circuit includes a decoding stage for decoding an address for selecting a corresponding word line; A driving stage for driving the corresponding word line in response to an output signal of the decoding stage; And circuitry electrically connecting the decoding stage and the driving stage when the word lines are sequentially activated, and electrically separating the decoding stage and the driving stage when the word lines are sequentially inactive.

In this embodiment, the circuit connecting / disconnecting the decoding stage and the driving stage uses a transfer gate for electrically connecting / disconnecting the decoding stage and the driving stage in response to a control signal.

In this embodiment, a switch for connecting the input terminal of the driving means to a power supply voltage by the control signal is used.

In this embodiment, the control signal uses a signal synchronized with the mode register.

In this embodiment, the circuit connecting / disconnecting the decoding stage and the driving stage operates only in the test mode.

(Action)

Such a device can prevent the malfunction of the decoder circuit when the word line is deactivated in the test mode.

(Example)

Embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

2 is a block diagram showing a control relationship of a decoder according to the present invention. The predecoder 100, the main decoder 110, the word line deactivation signal generating circuit 120, the word line activation signal generating circuit 130, the word line boost signal generating circuit 140 and the mode register set circuit 150, Sense amplifier 160, and a cell array 170 including a memory cell (MEMORY CELL). Initially, the control signal WLE of the word line activation signal generation circuit 130 is activated to activate the word line. The address DRAij is input to the main decoder 110 through the predecoder 100. In this case, when the word line boost signal PXi is activated from the word line boost signal generation circuit 140, the corresponding word line WL1 is activated. The word lines are sequentially activated as the address DRAij changes. Subsequently, when the word line is inactivated, the control signal WLOFF / WLOFFD of the word line deactivation signal generation circuit 120 is activated by the mode register set circuit 150. When the address DRAij is input to the main decoder 110 through the predecoder 100, the corresponding word line WL1 is inactivated. As the address DRAij changes, word lines are sequentially inactivated. When all of the word lines are deactivated, the control signals WLOFF / WLOFFD of the word line deactivation signal generation circuit 120 are deactivated, and the word line boost signal PXi is deactivated. The control signal WLE of the word line activation signal generation circuit 130 is inactivated to be in a precharge state.

3 is a circuit diagram showing a decoder circuit according to the present invention. The decoder is composed of a decoding stage 111, a decoder connection / separation circuit 112 and a word line driver stage 113.

The decoding stage 111 receives an input address and generates a signal for activating a corresponding word line, and includes a PMOS transistor MP10 and NMOS transistors MN10, MN20, MN30, and MN40. The drain of the PMOS transistor MP10 is connected to the power supply voltage Vcc terminal, the source is connected to the node N1, and the gate is connected to the word line activation signal WLE. The NMOS transistors MN10, MN20, MN30, and MN40 are connected in series with each other, and the source of the NMOS transistor MN10 is connected to the node N10. The drain of the NMOS transistor MN40 is connected to the ground voltage Vss terminal. The input addresses DRA234, DRA56, DRA78, and DRA91011 are connected as shown in the gates of the NMOS transistors MN10, MN20, MN30, and MN40.

The word line driving stage 112 includes an inverter I30 and NMOS transistors MN50, MN60, MN70, and MN80 for activating the word line when a signal for activating the word line is generated by the decoding stage 111. An input terminal of the inverter I30 is connected to the node N30, and a gate of the NMOS transistor MN80 for deactivating a word line is connected. The source of the NMOS transistor MN80 operating when the word line is inactivated is connected to the word line WLi and the drain is connected to the ground voltage Vss terminal. The output terminal of the inverter I30 is connected to one end of the NMOS transistor MN60 and the other end of the NMOS transistor MN60 is connected to the gate of the NMOS transistor MN70 for word line boosting. The gate of the NMOS transistor MN60 is connected to the power supply voltage Vcc terminal. The source of the NMOS transistor MN70 for the word line boost is connected to the word line boost signal PXi and the drain is connected to the word line WLi.

The decoder connection / disconnection circuit 112 connects the input terminal N30 of the inverter I30 to the node N10 of the decoding terminal when activating a word line in a test operation. When the word line is inactivated, the input terminal N30 of the inverter I30 is connected to the power supply voltage Vcc. Inverter I10, transfer gates TM10 and TM20 and transfer gates TM10 and TM20 connected to the control signal WLOFF of the word line deactivation signal generation circuit 120 and the control signal WLOFFD having a predetermined delay. And PMOS switches MP30 and MP40 connected to an inverter I20, a power voltage Vcc terminal, and a gate thereof. The connections of each configuration are connected as shown.

In the operation of the circuit, when the word line is activated at the beginning of the test operation, the control signal WLE of the word line activation signal generation circuit 130 is activated to turn off the PMOS transistor MP10. Next, the control signal WLOFF / WLOFFD of the word line deactivation signal generation circuit 120 is deactivated and the PMOS transistor MP30 connected to the power supply voltage Vcc terminal is turned on. The node N20 is in a power supply voltage Vcc state. Next, when the addresses DAR234, DRA56, DRA78, and DRA91011 are input to activate the word line, the NMOS transistors MN10, MN20, MN30, and MN40 of the decoding terminal 111 are turned on. The node N10 becomes the ground voltage Vss. The potential of the node N10 reaches the input terminal of the inverter I30 through the transfer gate TM10. The NMOS transistor MN70 is turned on to activate the word line WLi.

To deactivate the activated word line WLi, the control signal WLOFFD / WLOFFD of the word line deactivation signal generating circuit 120 is activated, and the addresses DRA234, DRA56, DRA78, and DRA91011 for deactivating the word line are input. do. The NMOS transistors MN10, MN20, MN30, and MN40 are turned on and the node N10 becomes the ground voltage Vss. Next, the node N20 changes from the power supply voltage Vcc state to the ground voltage Vss state through the transfer gate TM20. The PMOS transistor MP40 connected to the node N20 is turned on. When the NMOS transistor MN80 is turned on, the word line WLi is inactivated.

Unlike the process of deactivating the conventional word line, since the voltage of the node N30 is the power supply voltage Vcc without the loss of the threshold voltage of the transistor, and the input addresses DRA234, DRA56, DRA78, and DRA91011 are all changed. This becomes a process of sequentially deactivating word lines. In this case, when the word line transitions from the high voltage to the ground voltage (Vss), power supply noise rarely occurs, and when the voltage of the node N30 is lower than the operating voltage (Vcc / 2) of the inverter I30, it causes malfunction. There will be no.

When a high voltage (Vcc + Vt, referred to as Vpp) is used as the power supply voltage in the decoder circuit, the voltage of the node N30 is increased to the high voltage (Vpp), thereby improving the characteristics of power supply noise. 4, 5, and 6 illustrate a word line deactivation signal generation circuit 120, a word line activation signal generation circuit 130, and a word line boost signal generation circuit 140 when the power supply voltage of the decoder is used as the high voltage Vpp. Shows the configuration. Each circuit adds a level shifter LS for changing the power supply voltage Vcc to a high voltage Vpp at the control signal output stage so that the output signal becomes a high voltage Vpp.

7 is a timing diagram illustrating a process in which a word line is activated and then deactivated in a memory semiconductor device.

Since / CS and / RAS are low level and / CAS and / WE are high level up to the (n + 1) th clock, this command activates the word line of the corresponding address. In this case, the word line boost signal PXi receives the decoded address DRA01 as shown in FIG. 6. As shown in FIG. 7, the word line boost signal PXi must be active during the test process, and thus the decoded address DRA01 must be the same. Therefore, one of four word lines is sequentially activated and deactivated. The (n-8) th word line WL (8) is activated by receiving the (n-8) th address from the (n-1) th clock where the word line is activated. The (n-4) and (n) th addresses are input from the (n), (n + 1) th clocks. The process of sequentially activating word lines by activating the (n-4) and (n) th word lines WL (n-4) and WL (n) is completed. Next, the (0) th address is input from the (n + 2) th clock to prepare for deactivating the word line. Since the input signals (/ CS, / RAS, / CAS, / WE) are all at low level at the (n + 3) th clock, it is a command to set the mode register by receiving the key address and the control signal (by the mode register). PMRS) is synchronized. As shown in FIG. 4 and the control signal PMRS is activated, the transfer gate TM30 operates. The output signal WLOFF / WLOFFD of the word line deactivation signal generating circuit 120 is activated and the (0) th word line WL (0) is deactivated to start the process of deactivating the word line. At the (n + 5) th clock, the fourth address is input and the corresponding fourth word line WL (4) is deactivated. Next, the (n-4) and (n) th addresses are input from the (n + 7), (n + 8) th clocks. As the (n-4) and (n) th word lines WL (n-4) and WL (n) are inactivated, all word lines are inactivated. At the (n + 9) th clock, / CS, / RAS, and / WE are all low level and / CAS is high level, so this is a precharge command. When the control signal PRE is activated, as illustrated in FIG. 4, the output signals WLOFF / WLOFFD of the word line deactivation signal generation circuit 120 are deactivated. The output signal WLE of the word line activation signal generation circuit 130 of FIG. 5 and the output signal PXi of the word line boost signal generation circuit 140 of FIG. 6 are inactivated. The decoder of the present invention also becomes a precharge state when the output signal WLE of the word line activation signal generation circuit 130 is inactivated.

According to a preferred embodiment of the present invention, an operation error caused by power supply noise can be solved by sequentially deactivating a word line activated by a control signal in the test mode and improving an input voltage of a word line driving stage of the decoder.

Claims (3)

In the decoder circuit of the semiconductor memory device having a test operation mode having a plurality of word lines, the word lines are sequentially activated and the activated word lines are sequentially inactivated: Decoding means for decoding an address for selecting a corresponding word line; Driving means for driving the corresponding word line in response to an output signal of the decoding means; Means for electrically connecting said decoding means and said driving means when said word lines are sequentially activated, and electrically separating said decoding means and said driving means when said word lines are sequentially deactivated, And the means sets the potential of the input terminal of the driving means to a power supply voltage irrespective of power supply noise generated when the word line is deactivated. The method of claim 1, The means for connecting / disconnecting the decoding means and the driving means comprises: a transfer gate for electrically connecting / disconnecting the decoding means and the driving means in response to a control signal; And a switch for connecting the input terminal of the driving means to a power supply voltage by the control signal. The method of claim 2, And the control signal is synchronized with a mode register signal.