KR20010081761A - A method of a contact hole in a semiconductor device - Google Patents
A method of a contact hole in a semiconductor device Download PDFInfo
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- KR20010081761A KR20010081761A KR1020000007864A KR20000007864A KR20010081761A KR 20010081761 A KR20010081761 A KR 20010081761A KR 1020000007864 A KR1020000007864 A KR 1020000007864A KR 20000007864 A KR20000007864 A KR 20000007864A KR 20010081761 A KR20010081761 A KR 20010081761A
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- 238000000034 method Methods 0.000 title claims abstract description 41
- 239000004065 semiconductor Substances 0.000 title abstract description 14
- 238000005530 etching Methods 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 27
- 239000002019 doping agent Substances 0.000 claims abstract description 17
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 6
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- 239000000203 mixture Substances 0.000 claims description 4
- VSHBTVRLYANFBK-UHFFFAOYSA-N ozone sulfuric acid Chemical compound [O-][O+]=O.OS(O)(=O)=O VSHBTVRLYANFBK-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 17
- 238000000576 coating method Methods 0.000 abstract description 3
- 239000011248 coating agent Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 79
- 239000011229 interlayer Substances 0.000 description 34
- 229910052751 metal Inorganic materials 0.000 description 18
- 239000002184 metal Substances 0.000 description 18
- 229920002120 photoresistant polymer Polymers 0.000 description 15
- 238000001039 wet etching Methods 0.000 description 15
- 238000009792 diffusion process Methods 0.000 description 8
- 238000000137 annealing Methods 0.000 description 6
- 238000000151 deposition Methods 0.000 description 6
- 238000001312 dry etching Methods 0.000 description 6
- 239000012535 impurity Substances 0.000 description 6
- 238000004544 sputter deposition Methods 0.000 description 6
- 239000000126 substance Substances 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- -1 B 2 O 3 Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000009471 action Effects 0.000 description 2
- 238000004380 ashing Methods 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000001154 acute effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
본 발명은 반도체장치의 콘택홀 형성방법에 관한 것으로서, 특히, 콘택홀이 형성될 하지층의 도판트 농도를 화학적 처리를 통하여 변화시킨 다음 습식식각과 건식식각의 두 단계 식각으로 하지층의 소정 부위를 제거하여 상부 반경이 하부 반경보다 큰 콘택홀을 형성하므로서 후속공정에서 콘택홀에 증착되는 층의 단차피복도를 개선하도록 한 반도체장치의 프로파일이 개선된 콘택홀 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact hole in a semiconductor device, and in particular, by changing a dopant concentration of a base layer on which a contact hole is to be formed through chemical treatment, and then performing a wet etching process and a dry etching process, a predetermined portion of a base layer is formed. The present invention relates to a method for forming a contact hole in which the profile of a semiconductor device is improved so that the upper radius is larger than the lower radius to form a contact hole, thereby improving the step coverage of the layer deposited in the contact hole in a subsequent process.
차세대 고집적소자가 더욱 고밀도로 형성됨에 따라 반도체장치의 소자를 전기적으로 연결하기 위한 배선형성공정도 더욱 정밀도를 요구하고 그에 따라 공정도 복잡해진다.As next-generation high-density devices are formed at higher densities, the wiring forming process for electrically connecting the devices of the semiconductor device also requires more precision, and the process becomes complicated.
서로 다른 층에 형성된 소자들을 전기적으로 연결하기 위하여 콘택홀 또는 비어홀들을 형성하게 되는데, 이러한 홀들의 반경이 더욱 작아지고 단차가 커지게 된다.Contact holes or via holes are formed to electrically connect devices formed in different layers, and the radius of these holes becomes smaller and the step height becomes larger.
이러한 홀에 금속배선을 효과적으로 증착하기 위해서 금속배선의 피복방법을 개선하거나 금속배선이 증착되는 홀의 프로파일 경사를 완만하게 형성하는 방법이 있다.In order to effectively deposit the metal wiring in such a hole, there is a method of improving the coating method of the metal wiring or gently forming the profile slope of the hole in which the metal wiring is deposited.
도 1a 내지 도 1g는 종래 기술에 따른 반도체장치의 콘택홀 형성방법을 도시한 공정단면도이다.1A to 1G are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to the related art.
도 1a를 참조하면, 반도체 기판인 실리콘 기판(10) 위에 산화막인 게이트절연막(도시안함), 도핑된 폴리실리콘층(12)을 형성한 다음, 이 들을 포토리쏘그래피로 패터닝하여 게이트(12)를 형성한다.Referring to FIG. 1A, a gate insulating film (not shown), a doped polysilicon layer 12, which is an oxide film, and a doped polysilicon layer 12 are formed on a silicon substrate 10, which is a semiconductor substrate, and then the gate 12 is patterned by photolithography. Form.
그리고, 소스/드레인(도시안함)을 이온주입 등으로 형성한다. 만약, 엘디디(lightly doped drain) 구조의 트랜지스터를 형성할 경우 저농도 불순물 확산영역(도시 안함)을 형성한다.The source / drain (not shown) is formed by ion implantation or the like. If a transistor having a lightly doped drain structure is formed, a low concentration impurity diffusion region (not shown) is formed.
그리고, 이러한 게이트패턴의 측면을 절연시키는 측벽 스페이서(13)를 기판의 전면에 질화막을 증착한 다음 에치백하여 형성한다. 이때, 기판 표면을 식각정지층으로 이용한다.The sidewall spacers 13 that insulate the side surfaces of the gate patterns are formed by depositing a nitride film on the entire surface of the substrate and then etching back. In this case, the substrate surface is used as an etch stop layer.
엘디디 구조를 형성할 경우 측벽 스페이서(13)를 이용하여 저농도 불순물 확산영역 옆에 고농도 불순물 확산영역을 형성한다.When the LED structure is formed, a high concentration impurity diffusion region is formed next to the low concentration impurity diffusion region using the sidewall spacers 13.
그 다음, 상기 트랜지스터를 포함하는 구조물을 포함하는 기판의 전면에 층간절연층(14)으로 산화막을 화학기상증착법으로 증착하여 형성한다. 이때,층간절연층(14)은 평탄도를 개선하기 위하여 어닐링에서 흐름성(reflow)이 우수한 절연층으로 형성되며, 특히, 붕소(boron)와 인(phosphor)을 소정의 농도로 포함하고 있으며 절연층 내부는 B2O3, P2O5와 같은 화합물의 형태를 갖는다. 그리고, 증착된 층간절연층(14)은 게이트(12)가 기판(10) 표면 위로 돌출되어 있기 때문에 단차가 크므로 게이트(12)를 덮는 층간절연층(14)의 단차 또한 이와 유사한 패턴을 갖게 된다.Next, an oxide film is formed by chemical vapor deposition on the front surface of the substrate including the structure including the transistor by the interlayer insulating layer 14. In this case, the interlayer insulating layer 14 is formed of an insulating layer having excellent reflow during annealing in order to improve flatness. In particular, the interlayer insulating layer 14 includes boron and phosphorus at a predetermined concentration and is insulated. The inside of the layer has the form of a compound such as B 2 O 3 , P 2 O 5 . Since the deposited interlayer insulating layer 14 has a large step because the gate 12 protrudes over the surface of the substrate 10, the step of the interlayer insulating layer 14 covering the gate 12 also has a similar pattern. do.
도 1b를 참조하면, 단차가 큰 층간절연층에 어닐링 등의 열공정을 실시하여 리플로잉(reflowing)시켜 층간절연층(140) 상부 표면의 평탄도를 개선한다. 즉, 상기한 화합물로 도핑되어 유동성이 큰 층간절연층(140)에 열을 가하면 단차가 큰 부위에 있던 층간절연층이 단차가 낮은곳으로 흘러서 단차를 감소시키게 된다. 이와 같은 작용을 리플로잉이라 한다.Referring to FIG. 1B, the flatness of the upper surface of the interlayer insulating layer 140 is improved by reflowing by performing a thermal process such as annealing on the interlayer insulating layer having a large step. That is, when the doped with the above compound and heat is applied to the interlaminar insulating layer 140 having high fluidity, the interlayer insulating layer in a large step portion flows to a low step to reduce the step. This action is called reflowing.
따라서, 리플로잉된 층간절연층(140)의 표면은 완만한 경사를 갖게 되어 콘택홀 형성용 포토레지스트를 사용하는 사진공정을 용이하게 하고 홀 형상 후의 프로파일 개선에 유용하다.Therefore, the surface of the reflowed interlayer insulating layer 140 has a gentle inclination, which facilitates the photolithography process using the photoresist for forming contact holes and is useful for improving the profile after the hole shape.
도 1c를 참조하면, 단차가 개선된 층간절연층(140) 상에 포토레지스트를 도포한 다음 소스/드레인이 형성된 기판 표면의 상부에 대응하는 포토레지스트 부위를 노광 및 현상하여 포토레지스트패턴(15)을 형성한다.Referring to FIG. 1C, a photoresist is applied on an interlayer insulating layer 140 having improved step height, and then a photoresist pattern 15 is exposed and developed by exposing and developing a photoresist portion corresponding to an upper portion of a substrate surface on which a source / drain is formed. To form.
도 1d를 참조하면, 포토레지스트패턴(15)을 식각마스크로 이용하여 층간절연층(141)의 노출 부위를 습식식각 등의 등방성식각으로 소정 깊이 만큼만 제거한다. 이때, 등방성식각은 BOE계열의 식각용액으로 실시하고, 등방성식각이므로 기판과 수직한 방향 뿐만 아니라 수평한 방향 즉, 측방향으로도 식각이 진행된다. 일반적으로 수평방향 대 수직방향의 식각비는 약 2.5:1에서 약 3:1의 비율을 갖는다. 이와 같은 비율에 따라 콘택홀의 프로파일 내지는 형상이 변화하므로 이러한 비율의 제어가 콘택홀의 특성개선에 필수적이다.Referring to FIG. 1D, the exposed portion of the interlayer insulating layer 141 is removed only by a predetermined depth by isotropic etching, such as wet etching, by using the photoresist pattern 15 as an etching mask. At this time, the isotropic etching is performed with an etching solution of the BOE series, and isotropic etching, the etching proceeds not only in a direction perpendicular to the substrate but also in a horizontal direction, that is, in a lateral direction. In general, the horizontal to vertical etch ratio is about 2.5: 1 to about 3: 1. Since the profile or shape of the contact hole changes according to such a ratio, control of this ratio is essential for improving the characteristics of the contact hole.
도 1e를 참조하면, 포토레지스트패턴(15)을 잔류시킨채 일차 등방성식각되어 잔류하며 노출된 층간절연층(142)의 표면에 플라즈마등을 사용하는 비등방성식각을 실시하여 기판의 소스/드레인 표면이 노출되도록 한다. 이때, 비등방성식각으로 식각이 이루어지므로 기판의 수직방향으로만 시각이 진행되어 시각 프로파일은 수직이 된다.Referring to FIG. 1E, the source / drain surface of the substrate is subjected to anisotropic etching using a plasma or the like on the surface of the interlayer insulating layer 142 that remains after being first isotropically etched while the photoresist pattern 15 remains. To be exposed. At this time, since the etching is performed by anisotropic etching, the viewing process proceeds only in the vertical direction of the substrate, and the viewing profile becomes vertical.
도 1f를 참조하면, 식각마스크로 사용된 포토레지스트패턴을 산소 애슁등의 방법으로 제거하여 잔류한 층간절연층(142)의 표면을 노출시킨다. 따라서, 콘택홀의 형성이 완료된다.Referring to FIG. 1F, the surface of the remaining interlayer insulating layer 142 is exposed by removing a photoresist pattern used as an etching mask by a method such as oxygen ashing. Thus, formation of the contact hole is completed.
그러나, 이와 같이 형성된 콘택홀의 상부 프로파일은 아직도 수직에 가까우므로 후속 공정에서 증착되는 금속층 등의 단차피복도를 크게 개선하는데 미흡하다.However, since the upper profile of the contact hole thus formed is still close to the vertical, it is insufficient to greatly improve the step coverage of the metal layer or the like deposited in the subsequent process.
도 1g를 참조하면, 노출된 기판 표면, 즉, 소스/드레인과 전기적으로 접촉하도록 콘택홀 내부 표면을 포함하는 층간절연층(142) 상에 소정의 금속층(16)을 스퍼터링 등의 방법으로 증착하여 형성한다. 이때, 증착되는 금속층(16)의 단차피복도는 전술한 바와 같이 양호하지 못하다.Referring to FIG. 1G, a predetermined metal layer 16 is deposited on the exposed substrate surface, that is, the interlayer insulating layer 142 including the contact hole inner surface so as to be in electrical contact with the source / drain by sputtering or the like. Form. At this time, the step coverage of the deposited metal layer 16 is not good as described above.
반도체소자의 고집적화에 따라 콘택부의 선폭이 감소하고 단차는 커지게 된다. 이는 콘택홀 자체의 형성도 곤란하게 할 뿐만 아니라 콘택홀에 매립되는 금속층 등의단차피복도를 감소시키게 된다. 이와 같은 현상을 개선하기 위하여 종래 기술에서는 하지콘택막인 층간절연층의 도판트 농도를 높여서 어닐링을 실시하여 평탄도를 향상시키는 방법을 사용한다.As the semiconductor device is highly integrated, the line width of the contact portion decreases and the step height increases. This not only makes it difficult to form the contact hole itself, but also reduces the step coverage of a metal layer or the like embedded in the contact hole. In order to improve such a phenomenon, the prior art uses a method of improving the flatness by annealing by increasing the dopant concentration of the interlayer insulating layer, which is a base contact film.
그러나, 상기한 방법으로 형성한 콘택홀은 단차가 크기 때문에 이후 콘택홀에 증착되는 금소배선용 금속층은 스퍼터링으로 형성하기 곤란하여 화학기상증착을 이용하는 증착방법이 일반적으로 병행된다.However, since the contact hole formed by the above-described method is large in size, the metal layer for metal wiring to be subsequently deposited in the contact hole is difficult to be formed by sputtering, and thus a deposition method using chemical vapor deposition is generally used in parallel.
또한, 스퍼터링방법에서는 선택적성장을 이용하는 매립방법이 있으나 아직 양산에 적용하기에는 곤란하며 추가적인 선택비 및 증착속도 제어기술이 필요하다. 스퍼터링방법 중 먼저 알루미늄 등을 증착한 후 리플로잉시켜 평탄화하는 방법이 있으나 배선저항의 감소 또는 금속내의 입자간 표면장력 등에 기인한 포집현상으로 배선내에 공극 등이 발생하는 문제점이 있다.In addition, the sputtering method has a landfill method using selective growth, but it is still difficult to apply to mass production, and additional selection ratio and deposition rate control techniques are required. Among sputtering methods, there is a method of first depositing aluminum and then reflowing to planarize, but there is a problem that voids occur in the wiring due to collection phenomenon due to reduction of wiring resistance or intergranular surface tension in metal.
따라서, 본 발명의 목적은 콘택홀이 형성될 하지층의 도판트 농도를 화학적 처리를 통하여 변화시킨 다음 습식식각과 건식식각의 두 단계 식각으로 하지층의 소정 부위를 제거하여 상부 반경이 하부 반경보다 큰 콘택홀을 형성하므로서 후속공정에서 콘택홀에 증착되는 층의 단차피복도를 개선하도록 한 반도체장치의 프로파일이 개선된 콘택홀 형성방법을 제공하는데 있다.Accordingly, an object of the present invention is to change the dopant concentration of the underlying layer on which the contact hole is to be formed through chemical treatment, and then to remove certain portions of the underlying layer by wet etching and dry etching. The present invention provides a method for forming a contact hole in which a profile of a semiconductor device is improved to form a large contact hole, thereby improving the step coverage of a layer deposited in the contact hole in a subsequent process.
상기 목적들을 달성하기 위한 본 발명에 따른 반도체장치 콘택홀 형성방법은 기판상에 도판트로 도핑되어 흐름성이 우수한 재료로 피식각층을 형성하는 단계와, 상기 피삭각층을 리플로잉시켜 평탄도를 개선하는 단계와, 상기 피식각층의 표면 부위의 상기 도판트 농도를 감소시키는 단계와, 상기 피식각층상에 홀 형성부위를 정의하는 식각마스크를 형성하는 단계와, 노출된 상기 홀 형성부위의 상기 피식각층을 소정 깊이 까지 등방성식각으로 상기 식각마스크 하부의 상기 피식각층도 식각되도록 언더에치하는 단계와, 상기 식각마스크를 이용하는 비등방성식각을 상기 언더에치된 상기 피식각층에 실시하여 상기 기판의 소정 부위를 노출시키는 홀을 형성하는 단계를 포함하여 이루어진다.According to an aspect of the present invention, there is provided a method of forming a contact hole in a semiconductor device, the method comprising: forming an etched layer of a material having excellent flowability by doping with a dopant on a substrate; Reducing the dopant concentration of the surface portion of the etched layer, forming an etch mask defining a hole forming portion on the etched layer, and exposing the etched layer of the exposed hole forming portion Underetching the etched layer under the etch mask by isotropic etching to a predetermined depth, and performing anisotropic etching using the etch mask on the underetched etched layer to form a predetermined portion of the substrate. And forming a hole exposing the hole.
도 1a 내지 도 1g는 종래 기술에 따른 반도체장치의 콘택홀 형성방법을 도시한 공정단면도1A to 1G are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to the related art.
도 2a 내지 도 2h는 본 발명에 따른 반도체장치의 콘택홀 형성방법을 도시한 공정단면도2A through 2H are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to the present invention.
본 발명은 습식식각과 건식식각으로 이루어진 두단계 식각공정을 통하여 콘택홀을 형성하지만, 일차 습식식각 실시전 단계에서 피식각층의 표면 도판트 농도를 변화시켜 습식식각시 노출부위의 측면식각량을 크게하여 콘택홀의 상부 지름을 확장시킨 다음 비등방성식각으로 나머지 피식각층을 제거하여 콘택홀의 하부구조를 완성하면 콘택홀의 상부 프로파일은 더욱 완만해지게 되어 후속 금속배선 형성공정시 단차피복도를 크게 개선한다.The present invention forms a contact hole through a two-step etching process consisting of wet etching and dry etching. However, the surface dopant concentration of the layer to be etched is changed in the step before the first wet etching, thereby greatly increasing the side etching amount of the exposed part during wet etching. By expanding the upper diameter of the contact hole and then removing the remaining etched layer by anisotropic etching to complete the lower structure of the contact hole, the upper profile of the contact hole becomes more gentle, which greatly improves the step coverage during the subsequent metallization process.
즉, 본 발명은 콘택홀을 형성하기 위하여 도핑된 산화막을 증착한 다음 일차 콘택 습식식각시 측면 식각량을 증가시키고 이차 건식식각으로 최종 콘택홀을 완성하여 이후 금속배선층의 단차피복특성을 개선한다.That is, according to the present invention, the doped oxide layer is deposited to form a contact hole, and then the side etching amount is increased during the wet etching of the first contact, and the final contact hole is completed by the secondary dry etching, thereby improving the step coating characteristics of the metallization layer.
콘택홀을 형성하기 위하여 먼저 습식식각을 실시하는 이유는 다음과 같다.The first reason for performing wet etching to form the contact hole is as follows.
피식각층에 대하여 건식식각만으로 콘택홀을 형성하게 되면 최초 개구부가 작고 단차가 크게되며 콘택홀 상부 모서리부가 예각에 가까워져서 증착되는 금속층의 오버행(overhang)이 커지게되어 단차피복도가 열화된다.If the contact hole is formed only by dry etching with respect to the layer to be etched, the initial opening is small, the step height is large, and the upper edge portion of the contact hole is closer to the acute angle, resulting in an overhang of the deposited metal layer, thereby increasing the step coverage.
그러나, 습식식각을 채용하면 최초 개구부의 지름이 커지고 단차가 습식식각되어진 깊이만큼 감소하게 되어 금속배선의 단차피복도를 개선한다. 또한, 콘택홀 상부 모서리의 피삭각층 표면과 콘택홀 프로파일이 이루은 각도가 커지게 되어 금속배선층의 오버행정도를 감소시킨다.However, when the wet etching is adopted, the diameter of the initial opening is increased and the step is reduced by the depth of the wet etching, thereby improving the step coverage of the metal wiring. In addition, the angle formed between the surface of the cutting layer on the upper edge of the contact hole and the contact hole profile is increased to reduce the degree of overhang of the metal wiring layer.
따라서, 이러한 장점을 콘택홀 형성에 적용하기 위하여 습식식각과 건식식각을 병행하게 된다.Therefore, wet etching and dry etching are combined in order to apply these advantages to contact hole formation.
피식각층상에 형성된 포토레지스트패턴을 이용하여 콘택홀을 형성시, 등방성식각인 습식식각은 식각방향이 피식각층 수평방향과 수직방향으로 동시에 진행되기 때문에 수평식각량 대 수직식각량의 비율이 습식식각의 특성을 나타내는 주요 인자가 된다. 일반적으로 산화막에 대한 수평방향 대 수직방향 식각비율은 약 2.5:1 또는 약 3:1 정도이므로 이를 이용하여 콘택홀을 식각한다.When the contact hole is formed using the photoresist pattern formed on the etched layer, the wet etching, which is an isotropic etching, is performed simultaneously in the horizontal direction and the vertical direction of the etched layer, so that the ratio of the horizontal etching amount to the vertical etching amount is wet etching. It is a major factor in the characterization of. In general, since the horizontal to vertical etch ratio with respect to the oxide layer is about 2.5: 1 or about 3: 1, the contact hole is etched using the etch rate.
본 발명에서는 도핑된 산화막으로 이루어진 피식각층에 화학처리를 실시하여 산화막 표면의 도판트 농도를 감소시켜 습식식각시 측면식각량을 증가시키며, 또한, 소정 깊이까지는 도판트의 농도가 감소된 상태이므로 습식식각이 진행될수록 초기 산화막에 대한 어닐링 실시 후의 상태와 유사한 표면상태를 갖는다.In the present invention, by performing a chemical treatment on the etched layer of the doped oxide film to reduce the dopant concentration on the surface of the oxide film to increase the side etching amount during the wet etching, and also because the concentration of the dopant is reduced to a predetermined depth is wet As the etching proceeds, the surface state is similar to that after annealing the initial oxide film.
이하, 첨부한 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2h는 본 발명에 따른 반도체장치의 콘택홀 형성방법을 도시한 공정단면도이다.2A to 2H are cross-sectional views illustrating a method of forming a contact hole in a semiconductor device according to the present invention.
도 2a를 참조하면, 반도체 기판인 실리콘 기판(20) 위에 산화막인 게이트절연막(도시안함), 도핑된 폴리실리콘층(21)을 형성한 다음, 이 들을 포토리쏘그래피로 패터닝하여 게이트(21)를 형성한다.Referring to FIG. 2A, a gate insulating film (not shown) and a doped polysilicon layer 21 are formed on a silicon substrate 20, which is a semiconductor substrate, and then patterned by photolithography to form a gate 21. Form.
그리고, 소스/드레인(도시안함)을 이온주입 등으로 형성한다. 만약, 엘디디(lightly doped drain) 구조의 트랜지스터를 형성할 경우 저농도 불순물 확산영역(도시 안함)을 형성한다.The source / drain (not shown) is formed by ion implantation or the like. If a transistor having a lightly doped drain structure is formed, a low concentration impurity diffusion region (not shown) is formed.
그리고, 이러한 게이트패턴의 측면을 절연시키는 측벽 스페이서(22)를 기판의 전면에 질화막을 증착한 다음 에치백하여 형성한다. 이때, 기판 표면을 식각정지층으로 이용한다.The sidewall spacers 22 that insulate the sidewalls of the gate pattern are formed by depositing a nitride film on the entire surface of the substrate and then etching back. In this case, the substrate surface is used as an etch stop layer.
엘디디 구조를 형성할 경우 측벽 스페이서(22)를 이용하여 저농도 불순물 확산영역 옆에 고농도 불순물 확산영역을 형성한다.When the LED structure is formed, a high concentration impurity diffusion region is formed next to the low concentration impurity diffusion region using the sidewall spacers 22.
그 다음, 상기 트랜지스터를 포함하는 구조물을 포함하는 기판의 전면에 층간절연층(230)으로 산화막을 화학기상증착법으로 증착하여 형성한다. 이때, 층간절연층(230)은 평탄도를 개선하기 위하여 어닐링에서 흐름성(reflow)이 우수한 절연층으로 형성되며, 특히, 붕소(boron)와 인(phosphor)을 소정의 농도로 포함하고 있으며 절연층 내부는 B2O3, P2O5와 같은 화합물의 형태를 갖는다. 그리고, 증착된 층간절연층(230)은 게이트(21)가 기판(20) 표면 위로 돌출되어 있기 때문에 단차가 크므로 게이트(21)를 덮는 층간절연층(230)의 단차 또한 이와 유사한 패턴을 갖게 된다.Next, an oxide film is deposited by chemical vapor deposition on the front surface of the substrate including the structure including the transistor, using the interlayer insulating layer 230. In this case, the interlayer insulating layer 230 is formed of an insulating layer having excellent reflow in annealing in order to improve flatness. In particular, the interlayer insulating layer 230 includes boron and phosphorus at a predetermined concentration and is insulated. The inside of the layer has the form of a compound such as B 2 O 3 , P 2 O 5 . Since the deposited interlayer insulating layer 230 has a large step because the gate 21 protrudes over the surface of the substrate 20, the step of the interlayer insulating layer 230 covering the gate 21 also has a similar pattern. do.
도 2b를 참조하면, 단차가 큰 층간절연층에 어닐링 등의 열공정을 실시하여 리플로잉(reflowing)시켜 층간절연층(231) 상부 표면의 평탄도를 개선한다. 즉, 상기한 화합물로 도핑되어 유동성이 큰 층간절연층(231)에 열을 가하면 단차가 큰 부위에있던 층간절연층이 단차가 낮은곳으로 흘러서 단차를 감소시키게 된다. 이와 같은 작용을 리플로잉이라 한다.Referring to FIG. 2B, the flatness of the upper surface of the interlayer insulating layer 231 is improved by reflowing by performing a thermal process such as annealing on the interlayer insulating layer having a large step. That is, when the layer is doped with the above-mentioned compound and heat is applied to the interlaminar insulating layer 231 having high fluidity, the interlayer insulating layer, which was in a large step, flows to a low step to reduce the step. This action is called reflowing.
따라서, 리플로잉된 층간절연층(230)의 표면은 완만한 경사를 갖게 되어 콘택홀 형성용 포토레지스트를 사용하는 사진공정을 용이하게 하고 홀 형상 후의 프로파일 개선에 유용하다.Therefore, the surface of the reflowed interlayer insulating layer 230 has a gentle slope, which facilitates the photolithography process using the photoresist for forming contact holes and is useful for improving the profile after the hole shape.
도 2c를 참조하면, 붕소와 인을 포함하는 산화막으로서 리플로잉된 층간절연층에 대하여 오존-황산 혼합액으로 화학처리(CT)를 실시한다. 화학처리 결과, 층간절연층(232)의 표면에서 소정 깊이까지에 존재하던 도판트들이 오존-황산 혼합액으로 추출되어 도판트의 농도가 감소된다. 이러한 도판트들의 외부 확산정도는 화학처리조건(혼합액 농도, 처리시간 등)에 의하여 결정되며 일반적으로 처리시간과 온도가 크면 확산정도도 증가하게 된다.Referring to FIG. 2C, a chemical treatment (CT) is performed with an ozone-sulfuric acid mixture on an interlayer insulating layer reflowed as an oxide film containing boron and phosphorus. As a result of the chemical treatment, the dopants that existed up to a predetermined depth on the surface of the interlayer insulating layer 232 are extracted with the ozone-sulfuric acid mixture and the concentration of the dopant is reduced. The degree of external diffusion of these dopants is determined by the chemical treatment conditions (mixture concentration, treatment time, etc.). In general, when the treatment time and temperature are large, the degree of diffusion increases.
이와 같이 표면의 도판트 농도가 감소한 부위의 층간절연층(232)은 습식식각시 식각속도가 증가하고 특히 수평방향으로의 식각도 촉진된다.As such, the interlayer insulating layer 232 of the portion where the dopant concentration of the surface is reduced has an increased etch rate during wet etching, and is particularly promoted in the horizontal direction.
도 2d를 참조하면, 단차가 개선되고 표면의 도핑농도가 감소된 층간절연층(232) 상에 포토레지스트를 도포한 다음 소스/드레인이 형성된 기판 표면의 상부에 대응하는 포토레지스트 부위를 노광 및 현상하여 포토레지스트패턴(24)을 형성한다.Referring to FIG. 2D, the photoresist is applied on the interlayer insulating layer 232 having improved step height and reduced doping concentration of the surface, and then exposing and developing the photoresist portion corresponding to the top of the substrate surface on which the source / drain is formed. The photoresist pattern 24 is formed.
도 2e를 참조하면, 포토레지스트패턴(24)을 식각마스크로 이용하여 층간절연층(233)의 노출 부위를 습식식각 등의 등방성식각으로 소정 깊이 만큼만 제거한다. 이때, 등방성식각은 BOE계열의 식각용액으로 실시하고, 등방성식각이므로 기판과 수직한 방향 뿐만 아니라 수평한 방향 즉, 측방향으로도 식각이 진행된다. 일반적으로 수평방향 대 수직방향의 식각비는 약 2.5:1에서 약 3:1의 비율을 갖는다. 이와 같은 비율에 따라 콘택홀의 프로파일 내지는 형상이 변화하므로 이러한 비율의 제어가 콘택홀의 특성개선에 필수적이다.Referring to FIG. 2E, the exposed portion of the interlayer insulating layer 233 is removed by a predetermined depth only by a predetermined depth by using the photoresist pattern 24 as an etching mask. At this time, the isotropic etching is performed with an etching solution of the BOE series, and isotropic etching, the etching proceeds not only in a direction perpendicular to the substrate but also in a horizontal direction, that is, in a lateral direction. In general, the horizontal to vertical etch ratio is about 2.5: 1 to about 3: 1. Since the profile or shape of the contact hole changes according to such a ratio, control of this ratio is essential for improving the characteristics of the contact hole.
본 발명의 실시예에서는 층간절연층(233)이 화학처리되어 붕소와 인의 도핑농도가 감소되었으므로 수평방향으로의 식각량이 종래 기술에서 보다 증가한다.In the embodiment of the present invention, since the interlayer insulating layer 233 is chemically treated to reduce the doping concentrations of boron and phosphorus, the etching amount in the horizontal direction is increased than in the related art.
도 2f를 참조하면, 포토레지스트패턴(24)을 잔류시킨채 일차 등방성식각되어 잔류하며 노출된 층간절연층(234)의 표면에 플라즈마등을 사용하는 비등방성식각을 실시하여 기판의 소스/드레인 표면이 노출되도록 한다. 이때, 비등방성식각으로 식각이 이루어지므로 기판의 수직방향으로만 시각이 진행되어 식각 프로파일은 수직이 된다.Referring to FIG. 2F, anisotropic etching using a plasma or the like is performed on the surface of the interlayer insulating layer 234 that remains after being first isotropically etched with the photoresist pattern 24 remaining. To be exposed. At this time, since the etching is performed by anisotropic etching, the viewing progresses only in the vertical direction of the substrate, so that the etching profile becomes vertical.
도 2g를 참조하면, 식각마스크로 사용된 포토레지스트패턴을 산소 애슁등의 방법으로 제거하여 잔류한 층간절연층(234)의 표면을 노출시킨다. 따라서, 콘택홀의 형성이 완료된다.Referring to FIG. 2G, the surface of the remaining interlayer insulating layer 234 is exposed by removing a photoresist pattern used as an etching mask by a method such as oxygen ashing. Thus, formation of the contact hole is completed.
그러나, 이와 같이 형성된 콘택홀 도는 비어홀(via hole)의 상부 프로파일은 완만해져서 후속 공정에서 증착되는 금속층 등의 단차피복도를 크게 증가시킨다.However, the upper profile of the contact hole or via hole formed as described above becomes smooth, greatly increasing the step coverage of the metal layer or the like deposited in a subsequent process.
도 2h를 참조하면, 노출된 기판 표면, 즉, 소스/드레인과 전기적으로 접촉하도록 콘택홀 내부 표면을 포함하는 층간절연층(234) 상에 소정의 금속층(25)을 스퍼터링 등의 방법으로 증착하여 형성한다. 이때, 증착되는 금속층(25)의 단차피복도는 전술한 바와 같이 크게 개선된다.Referring to FIG. 2H, a predetermined metal layer 25 is deposited on the exposed substrate surface, that is, the interlayer insulating layer 234 including the contact hole inner surface to be in electrical contact with the source / drain by sputtering or the like. Form. At this time, the step coverage of the deposited metal layer 25 is greatly improved as described above.
따라서, 본 발명은 콘택홀의 상부 개구부가 완만한 경사를 가지며 넓어졌으므로 금속배선 스퍼터링증착이 요이하고, 그못층의 단차피복도를 크게 개선하며, 금속배선 형성 후의 층간평탄도를 개선하며, 공정불량을 방지하므로 전체적인 제품수율을 향상시키는 장점이 있다.Therefore, in the present invention, since the upper opening of the contact hole has a wider slope and wider, metal wiring sputtering deposition is required, the step coverage of the nail layer is greatly improved, the interlayer flatness after the metal wiring is formed, and the process defect is prevented. Therefore, there is an advantage to improve the overall product yield.
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