KR20010077228A - Etching solution for Molybdenum-Aluminum alloy-Molybdenum metal layer - Google Patents

Etching solution for Molybdenum-Aluminum alloy-Molybdenum metal layer Download PDF

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KR20010077228A
KR20010077228A KR1020000004889A KR20000004889A KR20010077228A KR 20010077228 A KR20010077228 A KR 20010077228A KR 1020000004889 A KR1020000004889 A KR 1020000004889A KR 20000004889 A KR20000004889 A KR 20000004889A KR 20010077228 A KR20010077228 A KR 20010077228A
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etching
layer
etching solution
water
molybdenum
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송형수
김기섭
박민춘
이요한
김성수
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한의섭
동우 화인켐 주식회사
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    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/10Etching compositions
    • C23F1/14Aqueous compositions
    • C23F1/16Acidic compositions
    • C23F1/20Acidic compositions for etching aluminium or alloys thereof
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23FNON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
    • C23F1/00Etching metallic material by chemical means
    • C23F1/10Etching compositions
    • C23F1/14Aqueous compositions
    • C23F1/16Acidic compositions
    • C23F1/30Acidic compositions for etching other metallic material
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • H01L21/3213Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • G02F1/13629Multilayer wirings
    • GPHYSICS
    • G02OPTICS
    • G02FOPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362Active matrix addressed cells
    • G02F1/136286Wiring, e.g. gate line, drain line
    • G02F1/136295Materials; Compositions; Manufacture processes

Abstract

PURPOSE: An etchant for etching a tri-layered metallic film of Mo/Al-Nd/Mo is provided, which can etch the tri-layered metallic film of Mo/Al-Nd/Mo without undercut phenomenon of a bottom Mo layer while forming a metal line of a TFT-LCD. CONSTITUTION: A tri-layered metallic film of Mo/Al-Nd/Mo is used as a source/drain array metal line. And the etchant includes H3PO4 of 68-74 wt%, HNO3 of 2-4 wt%, CH3COOH of 5-15wt% and water. And the etchant also includes an additive of 0.01-0.l05 wt% of the whole composition. The etchant also includes H3PO4 of 70-74 wt%, HNO3 of 2-4 wt%, CH3COOH of 8-15wt%, water and an additive of 0.01-0.03 wt%. The water is an ultra pure water having a resistance above 18M ohm.

Description

몰리브덴-알루미늄합금-몰리브덴 삼중층 금속막용 에칭 용액 {Etching solution for Molybdenum-Aluminum alloy-Molybdenum metal layer}Etching solution for molybdenum-aluminum alloy-molybdenum metal layer

본 발명은 반도체장치에서 다층 구조의 금속막의 습식 에칭에 사용되는 에칭 용액에 관한 것이다. 더욱 특별하게는, 본 발명은 TFT-LCD의 소스/드레인 어레이 형성 공정에서 Mo/Al-Nd/Mo의 삼중층 금속막을 하부 Mo층의 언더컷(undercut) 없이 에칭할 수 있는 에칭 용액에 관한 것으로, 상기 에칭 용액은 특정 비율의 인산, 질산, 아세트산, 첨가제 및 물의 혼합 용액이다.The present invention relates to an etching solution used for the wet etching of a metal film of a multilayer structure in a semiconductor device. More particularly, the present invention relates to an etching solution capable of etching a triple layer metal film of Mo / Al-Nd / Mo without undercut of a lower Mo layer in a source / drain array forming process of a TFT-LCD. The etching solution is a mixed solution of phosphoric acid, nitric acid, acetic acid, additives and water in a specific ratio.

반도체 장치에서, 기판 위에 금속 배선을 형성하는 과정은, 보통 박막증착-사진 (레지스트 도포, 정렬, 노광 및 현상)-에칭의 단위 공정 단계로 이루어지고, 개개의 단위 공정 전후에 결과 및 이상 여부를 확인하기 위한 검사와 청정도를 유지하기 위한 세정을 포함한다. 에칭 공정은, 기판이나 웨이퍼 위의 박막 위에 레지스트 도포한 후, 노광 및 현상 단계 등을 거쳐 패턴을 형성시킨 후, 필요한 부분만 남기고 필요없는 부분의 박막을 화학적 또는 물리적 반응으로 제거하는 공정을 의미하며, 일반적으로 플라즈마 등을 이용한 건식 에칭 공정 또는 에칭 용액을 사용하는 습식공정이 사용된다.In a semiconductor device, the process of forming metal wiring on a substrate is usually a unit process step of thin film deposition-photolithography (resist application, alignment, exposure and development)-etching, and the results and abnormalities before and after each unit process are examined. Inspection to confirm and cleaning to maintain cleanliness. The etching process refers to a process of forming a pattern by applying a resist onto a thin film on a substrate or a wafer, and then exposing and developing a pattern, and then removing the unnecessary thin film by chemical or physical reaction, leaving only necessary portions. In general, a dry etching process using plasma or the like or a wet process using an etching solution is used.

공정 가스 플라즈마를 이용하는 건식 공정은, 습식 공정에 비해 에칭 제어력이 우수하고, 종점 검출이 용이하며, 프로파일의 조절이 가능하며, 그리고 공정 폐액이 적다는 장점을 가지고 있어, 최근 들어 이에 대해 많이 연구되고 있으나, 대량 처리가 어렵고 에칭 도중 공정가스에 의한 오염과 손상이 발생한다. 반면, 습식 공정은 건식 공정에 비해 선택성이 높고, 대량 처리가 가능하므로 생산성이 높고, 장치 등의 비용이 매우 저렴하므로, 경제적인 관점에서 이의 사용이 많이 요구되고 있다.The dry process using the process gas plasma has the advantages of better etching control, easier endpoint detection, adjustable profile, and less process waste compared to the wet process. However, bulk processing is difficult and contamination and damage by process gas occur during etching. On the other hand, the wet process has a higher selectivity than the dry process, and can be processed in large quantities, thereby increasing the productivity, and the cost of the device is very low.

반도체 장치의 금속 배선 물질로서 여러 가지 금속 또는 이의 합금이 사용되고 있으며, TFT-LCD의 게이트 및 소스/드레인 배선용 금속막으로는 전기저항이 작은 Al 금속을 일반적으로 사용한다. 그러나, 순수한 Al 은 화학물질에 대한 내성이 약하고 후속 공정에서 배선 결함 문제를 야기할 수 있으므로 최근에는 Al 합금 형태로 사용되거나, Al 또는 Al 합금층 위에 또다른 금속층을 가지는 다층 (multi layer)의 적층 구조가 적용된다.Various metals or alloys thereof are used as the metal wiring material of the semiconductor device, and Al metals having low electrical resistance are generally used as the metal film for gate and source / drain wiring of TFT-LCD. However, pure Al is weakly resistant to chemicals and can cause wiring defects in subsequent processes, so it has recently been used in the form of Al alloys, or multilayers of layers with another metal layer over Al or Al alloy layers. The structure is applied.

TFT-LCD의 게이트 및 소스/드레인 어레이의 형성 시에 필수적으로 사용되는 에칭 공정에서는 단차(Step)의 제어, 즉 적절한 단차 기울기 및 양호한 프로파일의수득이 중요한 공정 관리의 항목으로 중시된다.In the etching process, which is essentially used in the formation of the gate and source / drain array of the TFT-LCD, control of steps, that is, obtaining proper step slope and good profile, is an important item of process management.

서로 다른 재질의 이중막을 습식 에칭하는 경우에는, 에칭 속도 및 에칭 메카니즘의 차이로 인해 상부층의 돌출 현상 또는 하부층의 언더컷 현상이 발생한다. 상부층의 돌출 현상은, 추가의 습식 또는 건식 에칭으로 제거해야 하는 문제점을 일으키며, 하부층의 언더컷 현상은, 후속 공정에서 경사면에서 상부층의 단선 또는 상하부 금속의 단락 등의 주요한 불량을 야기한다. 이러한 단점은 이중층 금속막을 습식으로 에칭하는 것을 방해하는 주요한 원인이 되며, 고비용, 저생산성, 손상에 의한 불량률 증대라는 단점에도 불구하고 건식 에칭을 선호하는 근거가 되어 왔다.In the case of wet etching bilayers of different materials, protrusion of the upper layer or undercut of the lower layer may occur due to the difference in etching rate and etching mechanism. The protruding phenomenon of the upper layer causes a problem to be removed by further wet or dry etching, and the undercut phenomenon of the lower layer causes major defects such as disconnection of the upper layer on the inclined surface or short circuit of upper and lower metals in the subsequent process. This drawback is a major obstacle to wet etching the bilayer metal film, and has been the basis for favoring dry etching despite the disadvantages of high cost, low productivity, and increased defect rate due to damage.

그러나, 본 발명자들에 의한 특허출원 제99-41119호에는, 인산, 질산, 아세트산 및 물로 구성된 기존의 Al 에칭 용액에서 이들 산들의 조성비를 특정하게 변화시켜, Al-Nd 하부층 및 Mo 상부층으로 된 Mo/Al-Nd 이중층 금속막을 단일 공정으로 습식 에칭하여도, 우수한 프로파일 및 양호한 단차 기울기를 가지고 층덮임 현상을 주지 않는 우수한 에칭 용액을 제안한 바 있다.However, Patent Application No. 99-41119 by the present inventors discloses that the composition ratio of these acids in the existing Al etching solution composed of phosphoric acid, nitric acid, acetic acid and water is changed specifically, so that the Mo-based Al-Nd lower layer and the Mo upper layer are formed. Even if the wet etching of the / Al-Nd bilayer metal film is performed in a single process, an excellent etching solution with excellent profile and good step slope is proposed.

기존의 단일막 습식 에칭에서의 기술적인 문제로, 가공 재료에 대응한 에칭 용액 및 그 조성을 최적화하는 것, 가공 재료 및 레지스트와의 접착성을 높이는 것, 균일성이 좋은 에칭 용액의 혼합 및 온도 제어 등이 있고 이들에 대해서는 많은 연구가 진행되고 있다. 그러나, 이중층 금속막의 습식 에칭에서는, 에칭 용액의 조성비를 단순히 변화시킴으로써는 에칭 공정을 단일 단계로 행하는 것은 상식적으로 불가능한 것으로 받아들여지고 있고, 또 이를 구현한 예도 거의 보고된 바가 없었기에, 조성비의 변화에 의한 이중층 금속막의 단일 단계 습식 에칭의 달성은 경제적인 관점으로도 매우 놀라운 것이다.The technical problem in conventional single film wet etching is to optimize the etching solution and its composition corresponding to the processing material, to improve the adhesion with the processing material and the resist, to mix the etching solution with good uniformity and to control the temperature There are many studies on these. However, in the wet etching of the double layer metal film, it is generally accepted that it is not possible to perform the etching process in a single step by simply changing the composition ratio of the etching solution. The achievement of a single step wet etching of a double layer metal film by means of economics is also surprising.

그러나, 삼중층 이상의 다중층 금속막에 대해서는, 아직까지 이와 같이 효과적인 에칭 공정/용액이 개발된 경우는 거의 없으므로, 각 층을 별도의 습식 또는 건식 공정, 또는 이들의 조합에 의해 에칭하고 있다. 공정 단계 및 비용을 감소시키기 위하여, 두 개의 층을 동시에 습식 에칭하는 경우에, 상부층 돌출(Overhang)만이 발생한다면 추가의 공정으로 상부층의 돌출된 부분을 에칭하는 것이 가능하다. 그러나, 하부층 언더컷이 발생한다면, 후속 공정에서 상부층이 경사면에서 단선되든가 또는 상하부 금속이 단락이 일어날 확률이 커지며 반도체 장치의 주요한 불량을 야기한다.However, for such multilayer metal films of three or more layers, such an effective etching process / solution has not been developed so far, so that each layer is etched by a separate wet or dry process or a combination thereof. In order to reduce process steps and costs, in the case of wet etching two layers simultaneously, it is possible to etch the protruding portions of the top layer with an additional process if only an upper layer overhang occurs. However, if an underlayer undercut occurs, there is a high probability that the upper layer will be disconnected from the inclined surface or a short circuit will occur between the upper and lower metals in a subsequent process, leading to a major failure of the semiconductor device.

이러한 이유로, 공정의 번거러움 및 비용에도 불구하고, 삼중층 금속막을 에칭하는 경우에는, 각 층별로 별도의 습식 및/또는 건식 에칭을 조합하여 사용하고 있는 것이다.For this reason, despite the inconvenience and cost of the process, when etching the triple layer metal film, a separate wet and / or dry etching is used for each layer.

이러한 상황에서, 본 발명자들은 Mo/Al-Nd/Mo 삼중층 금속막의 에칭 시에 하부층에서 언더컷 현상을 나타내지 않고 하나 이상의 층을 동시에 에칭할 수 있는 에칭 용액을 개발하고자 연구하였으며, 그 결과, 인산, 질산, 아세트산 및 물로 된 기존의 Al 박막 에칭 용액에서 이들 산들의 조성비를 특정하게 변화시킬 경우에 하부 Mo층의 언더컷 현상의 발생이 없이, Mo/Al-Nd/Mo 금속막을 에칭할 수 있음을 발견하였다. 아울러, 상부 Mo층 또는 중간 Al-Nd층의 돌출 현상이 발생하더라도, 하부 Mo층의 언더컷이 없기 때문에, 통상적인 추가의 건식 에칭에 의해 상부 Mo층의 돌출 부분만을 에칭할 수 있어, 경제적이고 간편하게 양호한 단차 제어, 층덮임 제어 및 우수한 프로파일을 제공할 수 있음을 또한 발견하였다.In this situation, the present inventors have studied to develop an etching solution capable of simultaneously etching one or more layers without exhibiting an undercut phenomenon in the underlying layer during the etching of the Mo / Al-Nd / Mo triple layer metal film. In the existing Al thin film etching solution of nitric acid, acetic acid and water, it was found that the specific Mo / Al-Nd / Mo metal film can be etched without the occurrence of undercut of the lower Mo layer if the composition ratio of these acids was changed. It was. In addition, even if protrusion of the upper Mo layer or the middle Al-Nd layer occurs, since there is no undercut of the lower Mo layer, only the protruding portion of the upper Mo layer can be etched by the usual additional dry etching, which is economical and convenient. It has also been found that it can provide good step control, layering control and good profile.

도 1은 기존의 Al 에칭 용액으로 Mo/Al-Nd/Mo 삼중층을 습식 에칭한 후에 하부 Mo층의 언더컷 현상이 나타난 프로파일을 보여주는 SEM 사진이며,FIG. 1 is a SEM photograph showing a profile in which an undercut phenomenon of a lower Mo layer occurs after wet etching an Mo / Al-Nd / Mo triple layer with a conventional Al etching solution.

도 2는 본 발명에 따른 Al 에칭 용액으로 Mo/Al-Nd/Mo 삼중층을 습식 에칭한 후에 언더컷 현상이 나타나지 않은 프로파일을 보여주는 SEM 사진이다.2 is a SEM photograph showing a profile in which the undercut phenomenon does not appear after wet etching an Mo / Al-Nd / Mo triple layer with an Al etching solution according to the present invention.

따라서, 본 발명의 목적은 반도체장치, 특히 TFT-LCD 의 배선 형성시 소스/드레인 (Source/Drain) 재질인 Mo/Al-Nd/Mo 삼중층 금속막을 하부 Mo 층의 언더컷 현상 없이 에칭할 수 있는 에칭 용액을 제공함에 있다.Accordingly, it is an object of the present invention to etch a Mo / Al-Nd / Mo triple layer metal film, which is a source / drain material, during the formation of a wiring of a semiconductor device, particularly a TFT-LCD, without undercutting of the lower Mo layer. In providing an etching solution.

본 발명에 따른 에칭 용액은 68 ~ 74 중량%의 인산 (H3PO4), 2 ~ 4 중량%의 질산 (HNO3), 5 ~ 15중량%의 아세트산 (CH3COOH) 및 100 중량%가 되게 하는 양의 물을 포함하고 필요에 따라 조성물 전체 중량을 기준으로 0.01 ~ 0.05 중량%의 첨가제를 포함한다. 본 발명에 따른 에칭 용액은, 바람직하게는 70 ~ 74 중량%의 인산, 2~4 중량%의 질산, 8 ~ 15 중량%의 아세트산 및 100 중량%가 되게 하는 양의 물 및 필요에 따라 0.01~0.03 중량%의 첨가제를 포함한다.The etching solution according to the invention is 68 to 74% by weight of phosphoric acid (H 3 PO 4 ), 2 to 4% by weight of nitric acid (HNO 3 ), 5 to 15% by weight of acetic acid (CH 3 COOH) and 100% by weight And an amount of water of 0.01 to 0.05% by weight based on the total weight of the composition, if necessary. The etching solution according to the invention is preferably from 70 to 74% by weight of phosphoric acid, from 2 to 4% by weight of nitric acid, from 8 to 15% by weight of acetic acid and from water to an amount of from 100% to 0.01% by weight if necessary. 0.03% by weight of additives.

이하에, 본 발명을 더욱 상세히 설명한다.In the following, the present invention is described in more detail.

반도체 장치에서 배선을 형성하는 금속의 종류 및 기판의 종류에 따라 특유의 에칭 용액이 개발되어 사용되고 있다. TFT-LCD 장치의 채널부의 기본 구조는 게이트, Si 절연층, 소스/드레인, 보호층 (passivation) 및 ITO 층으로 구성되며, 소스/드레인 배선 형성용 금속으로서 주로 Al 또는 Al합금을 사용한다.In a semiconductor device, a unique etching solution is developed and used depending on the type of metal and the type of substrate forming the wiring. The basic structure of the channel portion of the TFT-LCD device is composed of a gate, a Si insulating layer, a source / drain, a passivation layer, and an ITO layer, and mainly uses Al or Al alloy as the metal for forming the source / drain wiring.

Al 또는 Al 합금에 대한 건식 에칭 및 습식 에칭법 및 여기에 사용되는 공정가스 및 에칭 용액에 대해서는 주지되어 있다. 건식 에칭에서는 CCl4, Cl2, BCl3, SiCl4, HCl, CCl2F2, CCl3F 등의 Cl 계 공정가스 또는 SF6, CF4, CHF3등의 F계 공정가스에 의한 이용한 플라즈마 에칭으로 행해지며, 습식 에칭은 인산, 질산, 아세트산 및 물, 예를 들면 72% 인산, 2% 질산, 10% 아세트산 및 16%의 물로 구성된 에칭 용액을 이용하여 30~45 ℃에서 행해진다.Dry etching and wet etching methods for Al or Al alloys and the process gases and etching solutions used therein are well known. In dry etching, plasma is used by Cl process gas such as CCl 4 , Cl 2 , BCl 3 , SiCl 4 , HCl, CCl 2 F 2 , CCl 3 F or F process gas such as SF 6 , CF 4 , CHF 3 . The etching is carried out and the wet etching is carried out at 30 to 45 DEG C using an etching solution composed of phosphoric acid, nitric acid, acetic acid and water, for example 72% phosphoric acid, 2% nitric acid, 10% acetic acid and 16% water.

질산은 Al 과 반응하여 알루미늄 옥시드를 형성하고, 인산과 물은 이 물질을 분해시킨다. 이때, 물은 에칭 용액을 희석하는 역할도 한다. 아세트산은 반응 속도 등을 조절하기 위해 완충제로서 사용되는데, 질산의 분해속도를 조절하며, 일반적으로 분해속도를 감소시킨다.Nitric acid reacts with Al to form aluminum oxide, and phosphoric acid and water decompose the material. At this time, the water also serves to dilute the etching solution. Acetic acid is used as a buffer to control the reaction rate and the like, which controls the rate of decomposition of nitric acid and generally reduces the rate of degradation.

다중층 금속막에서, 여러 층을 동시에 에칭하기 위해서는 하기 수학식에 따라 계산되는 에칭 속도 (E/R, Etching rate)가 비슷하게 되도록 에칭 용액의 조성비를 조절해야 한다.In the multilayer metal film, in order to etch several layers at the same time, the composition ratio of the etching solution must be adjusted so that the etching rate (E / R, Etching rate) calculated according to the following equation is similar.

에칭속도(E/R, Å/min) = [(에칭전 두께) - (에칭후 두께)]/(에칭 시간)Etch Rate (E / R, Å / min) = [(Thickness before etching)-(Thickness after etching)] / (Etching time)

본 출원인에 의한 특허출원 제1999-41119호에 의하면, Mo 층의 에칭속도는 Al-Nd 합금층의 에칭 속도보다 느리므로, Mo층의 에칭 속도에 직접적인 영향을 주는 질산의 함량을 증가시키고, Al-Nd 합금층의 에칭 속도를 감소시키기 위해 인산의 함량은 감소시키고 아세트산의 함량은 증가된다. 이러한 방식으로, 에칭 용액의 각성분비를 조절하였고, 인산 (H3PO4), 질산(HNO3) 및 아세트산의 중량비가 (40~ 70) : (5 ~ 20) : (10 ~ 20) 일 경우, 바람직하게는 상기 중량비가 (50~60) : (5~10) : (10 ~ 15)일 경우, 상부 Mo 층과 하부 Al-Nd 층의 에칭 속도의 차이가 최소화되었으며, 그 결과 상부 Mo 층이 하부 Al-Nd 합금층의 바깥 부위로 돌출되는 현상을 해결할 수 있었다. 물은 상기 혼합물을 100 중량%가 되는 양으로 사용하며, 일반적으로 0~30 중량% 이었다.According to the patent application 1999-41119 by the applicant, since the etching rate of the Mo layer is slower than that of the Al-Nd alloy layer, the content of nitric acid which directly affects the etching rate of the Mo layer is increased, and In order to reduce the etching rate of the -Nd alloy layer, the content of phosphoric acid is decreased and the content of acetic acid is increased. In this way, the angular component ratio of the etching solution was adjusted, and the weight ratio of phosphoric acid (H 3 PO 4 ), nitric acid (HNO 3 ) and acetic acid was (40 to 70): (5 to 20): (10 to 20). Preferably, when the weight ratio is (50 to 60): (5 to 10): (10 to 15), the difference in etching rate between the upper Mo layer and the lower Al-Nd layer is minimized, and as a result, the upper Mo layer The phenomenon of protruding to the outer portion of the lower Al-Nd alloy layer was solved. Water is used in an amount of up to 100% by weight of the mixture, generally 0-30% by weight.

이와는 달리, Mo(상부층)/Al-Nd(중간층)/Mo(하부층) 삼충층에 관한 본 발명에서는 질산의 함량이 2~4 중량%로 감소된다. 단순히 설명을 위한 것이지만, 이러한 질산 함량의 감소는, 본 발명에서 상부층과 하부층이 동일한 Mo층이므로, 이들 사이의 에칭 속도를 균형있게 조절하는데 도움을 주기 때문인 것으로 보인다.In contrast, in the present invention with respect to Mo (upper layer) / Al-Nd (middle layer) / Mo (lower layer) triplet layer, the content of nitric acid is reduced to 2 to 4% by weight. For illustrative purposes only, this reduction in nitric acid content appears to be because, in the present invention, the upper and lower layers are the same Mo layer, which helps to balance the etching rate between them.

한편, Mo/Al-Nd 이중층의 에칭 용액에 비하여, 본 발명의 삼중층 금속막용 에칭 용액에서, Al-Nd 합금층의 에칭 속도를 상대적으로 감소시키는 인산의 함량은 증가된 반면, 전체 에칭 속도를 조절하는 아세트산의 함량은 증가된 것이 좋은 결과를 주었다.On the other hand, compared with the etching solution of the Mo / Al-Nd bilayer, in the etching solution for the triple layer metal film of the present invention, the content of phosphoric acid which relatively decreases the etching rate of the Al-Nd alloy layer is increased while increasing the overall etching rate. Increased acetic acid content gave good results.

본 발명에서 사용되는 인산, 질산, 아세트산, 및 물은 반도체 공정용으로 사용가능한 순도의 것이 바람직하며, 시판되는 것을 사용하거나, 공업용 등급을 당업계에 통상적으로 공지된 방법에 따라 정제하여 사용할 수 있다. 반도체 공정용 물은 일반적으로 초순수 (ultra pure water)이며, 바람직하게는 18 MΩ 이상의 물을 사용한다.Phosphoric acid, nitric acid, acetic acid, and water used in the present invention are preferably those of the purity that can be used for the semiconductor process, and may be commercially available or may be purified using industrial grades according to methods commonly known in the art. . Water for semiconductor processing is generally ultra pure water, preferably at least 18 MΩ water is used.

본 발명에서 사용되는 첨가제는 에칭 용액에 통상적으로 사용되는 성분으로서 특별히 한정되는 것은 아니며, 일반적으로 계면활성제, 금속이온 봉쇄제 등을언급할 수 있다. 계면활성제는 에칭 용액의 점도를 저하시켜 에칭 균일성(unformity)을 향상시키기 위해 첨가되며, 에칭 용액에 견딜 수 있고 상용성이 있는 종류라면 임의의 음이온성, 양이온성, 양쪽이온성 또는 비이온성 계면활성제를, 바람직하게는 불소계 계면활성제를 사용한다. 또한, 에칭 용액에 통상적으로 들어가는 다른 첨가제를 첨가할 수 있다.The additive used in the present invention is not particularly limited as a component commonly used in etching solutions, and generally, a surfactant, a metal ion blocking agent, and the like can be mentioned. Surfactants are added to reduce the viscosity of the etching solution to improve the etching uniformity, and any anionic, cationic, zwitterionic or nonionic interface can be used if the type is compatible and compatible with the etching solution. The activator is preferably a fluorine-based surfactant. It is also possible to add other additives that normally enter the etching solution.

본 발명의 에칭 용액을 사용하여 금속막을 에칭하는 공정은 당업계 주지의 방법에 따라 행해질 수 있으며, 침지, 흘리기 등을 예시할 수 있다. 에칭 공정시의 온도는 일반적으로 30~45℃ 이며, 적정 공정 온도는 다른 공정 조건 및 요인에 의해 필요에 따라 정해진다.The step of etching the metal film using the etching solution of the present invention can be performed according to a method well known in the art, and can be immersed, shedding and the like. The temperature at the time of an etching process is generally 30-45 degreeC, and an appropriate process temperature is determined as needed by other process conditions and factors.

본 발명의 에칭 용액을 사용하여 삼중층 박막을 에칭하는 시간은, 온도 및 박막의 두께 등에 따라 변할 수 있으나 일반적으로 수초 내지 수분이다.The time for etching the triple layer thin film using the etching solution of the present invention may vary depending on the temperature and the thickness of the thin film, but is generally several seconds to several minutes.

상술한 에칭 온도 및 에칭 시간은 당업계 통상의 지식을 가진 자에 의해 용이하게 결정될 수 있으며, 본 발명을 한정하지는 않는다.The above-described etching temperature and etching time can be easily determined by those skilled in the art, and do not limit the present invention.

종래의 Al 또는 Al 합금용 에칭 용액을 사용하여 Mo/Al-Nd/Mo 삼중층 금속막을 에칭하면, 하부 Mo 층이 중간 Al-Nd 층 안으로 파고 들어가 심한 언더컷 형태를 나타내는데, 이것은 다음 공정에서 단차 덮임 불량 및 S/D 패턴의 접착력 약화로 인한 불량이 발생한다.Etching the Mo / Al-Nd / Mo triple layer metal film using a conventional etching solution for Al or Al alloys, the lower Mo layer penetrates into the intermediate Al-Nd layer and exhibits a severe undercut shape, which is covered by the next step. Defects occur due to defects and weak adhesion of the S / D pattern.

그러나, 본 발명에 따른 특정 조성 및 조성비의 에칭 용액을 사용하여 Mo/Al-Nd/Mo 삼중층 금속막을 에칭하면, 이러한 하부층의 언더컷 현상이 억제되고, 추후의 공정에서 층덮임 현상이 감소 또는 제거되므로 불량률이 감소된다.However, when the Mo / Al-Nd / Mo triple layer metal film is etched using an etching solution of a specific composition and composition ratio according to the present invention, the undercut phenomenon of this lower layer is suppressed, and the layer covering phenomenon is reduced or eliminated in a later process. Therefore, the defective rate is reduced.

따라서, 본 발명의 이점중의 하나는, 하부 Mo 층의 언더컷 현상이 억제되므로, 다음 공정에서 단차 덮임 불량 및 S/D 패턴의 접착력 약화로 인한 불량이 억제되므로, 비용 및 생산성의 관점에서도 매우 유리하다는 것이다.Therefore, one of the advantages of the present invention is that the undercut phenomenon of the lower Mo layer is suppressed, and therefore, the defect due to the step covering failure and the weakening of the adhesion of the S / D pattern is suppressed in the next step, which is very advantageous in terms of cost and productivity. It is.

본 발명의 또다른 이점은, 기존의 Al 에칭 용액과 동일한 구성성분, 즉 질산, 인산, 아세트산 및 첨가제를 사용하며, 단지 그 조성비만이 특정하게 한정된다는 점이다. 따라서, 에칭 용액의 제조시에 원료의 구입 및 정제 등이 비교적 용이하며, 취급상의 주의점 등에 대해서도 통상 주지된 바와 동일하다는 것이다.Another advantage of the present invention is that it uses the same constituents as the existing Al etching solution, i.e. nitric acid, phosphoric acid, acetic acid and additives, only their composition ratio being specifically limited. Therefore, it is relatively easy to purchase and purify the raw materials at the time of preparation of the etching solution, and the same as those commonly known for handling precautions.

본 발명의 또다른 이점은 대량생산이 가능한 습식 에칭 처리 단계를 도입하고 반도체 장치의 열화를 줄 수 있는 건식 에칭 처리 단계의 사용을 최소화함으로써, 오염과 손상에 의한 반도체 장치의 열화가 적고 생산성 면에서 매우 유리하다는 것이다.Another advantage of the present invention is the introduction of the wet etching process step that can be mass-produced and minimizing the use of the dry etching step that can cause deterioration of the semiconductor device, thereby reducing the deterioration of the semiconductor device due to contamination and damage and in terms of productivity It is very advantageous.

본 발명은 하기 실시예에 의해 더욱 상세하게 설명되나, 이들로 본 발명이 한정되지는 아니한다.The present invention is explained in more detail by the following examples, but the present invention is not limited thereto.

실시예에서 에칭된 금속막의 프로파일은 단면 SEM (Hitachi사 제품, 모델명 S-4200)을 사용하여 검사하였으며, 이의 결과는 다음과 같이 표시한다.The profile of the etched metal film in the Example was inspected using a cross-sectional SEM (Model S-4200, manufactured by Hitachi), and the results thereof are expressed as follows.

◎ : 양호, 하부 Mo층이 중간 Al-Nd 층의 안으로 들어가지 않은 프로파일을 보여줌.:: Good, showing the profile that the lower Mo layer did not enter into the middle Al-Nd layer.

○ : 보통, 하부 Mo층이 중간 Al-Nd 층과 거의 같은 정도로 에칭된 프로파일을 보여줌.○: Normally, the lower Mo layer shows a profile etched to about the same degree as the middle Al-Nd layer.

× : 불량, 하부 Mo층이 과도하게 에칭되어 중간 Al-Nd 층의 안으로 들어간프로파일 (언더컷 현상)을 보여줌.X: Poor, the lower Mo layer was excessively etched to show a profile (undercut phenomenon) that went into the middle Al-Nd layer.

실시예 1Example 1

반도체 공정용 등급인 인산, 질산, 아세트산 및 첨가제 (불소계 계면활성제 등)를 70/2/15의 중량비로 혼합하고 전체 100 중량%가 되는 양으로 물로 희석하여 에칭 용액을 제조한다. 에칭 시험은, 통상적인 방법에 따라 유리 기판상에 박막 스퍼터링법을 사용하여 Mo/Al-Nd/Mo 삼중층 및 포토 레지스트로 배선 패턴을 형성시킨 시험편에 상기 에칭 용액을 스프레이하여 에칭 처리한다. 에칭속도는 40℃에서 1500~2200 Å으로 우수한 편이었다.Phosphoric acid, nitric acid, acetic acid and additives (fluorine-based surfactants, etc.), which are grades for semiconductor processing, are mixed in a weight ratio of 70/2/15 and diluted with water in an amount of up to 100% by weight in total to prepare an etching solution. In the etching test, the etching solution is sprayed onto a test piece on which a wiring pattern is formed of a Mo / Al-Nd / Mo triple layer and a photoresist using a thin film sputtering method on a glass substrate according to a conventional method. The etching rate was excellent at 1500-2200 Pa at 40 degreeC.

단면 SEM (Hitachi사 제품, 모델명 S-4200)을 사용하여 상기 에칭된 시험편의 금속막 프로파일을 검사하였으며, 하부 Mo 층이 중간 Al-Nd 층 안쪽으로 들어간 언더컷 현상이 나타나지 않았다.The metal film profile of the etched test piece was examined using a cross-sectional SEM (Model S-4200, manufactured by Hitachi), and there was no undercut phenomenon in which the lower Mo layer entered the middle Al-Nd layer.

도 3은 실시예 1 에서 수득된 우수한 프로파일을 보여주는 사진이다.3 is a photograph showing a good profile obtained in Example 1.

실시예 2 ~ 5Examples 2-5

인산, 질산, 아세트산 및 첨가제를 표 1에 나타낸 바와 같은 비율로 사용함을 제외하고는 실시예 1과 동일하게 에칭 용액을 제조하고 에칭 시험을 행한다.An etching solution was prepared in the same manner as in Example 1 except that phosphoric acid, nitric acid, acetic acid, and additives were used in the proportions shown in Table 1, and an etching test was performed.

단면 SEM을 사용하여 상기 에칭된 시험편의 금속막 프로파일을 검사하였으며, 하부 Mo 층이 중간 Al-Nd 층 안쪽으로 들어간 언더컷 현상이 나타나지 않았다.The cross-sectional SEM was used to examine the metal film profile of the etched test specimens, and no undercut phenomenon was observed in which the lower Mo layer was inside the middle Al-Nd layer.

결과는 표 1에 기재한다.The results are shown in Table 1.

비교예 1~3Comparative Examples 1 to 3

표 1에 나타낸 바와 같은 비율로 인산, 질산, 아세트산 및 첨가제를 사용하고 전체100 중량%가 되는 양으로 물로 희석하여 에칭 용액을 제조하고, 실시예 1~5에서와 동일하게 에칭 시험을 행한다.The etching solution was prepared by using phosphoric acid, nitric acid, acetic acid and additives in the ratio as shown in Table 1 and diluting with water in an amount of 100% by weight in total, and the etching test was carried out in the same manner as in Examples 1 to 5.

단면 SEM 을 사용하여 상기 에칭된 시험편의 금속막 프로파일을 검사한다. 하부 Mo층이 중간 Al-Nd 층의 아래로 들어간 현상 (Under-cut 현상)을 보여 주었다. 전체적인 결과는 표 1에 기재한다.A cross-sectional SEM is used to examine the metal film profile of the etched test piece. The lower Mo layer showed under-cut phenomenon under the middle Al-Nd layer. The overall results are shown in Table 1.

실시예 번호Example number 조성 (중량%)*H3PO4/HNO3/CH3CO2H/첨가제Composition (wt%) * H 3 PO 4 / HNO 3 / CH 3 CO 2 H / Additive 결과result 1One 70/2/15/0.0170/2/15 / 0.01 22 71/3/4/0.0271/3/4 / 0.02 33 72/4/8/0.0272/4/8 / 0.02 44 74/2/7/0.0274/2/7 / 0.02 55 68/3/10/0.0268/3/10 / 0.02 1 (비교)1 (comparative) 63/8/10/0.0263/8/10 / 0.02 xx 2 (비교)2 (comparative) 65/7/9/0.0265/7/9 / 0.02 xx 3 (비교)3 (comparative) 67/3/10/0.0267/3/10 / 0.02 xx * 100 중량%가 되게 물로 희석함* Diluted with water to 100% by weight

상기 표 1에서 알 수 있는 바처럼, 본 발명에 따른 에칭 용액으로 Mo/Al-Nd/Mo 삼중층을 에칭할 경우 하부 Mo층의 언더컷 현상이 나타나지 않았다. 따라서, 통상적인 건식 에칭 공정에 의해 상부 Mo층의 돌출 부분을 에칭한 경우에 불량률이 적게 발생한다.As can be seen in Table 1, when the Mo / Al-Nd / Mo triple layer is etched with the etching solution according to the present invention, there was no undercut phenomenon of the lower Mo layer. Therefore, less defect rate occurs when the protruding portion of the upper Mo layer is etched by a conventional dry etching process.

반면, 비교예의 에칭 용액으로 Mo/Al-Nd/Mo 삼중층을 에칭할 경우 하부 Mo층의 언더컷 현상이 나타났으며, 통상적인 건식 에칭 공정에 의해서는 상부 Mo층의 돌출 부분을 에칭할 경우, 하부 Mo층의 언더컷 현상으로 인한 결함으로 인해 불량이 많이 발생한다.On the other hand, when the Mo / Al-Nd / Mo triple layer was etched with the etching solution of the comparative example, an undercut phenomenon of the lower Mo layer appeared, and when etching the protruding portion of the upper Mo layer by a conventional dry etching process, Many defects occur due to defects caused by undercut of the lower Mo layer.

또한, 실시예 1~5의 에칭 용액을 사용하여 에칭한 경우, 기존의 습식-건식 2단계 공정에 의해 에칭된 배선에 비해, 에칭된 배선 패턴의 균일성이 우수할 뿐만아니라 이물, 전여물, 긁힘(scratch), 라인 연결 (line short, bridge), 단선 (line open), 금속부식 (metal corrosion), 금속변색 (metal discolor), 오정렬(misalign)의 품질 요인을 만족하였다.In addition, when etching using the etching solution of Examples 1 to 5, compared to the wiring etched by the conventional wet-dry two-step process, not only the uniformity of the etched wiring pattern is excellent, but also foreign materials, deposits, Quality factors such as scratch, line short, bridge, line open, metal corrosion, metal discolor, and misalignment were satisfied.

본 발명의 에칭 용액을 이용하여 Mo/Al-Nd/Mo 삼중층을 하부 Mo 층의 언더컷 현상의 발생없이 에칭할 수 있어 양호한 테이퍼 프로파일을 가지므로 단차 덮임이 개선되어 LSD 제조 공정에 적용 가능하다.By using the etching solution of the present invention, the Mo / Al-Nd / Mo triple layer can be etched without occurrence of undercut of the lower Mo layer, and thus has a good taper profile, so that step coverage is improved and applicable to the LSD manufacturing process.

Claims (3)

68 ~ 74 중량%의 인산 (H3PO4), 2 ~ 4 중량%의 질산 (HNO3), 5 ~ 15 중량%의 아세트산 및 100 중량%가 되게 하는 양의 물을 포함하고, 필요에 따라 조성물 전체 중량을 기준으로 0.01 ~ 0.05 중량%의 첨가제를 포함함을 특징으로 하는, 반도체 장치에서 Mo/Al-Nd/Mo 삼중층 금속막의 에칭 용액.68 to 74 wt% phosphoric acid (H 3 PO 4), 2 to 4 wt% nitric acid (HNO 3 ), 5 to 15 wt% acetic acid and water to an amount of up to 100 wt% Etching solution of the Mo / Al-Nd / Mo triple layer metal film in a semiconductor device, characterized in that it comprises 0.01 to 0.05% by weight of the additive based on the total weight. 제 1 항에 있어서, 50 ~ 60 중량%의 인산, 5~10 중량%의 질산, 11 ~ 15 중량%의 아세트산을 포함함을 특징으로 하는 에칭 용액.The etching solution of claim 1 comprising 50-60 wt% phosphoric acid, 5-10 wt% nitric acid, 11-15 wt% acetic acid. 제 1 또는 2항에 있어서, 반도체장치가 TFT-LCD이고 Mo/Al-Nd/Mo 삼중층 금속막이 소스/드레인 어레이 배선용으로 사용됨을 특징으로 하는 에칭 용액.The etching solution according to claim 1 or 2, wherein the semiconductor device is a TFT-LCD and a Mo / Al-Nd / Mo triple layer metal film is used for source / drain array wiring.
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US6525447B2 (en) * 2000-01-13 2003-02-25 Murata Manufacturing Co., Ltd. Method for manufacturing a langasite single crystal substrate, a langasite single crystal substrate, and a piezoelectric device
KR100444345B1 (en) * 2002-03-28 2004-08-16 테크노세미켐 주식회사 Etchant for making metal electrodes of TFT in FPD
US6797621B2 (en) * 2000-03-20 2004-09-28 Lg.Philips Lcd Co., Ltd. Etchant composition for molybdenum and method of using same
KR100704531B1 (en) * 2002-04-24 2007-04-10 미쓰비시 가가꾸 가부시키가이샤 Etchant and method of etching
KR20080030817A (en) * 2006-10-02 2008-04-07 동우 화인켐 주식회사 Total etchant composition for metal electrode of thin film transistor liquid crystal display
KR100944300B1 (en) * 2001-10-22 2010-02-24 미츠비시 가스 가가쿠 가부시키가이샤 Etching method for aluminum-molybdenum laminate film
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Publication number Priority date Publication date Assignee Title
US6525447B2 (en) * 2000-01-13 2003-02-25 Murata Manufacturing Co., Ltd. Method for manufacturing a langasite single crystal substrate, a langasite single crystal substrate, and a piezoelectric device
US6797621B2 (en) * 2000-03-20 2004-09-28 Lg.Philips Lcd Co., Ltd. Etchant composition for molybdenum and method of using same
KR100944300B1 (en) * 2001-10-22 2010-02-24 미츠비시 가스 가가쿠 가부시키가이샤 Etching method for aluminum-molybdenum laminate film
KR100444345B1 (en) * 2002-03-28 2004-08-16 테크노세미켐 주식회사 Etchant for making metal electrodes of TFT in FPD
KR100704531B1 (en) * 2002-04-24 2007-04-10 미쓰비시 가가꾸 가부시키가이샤 Etchant and method of etching
KR20080030817A (en) * 2006-10-02 2008-04-07 동우 화인켐 주식회사 Total etchant composition for metal electrode of thin film transistor liquid crystal display
CN111423883A (en) * 2020-03-03 2020-07-17 江苏中德电子材料科技有限公司 Anode etching liquid for active matrix organic light-emitting diode display
CN111423883B (en) * 2020-03-03 2021-11-05 江苏中德电子材料科技有限公司 Anode etching liquid for active matrix organic light-emitting diode display

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