KR20010075916A - Finite impulse response filter using multi phase clock - Google Patents

Abstract

PURPOSE: A finite impulse response filter by using a multiplex phase clock is provided to reduce the managing time by supplying the clock phase input to each flip-flop according to the operation managing time and to realize the finite impulse response filter without increasing an extra memory device. CONSTITUTION: The finite impulse response filter by using the multiplex phase clock includes many flip-flops(FF1-FF9), a few clocks(CLK1-CLK4), the first, second and third adders(11, 12, 15) and the first and second multipliers (13, 14). The first and second flip-flops(FF1, FF2) and the sixth and seventh flip-flops(FF6, FF7) output the input data by synchronizing them to the first clock(CLK1). The first and second adders(11, 12) add the signals, which are output from the first and second flip-flops(FF1, FF2) and the sixth and seventh flip-flops(FF6, FF7). The third and eighth flip-flops(FF3, FF8) output the output of the first and second adders(11, 12) by synchronizing it to the second clock(CLK2). The first and second multipliers(13, 14) multiply the signal, which is output from the flip-flops(FF3, FF8) and the appointed coefficient. The fourth and ninth flip-flops output the output of the first and second multipliers(13, 14) by synchronizing it to the third clock(CLK3). The third adder(15) adds the output signal of the flip-flops(FF4, FF9). The fifth flip-flop(FF5) outputs the output of the third adder(15) by synchronizing it to the fourth clock(CLK4).

Description

Finite impulse response filter using multi-phase clock {FINITE IMPULSE RESPONSE FILTER USING MULTI PHASE CLOCK}

The present invention relates to a finite impulse response filter using a multi-phase clock to reduce the overall delay time of a filter implemented using the pipeline concept. In particular, the present invention relates to a multi-phase clock designed to be implemented without using an additional memory device. A finite impulse response filter.

FIG. 1 is a circuit diagram of a general 4-tap finite impulse filter as an example of a general finite impulse response filter. As shown therein, first and second adders 11 and 12 respectively add two input signals. And first and second multipliers 13 and 14 multiplying a value output from the adders 11 and 12 by a predetermined coefficient, and in the first and second multipliers 13 and 14, respectively. And a third adder 15 for adding and outputting the output value.

FIG. 2 is a circuit diagram of a finite impulse response filter having a conventional pipeline shape. As shown in FIG. 2, first and second flip-flops FF1 and FF2 outputting data in synchronization with a clock CLK. A first adder 11 for adding two signals output from the flip-flops FF1 and FF2, a sixth and seventh flip-flops FF6 and FF7 for outputting a predetermined time delay time respectively; A second adder 12 that adds two signals output from the flip-flop, and a third outputting signal output from the first and second adders 11 and 12 in synchronization with an input clock CLK. First and second multipliers 13 and 14 for multiplying a signal output from an eighth flip-flop FF3 and FF8 by the flip-flop FF3 and FF8, and a first and second multipliers 13 and 14. Fourth and ninth flip-flops FF4 and FF9 for synchronizing the signals output from the double multipliers 13 and 14 with the clock and adding the two signals output from the flip-flops FF4 and FF9.A third adder 15 and a fifth flip-flop FF5 for finally outputting the signal output from the third adder 15 in synchronization with the input clock CLK.

Looking at the conventional technology configured as described above is as follows.

When two input signals are respectively input to the first and second adders 11 and 12 of FIG. 1, the two input signals are added and output to the first and second multipliers 13 and 14, respectively.

Then, the first multiplier 13 multiplies the output of the first adder 11 by a predetermined coefficient to provide it to the third adder 15, and the second multiplier 14 outputs the second adder 12. Is multiplied by another predetermined coefficient and provided to the third adder (15).

Therefore, the third adder 15 adds two signals respectively output from the first and second multipliers 13 and 14 and finally outputs them.

In the case of FIG. 1 operating as described above, a new input cannot be applied until the final output value is output, thus causing a large processing time.

In order to solve the above problems, as shown in FIG. 2, a finite impulse response filter of a pipeline type that inserts a flip-flop, which is a memory element, is output to an output of an individual operation unit.

The two input signals are respectively input to the first and second flip-flops FF1 and FF2 before being transferred to the first adder 11, and the respective input signals are synchronized to the clock CLK to allow the first adder to be input. It is inputted by (11).

Similarly, the signals input to the sixth and seventh flip-flops FF6 and FF7 are respectively input to the second adder 12 in synchronization with the clock CLK.

Then, the first and second adders 11 and 12 add two input signals, respectively, and transfer the input signals to the third and eighth flip-flops FF3 and FF8.

When the signals input to the third flip-flop FF3 and the eighth flip-flop FF8 are transferred to the first and second multipliers 13 and 14 in synchronization with the clock CLK, the first and second The new signals input to the two flip flops FF1 and FF2 and the sixth and seventh flip flops FF6 and FF7 are transferred to the adders 11 and 12 in synchronization with the clock CLK.

Accordingly, the first and second multipliers 13 and 14 multiply and output the input signal by a predetermined coefficient, and the first and second adders 11 and 12 add the newly input signal.

The output values calculated by the first and second multipliers 13 and 14 are transferred to the third adder 15 through the fourth and ninth flip-flops FF4 and FF9, and thus the third adder 15 ) Adds the transmitted value and outputs the finally calculated value through the fifth flip-flop FF5.

In the circuit of FIG. 2 operating in this manner, since the processing time of the multiplier is greater than the processing time of the adder, a value of a period larger than the maximum processing time of the multiplier should be selected for the period of the clock CLK applied to this circuit.

For example, if the maximum processing time of the multiplier is 99.99ns, the clock should be selected with a clock lower than 10MHz.

Therefore, when a 10MHz clock is applied, the total processing time is 300ns.

However, in the prior art as described above, although accurate processing is possible, the processing time takes a lot due to the delay time due to the flip-flop.

Therefore, the present invention for solving the conventional problems as described above finite impulse response filter using a multi-phase clock to provide a phase of the clock input to each flip-flop according to each operation processing time to shorten the overall processing time In providing.

Another object of the present invention is to provide a finite impulse response filter using a multi-phase clock that can be implemented without increasing a separate memory device.

1 is a circuit diagram of a conventional four tap finite impulse response (FIR) filter.

2 is a circuit diagram of a finite impulse response filter in the form of a conventional pipeline.

3 is a circuit diagram of a finite impulse response filter using a multi-phase clock of the present invention.

4 is a clock waveform diagram input to the flip-flop of FIG.

***** Explanation of symbols for the main parts of the drawing *****

11: first adder 12: second adder

13: first multiplier 14: second multiplier

15: third adder FF: flip-flop

In order to achieve the above object, the present invention provides a finite impulse response filter implemented by connecting n adders and m multipliers in a pipeline form, wherein a flip-flop is connected to an output terminal of the n adders and n multipliers, It is characterized in that the phase of the clock (CLK) input to the connected flop flop according to the operation processing time of the adder and the multiplier.

Hereinafter, described in detail by the accompanying drawings as follows.

FIG. 3 is a circuit diagram of a finite impulse response filter using a multi-phase clock of the present invention. As shown in FIG. 3, first and second outputting data is synchronized with a first clock CLK1 having a predetermined value. First and second adders for adding flip-flops FF1, FF2, and sixth and seventh flip-flops FF6, FF7, and signals output from the flip-flops FF1, FF2, FF6, FF7, respectively. 11) 12 and the first and second adders 11 and 12 to the second clock CLK2 whose phase is adjusted in accordance with the calculation processing time of the first and second adders 11 and 12. The third and eighth flip-flops FF3 and FF8 for synchronizing the outputs of the first and second multipliers 13 to multiply the signals output from the flip-flops FF3 and FF8 by a predetermined coefficient. (14) and the first and second multipliers 13 and 14 to the third clock CLK3 whose phase is adjusted in accordance with the operation processing time processed by the first and second multipliers 13 and 14. Fourth and ninth flip-flops (FF4) (FF9) for synchronizing and outputting the The third adder 15, which adds a signal output from the flip-flop FF4, FF9, and the fourth clock CLK4 whose phase is adjusted according to the operation processing time processed by the third adder 15, And a fifth flip-flop FF5 for synchronizing the output of the third adder 15 and finally outputting it.

Referring to the operation and effect of the present invention configured as described in detail as follows.

As shown in FIG. 4A, the first clock CLK1 is input to the first and second flip flops FF1 and FF2 and the sixth and seventh flip flops FF6 and FF7, respectively.

Then, the first and second flip-flops FF1 and FF2 and the sixth and seventh flip-flops FF6 and FF7 synchronize a signal input to the data input terminal with the first clock CLK1 to add a first adder. (11) and the second adder (12), respectively.

Therefore, the first adder 11 and the second adder 12 perform arithmetic processing of adding two input signals.

At this time, the second clock CLK2 is input to the third flip flop FF3 and the eighth flip flop FF8, and the phase of the second clock CLK2 is input. The first and second adders 11 and 12 are set in accordance with the time t_adder1 to perform the addition process.

As a result, the phase of the second clock CLK2 is set to be input after the processing time t_adder1 of the adder.

Accordingly, when the first adder 11 and the second adder 12 perform addition processing and output the third flip-flop FF3 and the eighth flip-flop FF8, the third flip-flop FF3 and the fifth adder 11 are added. The second clock CLK2 is input to the clock input terminal of the eight flip-flops FF8.

The third flip-flop FF3 and the eighth flip-flop FF8 synchronize the outputs of the first and second adders 11 and 12 to the second clock CLK2 so as to synchronize the first and second multipliers 13. In this case, the first and second multipliers 13 and 14 multiply a predetermined coefficient and an input signal to provide the fourth flip-flop FF4 and the ninth flip-flop FF9, respectively. .

At this time, the third clock CLK3 as shown in FIG. 4C is input to the clock input terminals of the fourth flip flop FF4 and the ninth flip flop FF9, and the third clock CLK3 is input. The phase of is set in accordance with the time t_mult when the first and second multipliers 13 and 14 perform the multiplication process.

As a result, the phase of the third clock CLK3 is set to be input after the multiplication process time t_mult of the multiplier.

Therefore, when the first multiplier 13 and the second multiplier 14 multiply and output the fourth flip-flop FF4 and the ninth flip-flop FF9, the fourth flip-flop FF4 and the fourth The third clock CLK3 is input to the clock input terminal of the nine flip flops FF9.

When the fourth flip-flop FF4 and the ninth flip-flop FF9 synchronize the outputs of the first and second multipliers 13 and 14 to the third clock CLK3 and provide them to the third adder 15. The third adder 15 adds signals transmitted through the fourth flip flop FF4 and the ninth flip flop FF9.

When the added value is output, the fourth clock CLK4, as shown in Fig. 4D, is input to the clock input terminal of the fifth flip-flop FF5.

At this time, the phase of the fourth clock CLK4 input is set to be input after the processing time t_adder2 of the third adder 15.

Therefore, the total processing time t_total to be processed is as follows.

t_total = t_adder1 + t_mult + t_adder2

For example, if the maximum processing time of the multiplier is 99.99 ns and the maximum processing time of the adder is 9.99 ns, each clock can be set to 10 MHz, but if the phases are different, the total processing time can be 120 ns.

As described above, the basic configuration is the same as in the prior art, and the phase of each clock inputted by the flip-flop is provided and processed according to the operation processing time of the adder and the multiplier, so that there is no memory element added.

As described in detail above, the present invention connects flip-flops to output terminals of the adder and the multiplier, respectively, and provides a phase of a clock CLK input to the connected flop according to the processing time of the adder and the multiplier. Therefore, the overall processing time can be shortened without increasing the use of the memory device.

Claims (2)

A finite impulse response filter implemented by connecting n adders and m multipliers in a pipeline form, wherein a clock is inputted to an output terminal of the n adders and m multipliers and input to the connected flop flops (CLK). A finite impulse response filter using a multi-phase clock, characterized in that to provide a phase according to the processing time of the adder and multiplier. In the first, second flip-flop and the sixth, seventh flip-flop and the first, second flip-flop and the sixth, seventh flip-flop to output the input data in synchronization with the first clock having a predetermined value By synchronizing the outputs of the first and second adders with the first and second adders that add the output signals, and the second clock CLK2 whose phase is adjusted in accordance with the operation processing time of the first and second adders. First and second multipliers for multiplying the third and eighth flip-flops to be output, the signals output from the third and eighth flip-flops by a predetermined coefficient, and an operation processing time processed by the first and second multipliers. The fourth and ninth flip flops for synchronizing the outputs of the first and second multipliers and the signals output from the fourth and ninth flip flops are added to the third clock CLK3 whose phase is adjusted accordingly. The third adder and outputting of the third adder to the fourth clock CLK4 whose phase is adjusted in accordance with the operation processing time processed by the third adder A finite impulse response filter using a multi-phase clock, characterized in that consisting of a fifth flip-flop to synchronously output the output.