KR20010074393A - Optical interface circuit - Google Patents

Abstract

PURPOSE: An optical interface circuit is provided to stably output a normal pulse wave even though a DC level of Vin is changed by generating the pulse wave of high or low level according to the variation of the binary voltage value of Vin. CONSTITUTION: An A/D converter(31) converts the Vin into the binary data(Dout(N)) and outputs. A delay part(32) delays the data(Dout(N)) during the sampling cycle and outputs the delayed data(Dout(N-1)) to an operator(33). The operator receives the data(Dout(N)) and the delayed data(Dout(N-1)), subtracts the delayed data(Dout(N-1)) value from the data(Dout(N)) value, and outputs the subtraction value(diff) and the comparison result(a,b). An output controller(34) piles up the subtraction value(diff) according to the comparison result(a,b). When the size of the piled subtraction value(diff) reaches to regular value, the output controller generates the high or low pulse wave by changing the level of the Vout.

Description

Optical interface circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an optical interface circuit used in a mouse controller and the like, and more particularly, to generate an internal voltage signal proportional to the amount of light received through a photodiode, and to sample the voltage value of the internal voltage signal at an arbitrary time interval. The present invention relates to an optical interface circuit which converts / inputs into binarized information values and generates pulse waveforms of “high” or “low” levels according to the relative amount of change in the rising or falling of the information values.

For example, a mouse controller typically provides position information (or displacement) of the mouse pointer to the computer side using an optical interface circuit.

That is, the mouse controller emits light from the light emitting diodes (LEDs), and at this time, receives light passing through a slot of a rotating wheel by the movement of the mouse using a photo diode, etc., Generates a current proportional to the amount of light received.

This current is discharged through the load element, so that the information about the positional movement of the mouse is converted into an analog type voltage signal at both ends of the load element.

In general, the analog-type voltage signal generated as described above is converted into a pulse waveform of a digital form by comparing a reference voltage having a fixed voltage value with the magnitude of the voltage and outputting it as a pulse signal having position information of a mouse pointer. do.

1 is a circuit diagram showing the configuration of a conventional optical interface circuit described above.

The conventional optical interface circuit includes a light emitting unit 1 for generating light; A light receiving unit 2 for receiving the light generated by the light emitting unit 1 and generating an internal voltage signal Vin of an analog type proportional to the amount of light received; A pulse converter 3 converts the voltage signal Vin generated by the light receiver 2 into a digital pulse waveform and outputs Vout.

Specifically, as shown in FIG. 1, the light emitting unit 1 has a structure in which a light emitting diode LED and a resistor R1 are connected in series to emit light when a power supply voltage VDD is applied to the light emitting diode LED. Will radiate.

This light is detected by the light receiving unit 2, but in the case of a mouse controller or the like, a rotor (not shown) in which a slot is formed to rotate due to the movement of the mouse is provided on the front of the light receiving unit 2 so that the mouse can be detected. The amount of light received by the light receiving unit 2 is adjusted according to the degree of movement of the light source.

The light receiving unit 2 discharges the photodiode PD that generates the current Iin and the current Iin generated by the photodiode PD to ground according to the amount of light received. And a load element portion 21 for generating Vin).

In this case, the load element 21 may be constituted by a simple passive resistor only. In this case, when a large current is emitted from the photodiode PD, a high voltage corresponding to the N1 node is displayed. Due to the RC value of the path itself, the charge / discharge time of the N1 node voltage becomes long, and thus, the reaction speed and precision of the entire optical interface circuit are deteriorated.

Thus, in general, the load element 21 may have a passive resistance R2 and an active resistance as shown in FIG. 1 so that the resistance value of the entire load element 21 may be relatively low when a high voltage is applied. It consists of a composite structure of (M1, Q1).

Hereinafter, the operating characteristics of the circuit of FIG. 1 will be described with reference to FIG. 2, which shows a graph of voltage Vin of the N1 node according to the current amount Iin generated by the photodiode PD.

The photodiode PD of the light receiver 2 emits a current Iin proportional to the amount of received light to the N1 node.

At this time, when the amount of emitted current Iin is small, the nMOS transistor M1 is not turned on, and all of the current generated by the photodiode PD is discharged only through the resistor R2. It will have a corresponding voltage value.

This is a case where the potential difference across the resistor R2 generated by the current discharged through the resistor R2 is not higher than the threshold voltage Vth of the nMOS transistor M1, that is, the area A in the graph of FIG. 2. do.

When the amount of current generated in the photodiode PD increases and the potential difference across the resistor R2 becomes higher than the threshold voltage Vth of the nMOS transistor M1, the nMOS transistor M1 starts to turn on. Therefore, the total resistance value of the load element unit 21 is relatively lower than the resistance value of the resistor R2.

Therefore, from this point on, the increase in the N1 node voltage Vin with respect to the increase in the emission current Iin slows down, which corresponds to the region B in the graph of FIG.

Accordingly, as the emission current Iin increases, the voltage Vin of the N1 node also increases linearly, and the voltage Vin of the N1 node is about 0.7 V (Q1 turn-on threshold voltage) than the voltage of the N2 node. When the PNP transistor Q1 is turned on, the overall resistance of the load element 21 is relatively lowered once again.

Therefore, from this point on, the increase in the N1 node voltage Vin with respect to the increase in the emission current Iin is further slowed down, which corresponds to region C in the graph of FIG.

As described above, the load element 21 for generating the voltage Vin according to the amount of the current Iin generated by the photodiode PD is configured to actively change the total resistance value according to the voltage level of the N1 node. Therefore, the problem of slowing the charge / discharge time is solved, thereby generating an analog type voltage signal Vin proportional to the amount of light received.

The pulse converter 3 receives the voltage signal Vin generated by the light receiving unit 2 and the reference voltage Vref generated by the reference voltage generator (not shown), so that the magnitudes of the two voltages Vin and Vref are mutually different. In comparison, when the voltage signal Vin is greater than the reference voltage Vref, a voltage of high level is output, and when the voltage signal Vin is less than the reference voltage Vref, a voltage of low level is output Vout. Will be

The pulse converting section 3 of the conventional optical interface circuit is typically " low " in accordance with the voltage magnitude relationship between the reference voltage Vref having an arbitrary fixed voltage value and the voltage signal Vin generated in the light receiving section 2; The final pulse waveform is output using an analog comparator (Comp.) That generates a voltage of "or" high "level.

Accordingly, the conventional optical interface circuit outputs an analog type internal voltage signal Vin and a pulse waveform voltage signal Vout as shown in FIGS. 3A and 3B.

FIG. 3A is a graph illustrating an analog type internal voltage signal Vin generated within a normal voltage shift and a reference voltage Vref generated by a reference voltage generator (not shown).

Here, the reference voltage Vref is a state in which the reference voltage Vref is applied at a fixed voltage value that is about the middle of the maximum value and the minimum value of the internal voltage signal Vin.

Therefore, the pulse converter 3 made of an analog comparator Comp. Outputs a pulse waveform as shown in FIG. 3B.

However, in the conventional optical interface circuit as described above, the reference voltage Vref having a fixed voltage value using the analog comparator Comp. And the voltage of the internal voltage signal Vin generated by the light receiving unit 2 are used. Since the pulse waveform is generated by comparing the magnitude relationship, when the DC level of the internal voltage signal Vin generated by the light receiving unit 2 is changed, any information according to the amount of light received by the light receiving unit 2 is changed. There is a problem that a corresponding normal pulse waveform cannot be output.

For example, as shown in FIG. 4A, when the DC level of the internal voltage signal Vin rises due to other causes inside or outside the light receiving unit 2, the fixed voltage is relatively higher than the fixed reference voltage Vref. Since the section in which the high internal voltage signal Vin is applied generates a "high" level voltage, in this case, the conventional optical interface circuit has a problem of outputting a distorted pulse waveform as shown in FIG. 4B.

As shown in FIG. 5A, when the DC level of the internal voltage signal Vin increases significantly due to other causes, and the minimum value of the internal voltage signal Vin is applied to a voltage higher than the reference voltage Vref, In the conventional optical interface circuit, as shown in FIG. 5B, only a signal of a "high" level is output, so that no information can be provided.

Accordingly, the present invention has been proposed to solve the problems of the prior art, and the voltage value of the internal voltage signal is sampled at an arbitrary time interval and converted / inputted into a binary information value to raise or lower the information value. By generating pulse waveforms of "high" or "low" level according to the amount of change, even if the DC level of the internal voltage signal changes, it is possible to stably output a normal pulse waveform corresponding to arbitrary information according to the amount of light received. Its purpose is to provide an optical interface circuit.

The present invention to achieve the above object and the light emitting unit for generating light; A light receiving unit which receives the light generated by the light emitting unit and generates an internal voltage signal Vin of an analog type proportional to the amount of received light; An N-bit A / D converter which receives the internal voltage signal generated by the light receiving unit, samples it, and converts / outputs it into a binary data value; A delay unit which receives the data output from the A / D converter and delays it for one sampling period and outputs the delayed data; An operation unit which receives the data output from the A / D converter and the delayed data output from the delay unit, compares the magnitude by subtracting the delayed data value from the data value, and outputs a subtraction value and a comparison result; The output control unit receives a subtraction value and a large comparison result from the operation unit, accumulates the subtracted values according to the large comparison result, and generates a pulse waveform of "low" or "high" when the accumulated subtraction value reaches a predetermined value. It is made to include.

1 is a circuit diagram showing a configuration of a conventional optical interface circuit.

2 is a graph showing Vin according to Iin in the circuit of FIG.

3A and 3B are graphs showing normal internal voltage signals and output pulses at this time.

4A and 4B are graphs showing the internal voltage signal at which the DC level is increased and the output pulse at this time.

5A and 5B are graphs showing an internal voltage signal at which the DC level is greatly increased and output pulses at this time.

6 is a block diagram showing a configuration of an optical interface circuit of the present invention.

7 is a block diagram showing the configuration of a pulse converter of the present invention;

8 is a graph showing an internal voltage signal and sampling timing.

9 is a flowchart illustrating the operation of the output control unit.

Explanation of symbols on the main parts of the drawings

31: A / D converter 32: delay unit

33: calculator 34: output controller

Hereinafter, with reference to the accompanying Figures 6 to 9 will be described the technical configuration and operation of the present invention.

An optical interface circuit according to the present invention, as shown in Fig. 6, the light emitting unit 10 for generating light; A light receiving unit 20 which receives the light generated by the light emitting unit 10 and generates an analog type internal voltage signal Vin proportional to the amount of light received; It consists of a pulse converter 30 for converting the internal voltage signal (Vin) generated by the light receiving unit 20 to a digital pulse waveform and outputting (Vout), wherein the characteristics of the present invention which is different from the prior art is a pulse The conversion section 30 is made as shown in FIG.

The pulse converter 30 of the present invention includes an N-bit A / D converter 31 which receives an internal voltage signal Vin generated by the light receiving unit 20, samples it, and converts / outputs it into a binary data value; A delay unit 32 which receives the data Dout (N) output from the A / D converter 31 and delays it for one sampling period and outputs it; The data Dout (N) output from the A / D converter 31 and the delayed data Dout (N-1) output from the delay unit 32 are inputted, and the delayed data value is subtracted from the data value. An arithmetic unit 33 for comparing and outputting a subtracted value diff and a large comparison result a, b; The subtraction value (diff) and the large and small comparison results (a, b) are input from the calculation unit 33, and the subtracted values (diff) are accumulated according to the large and small comparison results (a, b), and the magnitude of the accumulated subtracted value is constant. When the value is reached, the output control section 34 includes an output control section 34 for shifting the level of the output voltage Vout to generate a pulse waveform of "low" or "high".

The A / D converter 31 samples the internal voltage signal Vin output from the light receiving unit 20 at random intervals, and binary of the corresponding voltage level according to the internal voltage signal Vin at the sampling time point among 2N voltage levels. Output the data Dout (N). Of course, this data value is stored in an N-bit output buffer register (not shown) provided in the A / D converter 31 and outputted to the calculator 33 through this.

The delay unit 32 delays the N-bit data Dout (N) output from the A / D converter 31 for one sampling period to calculate the delayed N-bit data Dout (N-1). )

Accordingly, the calculation unit 33 performs data Dout (N) corresponding to the voltage value of the internal voltage signal Vin at the sampling point and data Dout corresponding to the voltage value of the internal voltage signal Vin before one sampling period. (N-1)) is input.

The calculation unit 33 of the present invention is a delayed N-bit data (Dout (N-1) output from the delay unit 32 from the N-bit data (Dout (N)) value output from the A / D converter 31) ) Is subtracted to output the subtracted value (diff) and the magnitude comparison result (a, b) through an N + 2 bit output register (not shown) provided therein.

At this time, two bits A and B of the N + 2 bit output register (not shown) store information on the magnitude comparison result, respectively, and are output to the output control unit 34 through this. That is, when the data Dout (N) value is larger than the delayed data Dout (N-1) value, " 1 " is written in the A bit, and the data Dout (D ( If the value is smaller than the N-1)) value, " 0 " is recorded in the A bit to thereby output (a: first comparison signal) to the output controller 34. In addition, if the data Dout (N) value and the delayed data Dout (N-1) value are the same, " 1 " is written in the B bit, otherwise, " 0 " The output controller 34 is configured to output (b: second comparison signal).

In the remaining N bits of the N + 2 bit output register (not shown), a value (diff) obtained by subtracting the delayed data (Dout (N-1)) value from the data (Dout (N)) value is recorded. It is made to output to the output control part 34. Therefore, as shown in FIG. 8, the large difference between the data Dout values input during the same sampling period means that the change, that is, the speed of increase and decrease of the internal voltage signal Vin, is faster.

9 is a flowchart showing the operation of the output control unit 34 of the present invention.

Hereinafter, referring to the accompanying FIG. 9, the output values a, b, and diff of the above-described calculation unit 33 are input, and according to the logic values of the first and second comparison signals a and b according to the comparison results. An output that accumulates a subtraction value and shifts the level of the output voltage when the magnitude of the accumulated subtraction value reaches a predetermined value C to generate a pulse waveform of "low" or "high". The specific operation relationship of the control part 34 is demonstrated.

The output control section 34 of the present invention consists of a plurality of registers (not shown) and a logic operator (not shown) to determine the voltage level of the final output pulse Vout.

First, the operation unit 33 operates to accumulate the subtracted values diff according to the logic values of the two bits A and B of the output register (not shown).

That is, when the logic value of the second comparison signal b is "low" and the logic value of the first comparison signal a is "high" (B = 0, A = 1), the data Dout (N) The subtracted value Diff subtracted the delayed data Dout (N-1) from the value is a positive value and corresponds to a period in which the internal voltage signal Vin increases.

At this time, the output control unit 34 stores the increase value of the internal voltage signal Vin by storing the subtraction value diff with the value of the Count register (not shown).

After that, it is checked whether the value (Count) of the Count register exceeds a predetermined value (C). If the count is less than the value, the increment by the next sampling data is continuously accumulated. If the value of the Count register exceeds the predetermined value (C), the value of the Count register is reset to "0", and the voltage of the "high" level is output (Vout = "1"). Here, the level of the output voltage (Output (N) = 1) is made to continue to output the conventional voltage level ("high") until the level transition signal is input.

When the logic value of the second comparison signal b is "low" and the logic value of the first comparison signal a is "low" (B = 0, A = 0), the data Dout (N) The subtracted value Diff subtracted from the delayed data Dout (N-1) is negative and corresponds to a period in which the internal voltage signal Vin decreases.

At this time, the output control unit 34 stores the subtraction value diff with the value of the Count register (not shown), thereby accumulating and recording the reduction width of the internal voltage signal Vin.

After that, if the accumulated Count register value (Count: accumulated subtraction value) decreases below a certain value (-C), and if it is larger than the predetermined value (-C), the decrease width by the next sampling data is continuously accumulated. . When the value of the Count register decreases below a certain value (-C), the value of the Count register is reset to "0", and the voltage of the "low" level is output (Vout = "0"). Here, the level of the output voltage (Output (N) = 0) is made to continue to output the conventional voltage level (“low”) until the level transition signal is input.

Here, the constant value C is a constant that determines the transition of the output voltage level. If the C value is set to about half of the difference between the maximum value and the minimum value of the internal voltage signal Vin, When the internal voltage signal Vin generated by the light receiving unit 20 increases by more than the C value, the pulse converter 30 of the present invention reduces the output voltage of the "high" level and decreases the output voltage of the "low" level by more than the C value. To generate it.

That is, as shown in Fig. 8, when the internal voltage signal Vin changes from time t1 to time t2, the output voltage does not transition to the "low" level, but only when it changes from time t1 to time t3. Transition to the "low" level.

Therefore, the present invention does not generate a pulse waveform of "low" or "high" according to the hostile voltage magnitude of the internal voltage signal Vin by using the fixed reference voltage Vref as in the prior art, and the internal voltage signal It is possible to generate a pulse waveform of "high" or "low" based on the relative increase / decrease width of (Vin).

As described above, the optical interface circuit according to the present invention samples the voltage value of the internal voltage signal at arbitrary time intervals, converts and inputs it into a binary information value, and according to the relative change amount of the rising or falling of the information value. By generating a pulse waveform of "high" or "low" level, even if the DC level of the internal voltage signal changes, it is possible to stably output a normal pulse waveform corresponding to arbitrary information according to the amount of light received. .

Claims (3)

A light emitting unit for generating light; A light receiving unit which receives the light generated by the light emitting unit and generates an analog type internal voltage signal Vin proportional to the amount of received light; In the optical interface circuit comprising a pulse converter for converting the internal voltage signal (Vin) generated by the light receiving unit to a digital pulse waveform, and outputs The pulse converter comprises: an N-bit A / D converter for receiving and sampling an internal voltage signal Vin generated by the light receiver and converting and outputting the binary data value; A delay unit which receives the data Dout (N) output from the A / D converter and delays the data for one sampling period; The data value Dout (N) delayed from the data value Dout (N) by receiving the data Dout (N) output from the A / D converter and the delayed data Dout (N-1) output from the delay unit. A subtracting unit for subtracting N-1)), comparing the magnitude relationship, and outputting first and second comparison signals a and b according to the subtraction value diff and the large comparison result; The subtractor receives the subtracted value diff and the first and second comparison signals a and b, and accumulates the subtracted values diff according to the logic values of the first and second comparison signals a and b. And an output control unit for generating a pulse waveform of "low" or "high" when the magnitude of the accumulated subtraction value reaches a predetermined value (C). The method according to claim 1, If the data value Dout (N) is larger than the delayed data value Dout (N-1), the operation unit outputs the logic value of the first comparison signal a as "1" and the data value Dout ( N)) is smaller than the delayed data value Dout (N-1), the logic value of the first comparison signal a is output as "0", and the data value Dout (N) and the delayed data value ( And outputting the logic value of the second comparison signal (b) as "1" when Dout (N-1)) is the same. The method according to claim 1, When the logic value of the first comparison signal a is "1", the output controller outputs a "high" level voltage when the accumulated subtraction value Count becomes larger than a predetermined value C. And when the magnitude of the cumulative value (Count) becomes smaller than a predetermined value (-C) when the logic value of the signal (a) is "0", the voltage of the "low" level is output.