KR20010074392A - Isolation method for semiconductor devices - Google Patents

Abstract

PURPOSE: A method for isolating a semiconductor device is provided to form a device isolation layer by forming a micro trench in order to improve operation fidelity of the trench burial by using a polysilicon as a device isolation layer. CONSTITUTION: The semiconductor device isolating method includes following steps. At first, an etching mask is formed on a predetermined portion of a semiconductor substrate(30) to expose a device isolation region. Then, the portion of the semiconductor substrate which is not protected with the etching mask is removed so as to form a perpendicular angle with respect to an etching profile to form a trench which a predetermined depth and width and having similar upper width and lower width. At third, the etching mask is removed. Then, the device isolation layer(330) is formed by burying the trench with a dielectric material. The angle of the etching profile is further greater than 85 degrees.

Description

Isolation method for semiconductor devices

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method for a semiconductor device, and more particularly, to form a trench having a width of 0.2 μm or less defining a device isolation region by vertically removing a predetermined portion of the substrate, thereby forming a non-doped polysilicon or A semiconductor that is formed by burying undoped polysilicon and high-temperature-USG in a laminated structure, overcomes the pattern size limitations of the shallow trench isolation method of the prior art, and forms a finer pattern so as to be suitable for the manufacture of more than one group of highly integrated devices. It is about shallow trench isolation of devices.

As the integration of semiconductor devices continues, technology development for reducing the device isolation region occupying a considerable area of the semiconductor device is actively progressing.

Technologies such as LOCOS have become unsuitable for device isolation technology of next-generation devices with densities of 256M DRAM or more due to the flatness of the isolation region surface and precise design rules.

Therefore, a BOX (buried oxide) type shallow trench isolation technology has been developed that can overcome the problems of various device isolation technologies. BOX type device isolation technology A trench is formed in a semiconductor substrate and has a structure in which silicon oxide or polysilicon which is not doped with impurities is embedded by chemical vapor deposition (hereinafter, referred to as CVD). Therefore, no buzz beaking occurs, there is no loss of the active region, and a flat surface can be obtained by embedding and etching back the oxide film.

However, such a trench type device isolation method also reduces the space of the device isolation region as the cell size is further reduced, so that the field breakdown voltage is lowered and punch-through may occur. Therefore, there is a need for a method for forming a trench having an ultrafine width of 0.2 μm or less.

When the STI process according to the prior art is applied to a next-generation device having such a size, the etching profile of the formed trench has an inclination angle of about 70-80 °, and thus it is difficult to secure the depth of the trench suitable for the device.

1A to 1C are process cross-sectional views showing a device isolation method of a semiconductor device according to the prior art.

Referring to FIG. 1A, a pad oxide film 11 for a buffer is formed on a semiconductor substrate 10 made of silicon by a thermal oxidation method, and chemical vapor deposition (hereinafter, CVD) is performed on the pad oxide film 11. Silicon nitride is deposited to form an etch protective film 12. In this case, the pad oxide film 11 serves to relieve stress due to the difference in thermal expansion rate between the substrate and the nitride film.

After the photoresist is applied on the etch protection film 12, a photoresist pattern exposing and exposing the surface of the etch protection film 12 over the device isolation region by performing exposure and development using an exposure mask defining a device isolation region is illustrated. No).

Next, using the photoresist pattern as an etching mask, the etching protection film and the pad oxide film of the portion not protected by the photoresist pattern are removed by anisotropic etching such as dry etching to expose a predetermined portion of the substrate 10. At this time, the remaining etching protection layer 12 serves to prevent the active region of the substrate from being etched in the chemical mechanical polishing (CMP) process when the device isolation layer is formed.

The trench is formed by etching the exposed device isolation region of the semiconductor substrate 10 to a predetermined depth by using the photoresist pattern as an etching mask. The trench is formed by anisotropic etching using reactive ion etching (hereinafter referred to as RIE) or plasma etching. At this time, the etching process is performed to have a constant etching depth and etching angle, the etching depth is generally about 3000-4000 ° and the etching angle which is the angle between the horizontal surface of the substrate 20 and the side profile of the trench to be etched is 75- It is around 82 °. The reason why the etching angle is formed to be inclined to have a predetermined angle is to prevent the generation of voids during deposition of an insulating material for filling trenches in a subsequent process.

Therefore, when the trench forming method according to the prior art is implemented, when the width of the trench becomes 0.15 μm or less as the device is ultra-highly integrated, the width of the trench must be widened to secure the etching depth required for the device design. It is impossible to form trenches that can satisfy the required values.

Then, the photoresist pattern is removed by oxygen ashing (O ₂ ahing) to expose the surface of the etching protection film 12 made of a nitride film.

Then, the insulating material layer 13 is formed on the trench and the etch protective film 12 to a thickness that sufficiently fills the inside of the trench. In this case, the insulating material layer 13 is formed by depositing a high temperature oxide film (HT-USG) or the like which is not doped with impurities on the entire surface of the substrate.

Referring to FIG. 1B, the insulating material layer 130 is removed by chemical mechanical polishing (CMP) so that the surface of the nitride film, which is an etch protection film, is exposed to leave the insulating material layer only in the trench. And the planarization of the top of the substrate is achieved. At this time, a part of the nitride film, which is the etch protection film 120, is also removed from the predetermined thickness and only a part of the nitride film remains on the pad oxide film 11.

Referring to FIG. 1C, the etching protection layer and the pad oxide layer are sequentially removed by a wet etching method to expose the active region of the semiconductor substrate 10 to complete the device isolation layer 130. At this time, the etch protective film is a nitride film is wet-removed with a high temperature phosphoric acid solution, the pad oxide film is removed and the edge portion of the insulating material layer 130 remaining in the pre-cleaning process is also slightly removed.

Therefore, when the width d1 of the trench formed as described above is 0.15 μm or less, the depth of the formed trench may not be as deep as necessary, so that an isolation layer required for device fabrication may not be formed.

Thus, the problem of the STI method having a trench width of 0.18 mu m or less according to the prior art is shown in FIG.

2 is a cross-sectional view illustrating a problem in forming a device isolation trench in a semiconductor device formed according to the prior art.

Referring to FIG. 2, an etching protection film 22 made of a nitride film, a pad oxide film 21, and a substrate are formed by using an etching mask (not shown) for forming a trench in which a device isolation film is to be formed on a silicon substrate 20. The part is etched.

In this case, the etching is performed by anisotropic etching such as reactive ion etch, the etching angle is formed to be inclined at a predetermined angle. This is to prevent the generation of voids during deposition of an insulating material layer such as an oxide film for filling the trench in a subsequent process.

That is, the dimension of the trench T3 required to be suitable for device isolation of the ultra-high integrated device should be similar to the upper width and the lower width of the trench, and the lower width of the trench T2 etched according to the prior art has an etching depth. Inversely narrowing, ultimately the etch stops without reaching the required depth.

The device isolation method of the conventional semiconductor device described above has to form a trench having an inclined etching profile due to the limitation of the filling capability of the trench buried material, so that the required trench dimension cannot be secured at the trench width of 0.18 μm or less, thus suitable device for the device. If the isolation film cannot be formed, and the trench width is required to be 0.15 µm or less, the phenomenon that the etching is interrupted during the trench formation occurs, and it is difficult to secure the required etching depth even at 0.18 µm or more.

Accordingly, an object of the present invention is to form a trench having a width of 0.2 μm or less defining a device isolation region by vertically removing a predetermined portion of the substrate, and forming the undoped polysilicon or undoped polysilicon and high temperature- A shallow trench isolation method for semiconductor devices in which USG is formed and buried to overcome the pattern size limitations of the shallow trench isolation device of the prior art to form a finer pattern to be suitable for fabricating one or more gigabytes of highly integrated devices. To provide.

In order to achieve the above object, a device isolation method of a semiconductor device according to the present invention includes forming an etching mask exposing a device isolation region on a predetermined portion of a semiconductor substrate, and etching the portion of the semiconductor substrate not protected by the etching mask. Removing the profile close to vertical to form a trench having a predetermined depth and width having a similar upper width and lower width, removing the etching mask, and filling the trench with an insulating material to form a device isolation layer. It consists of a process comprising the steps.

1A to 1C are process cross-sectional views showing a device isolation method of a semiconductor device according to the prior art.

2 is a cross-sectional view illustrating a problem in forming a device isolation trench in a semiconductor device formed according to the prior art;

3A to 3C are process cross-sectional views showing a device isolation method for a semiconductor device according to the first embodiment of the present invention.

4A to 4C are process cross-sectional views showing a device isolation method of the semiconductor device according to the second embodiment of the present invention.

In general, when forming shallow trench isolation (STI) or profile grooved isolation (PGI) as an isolation method between cells using trenches, silicon oxide is used as a trench filling material.

However, as the integration degree of the device is further increased, the space occupied by the trench, which is a device isolation region, in a limited space is also reduced. Since the reduction of the device isolation portion due to the reduction in the cell size necessarily reduces the width of the trench in which the device isolation film is formed, thus, the trench depth may not be secured by the method of forming the trench inclined as in the prior art.

Therefore, in the present invention, it is possible to form an ultra-fine device isolation region having a width of 0.2 μm or less by overcoming the limitation of the trench formation process by the conventional STI, and thus it is applicable to the manufacture of memory devices of 1 gigabyte or more. At this time, the formed trench has an etch angle close to 85 ° or more, and the trench is buried with undoped polysilicon or undoped polysilicon / USG (undoped silicate glass) to form a device isolation layer. .

That is, the present invention forms the isolation region of the semiconductor device by using the shallow trench formation etching and the undoped polysilicon having ultra fine dimensions.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

3A to 3C are process cross-sectional views showing a device isolation method of the semiconductor device according to the first embodiment of the present invention.

Referring to FIG. 3A, a pad oxide film 31 for a buffer is formed on a semiconductor substrate 30 made of silicon by a thermal oxidation method, and chemical vapor deposition (hereinafter, CVD) is performed on the pad oxide film 31. Silicon nitride is deposited to form an etch protection film 32. In this case, the pad oxide layer 31 serves to relieve stress due to the difference in thermal expansion rate between the substrate and the nitride layer, and the etch protection layer 32 is formed in the CMP (chmical mechanical polishing) step of a subsequent planarization process. It is formed to protect the active area from being etched.

After the photoresist is applied on the etch protection film 32, a photoresist pattern exposing and exposing the surface of the etch protection film 32 on the device isolation region by performing exposure and development using an exposure mask that defines the device isolation region is shown. No).

Next, using the photoresist pattern as an etching mask, the etching protection film and the pad oxide film of the portion not protected by the photoresist pattern are removed by anisotropic etching such as dry etching to expose a predetermined portion of the substrate 30. In this case, the remaining etching protection layer 32 serves to prevent the active region of the substrate from being etched in the CMP process when the device isolation layer is formed.

The trench is formed by etching the exposed device isolation region of the semiconductor substrate 30 to a predetermined depth by using the photoresist pattern as an etching mask. The trench is formed by anisotropic etching using reactive ion etching (hereinafter referred to as RIE) or plasma etching. At this time, the etching process is performed to have a constant etching depth and the etching angle required for device isolation, in the embodiment of the present invention, the etching angle which is the angle between the horizontal surface of the substrate 30 and the side profile of the trench to be etched is 85 ° This makes it almost close to vertical.

The reason for forming the etching angle close to the vertical is to secure the necessary etching depth and to form an insulating material for burying the trench in a subsequent process, such as undoped polysilicon, to prevent the generation of voids during deposition. Because. In addition, the etching depth can be formed to 0.1㎛ or less.

Therefore, when the trench forming method according to the embodiment of the present invention is implemented, as the device is ultra-highly integrated, even if the trench width is 0.15 μm or less, the trench depth required for the device design and the trench width can be secured simultaneously. It is possible to form trenches for ultra-fine device isolation.

Then, the photoresist pattern is removed by oxygen ashing (O ₂ ahing) to expose the surface of the etching protection film 32 made of a nitride film.

An insulating material layer 33 is formed on the trench and the etch protection film 32 to a thickness that sufficiently fills the inside of the trench. In this case, the insulating material layer 33 is formed by depositing polysilicon that is not doped with impurities so as not to cause voids.

Referring to FIG. 3B, the insulating material layer is removed by chemical mechanical polishing (CMP) so that the surface of the nitride film, which is an etch protection film, is exposed to leave the insulating material layer only in the trench. And the planarization of the top of the substrate is achieved. In this case, a part of the nitride film, which is the etch protection film 320, is also removed from the predetermined thickness, and only a part of the nitride film remains on the pad oxide film 31.

Referring to FIG. 3C, the etch protection layer and the pad oxide layer are sequentially removed by a wet etching method to expose the active region of the semiconductor substrate 30 to complete the device isolation layer 330. At this time, the etching protective film is a nitride film is wet-removed with a high temperature phosphoric acid solution, the pad oxide film is removed and the edge portion of the insulating material layer 330 remaining in the pre-cleaning process is also slightly removed.

Therefore, when the width d3 of the trench thus formed is 0.15 μm or less, the depth of the trench to be formed can be as deep as necessary, so that an isolation layer required for manufacturing an ultrafine device can be formed.

4A to 4C are process cross-sectional views showing a device isolation method of the semiconductor device according to the second embodiment of the present invention.

Referring to FIG. 4A, a pad oxide film 41 for a buffer is formed on a semiconductor substrate 40 made of silicon by thermal oxidation, and chemical vapor deposition (hereinafter, CVD) is performed on the pad oxide film 41. Silicon nitride is deposited to form an etch protective film 42. At this time, the pad oxide film 41 serves to relieve stress due to the difference in thermal expansion rate between the substrate and the nitride film, and the etch protection film 42 is formed in the CMP (chmical mechanical polishing) step of the subsequent planarization process. It is formed to protect the active area from being etched.

After the photoresist is applied on the etch protection film 42, a photoresist pattern exposing and exposing the surface of the etch protection film 42 on the device isolation area by performing exposure and development using an exposure mask that defines the device isolation area. No).

Next, using the photoresist pattern as an etching mask, the etching protection film and the pad oxide film of the portion not protected by the photoresist pattern are removed by anisotropic etching such as dry etching to expose a predetermined portion of the substrate 40. In this case, the remaining etching protection layer 42 serves to prevent the active region of the substrate from being etched in the CMP process when forming the device isolation layer.

The trench is formed by etching the exposed device isolation region of the semiconductor substrate 40 to a predetermined depth by using the photoresist pattern as an etching mask. The trench is formed by anisotropic etching using reactive ion etching (hereinafter referred to as RIE) or plasma etching. In this case, the etching process is performed to have a constant etching depth and the etching angle required for device isolation, in the embodiment of the present invention, the etching angle, which is the angle between the horizontal surface of the substrate 40 and the side profile of the trench to be etched, is 85 °. This makes it almost close to vertical.

The reason for forming the etching angle close to the vertical is to secure the necessary etching depth and to form an insulating material for burying the trench in a subsequent process, such as undoped polysilicon, to prevent the generation of voids during deposition. Because. In addition, the etching depth can be formed to 0.1㎛ or less.

Therefore, when the trench forming method according to the embodiment of the present invention is implemented, as the device is ultra-highly integrated, even if the trench width is 0.15 μm or less, the trench depth required for the device design and the trench width can be secured simultaneously. It is possible to form trenches for ultra-fine device isolation.

Then, the photoresist pattern is removed by oxygen ashing (O ₂ ahing) to expose the surface of the etching protection film 42 made of a nitride film.

Then, the first insulating material layer 43 is formed on the trench and the etch protection layer 42 to fill the inside of the trench to a predetermined thickness. In this case, the first insulating material layer 43 is formed so as not to void the polysilicon which is not doped with impurities and is formed so as not to completely fill the trench.

Next, a second insulating material layer 44 is formed on the first insulating material layer 43 to a thickness that completely fills the trench. In this case, the second insulating material layer 44 is formed by depositing a high temperature oxide film (HT-USG) or the like, which is not doped with impurities, on the entire surface of the substrate.

Referring to FIG. 4B, the insulating material layer is removed by chemical mechanical polishing (CMP) so as to expose the surface of the nitride film, which is an etch protection film, in order to leave the first and second insulating material layers only in the trench. The first and second insulating material layers 430 and 440 remain to planarize the substrate. At this time, a part of the nitride film, which is the etch protection film 420, is also removed from the predetermined thickness and only a part of the nitride film remains on the pad oxide film 41.

Referring to FIG. 4C, the etch protection layer and the pad oxide layer are sequentially removed by a wet etching method to expose the active region of the semiconductor substrate 40 to complete the device isolation layers 430 and 440 having a stacked structure. At this time, the etching protective film as a nitride film is wet-removed with a high temperature phosphoric acid solution, and the pad oxide film is removed by a pre-cleaning process or the like.

Therefore, when the width d4 of the trench thus formed is 0.15 μm or less, the depth of the trench to be formed can be as deep as necessary, so that an isolation layer required for manufacturing an ultrafine device can be formed.

Therefore, the present invention can form a device isolation film by forming an ultra-fine trench can be applied to the production of next-generation semiconductor devices, such as DRAM or more than 1 gigabyte, and the reliability of the trench filling because undoped polysilicon is used as the device isolation film This improvement has the advantage of improving the device isolation characteristics.

Claims (5)

Forming an etching mask exposing the device isolation region at a predetermined portion on the semiconductor substrate; Removing a portion of the semiconductor substrate which is not protected by the etch mask so that an etch profile is close to a vertical to form a trench having a predetermined depth and width and a top width and a bottom width similar to each other; Removing the etching mask; Forming a device isolation film by filling the trench with an insulating material. The method according to claim 1, And an angle of the etching profile is 85 ° or more. The method according to claim 1, And the insulating material is formed of undoped polysilicon. The method according to claim 1, And the device isolation film is formed in a stacked structure of undoped polysilicon and undoped silicate glass. The method according to claim 1, The trench isolation device is characterized in that the width of 0.20㎛ or less formed.