KR20010070213A - Apparatus and method for independent threshold voltage control of memory cell and select gate in a split-gate eeprom - Google Patents

Abstract

PURPOSE: An apparatus for controlling a threshold voltage of a split gate EEPROM and a memory cell independently and a method thereof are provided, which can broaden a threshold voltage window value of a memory transistor and a selection transistor and can prolong an operation lifetime of the memory cell. CONSTITUTION: A memory cell(11) has a memory transistor(12) and a selection transistor(14) sharing a common gate. The memory cell includes two independent and separate threshold voltage control parts injected onto different channel region parts of a substrate of the memory cell. One threshold voltage control part is arranged as to the memory transistor to affect a threshold voltage of the memory transistor and is formed with an N-type impurity(34) like As or P, and another threshold voltage control part is arranged as to the selection transistor to affect a threshold voltage of the selection transistor and is formed with a P type impurity(36) like B or BF.

Description

Apparatus and method for independently adjusting threshold voltages of memory cells and select gates in a split gate Y pyrom {APPARATUS AND METHOD FOR INDEPENDENT THRESHOLD VOLTAGE CONTROL OF MEMORY CELL AND SELECT GATE IN A SPLIT-GATE EEPROM}

FIELD OF THE INVENTION The present invention relates to electrically erasable and programmable read only memory (EEPROM) cells of a split gate p-channel, and in particular, an independent and distinct threshold voltage (Vt) that shares an active channel region and optimizes the programming window value of the memory cell. A division gate memory cell having a selection transistor having a control portion and a memory transistor is provided.

EEPROM memory cells are a type of nonvolatile semiconductor memory in which information can be electronically programmed into each memory element or cell and can be erased from each memory element or cell. Split-gate EEPROM memory cells are one form of EEPROM cells in which select and memory transistors are merged to share the same polysilicon gate, commonly known as poly2 or select gate. The poly2 gate forms both the word line or gate electrode of the select transistor and the control gate of the memory transistor. Such a configuration allows for a smaller cell size, ie provides a more efficient design.

Information is stored in a split gate EEPROM memory cell by isolating a dielectric layer and placing charge on a " floating gate " region of conductive polysilicon (commonly known as poly 1) that is electrically isolated from other conductive regions of the device. The charge on the floating gate can be detected when reading the memory cell because it changes the threshold voltage of the memory transistor. This change in threshold voltage changes the amount of current flowing through the cell when voltage is supplied to the cell during a read operation and the current can be detected by the sense amplifier circuit.

In a typical EEPROM design, n-channel cells are built on p well substrates. In U.S. Patent No. 5,790,455, entitled "Low Voltage Single Supply CMOS Electrically Erasable Read Only Memory", issued to Kaywood, assigned to the present application and incorporated herein by reference, the configuration itself is inverted. A p-channel device on an n well in which a p-type substrate is present is described. The advantage of such a configuration is that it maintains a similar write speed comparable to the prior art, while reducing the magnitude of the supply voltage required to write to and erase from the device. Such a configuration also eliminates any component that is functionally necessary in the prior art.

Referring to FIG. 1, the study of Kwood is illustrated from a general perspective on a single memory register 1. An n well 3 is created in the p type substrate 2 and a p type diffusion region for the source 4 and drain 5 is created in the n well 3. That is, in this design, the select and memory registers share a common active channel region. The poly1 or floating gate 6 of the memory transistor 1 is made after the formation of the active region for the source 4 and the drain 5. The poly 2 or select gate 7 of the memory transistor is combined on the floating gate 6. Various non-conductive layers 8 (not illustrated) isolate one another from the source 4, the drain 5, the floating gate 6 and the select gate 7.

In Kwood's work and other prior p-channel designs, the channels of both the memory cell and the select transistor are fitted with the same threshold voltage regulation implant or regulation. The threshold voltage regulator in the device is used to set the threshold voltage of the selection transistor to a predetermined value. However, the threshold voltage of the memory transistor is not set to any value and is assumed to be a "natural" Vt value (zero charge on the floating gate). The disadvantage of this study is that when the p-channel memory transistor is "programmed" into a conductive state, its threshold voltage is a greater positive value than the selection transistor. In such a case, the threshold voltage of the selection transistor alone controls the threshold voltages of the combined memory transistor and the selection transistor. As such, a portion of the cell's threshold window (Vt window) value, that is, the difference between the cell's threshold voltages in the programmed and erased state, is lost.

For example, a select transistor typically has Vt set at -0.8V, while a memory cell transistor can have a programmed Vt of + 3.0V and an erased Vt of -5.0V. The total threshold window value of the memory cell and the select gate will be from -0.8V to -0.5V and will not be the threshold window value of the memory cell alone from + 3.0V to -5.0V. Part of the threshold window value from + 3.0V to -0.8V is lost. This disadvantage reduces the working period of the memory cell.

In particular, the Vt window value of a cell varies with the number of program and erase periods it implements. The Vt window value typically collapses with increasing program / erase cycles due to electrons trapped in the tunnel oxide. Figure 2 illustrates the p-channel split gate EEPROM how it decreases with the period of the Vt window value. The thick lines for Vtw and Vte represent the critical mean of the large population of cells. The dashed line on one side shows the spread at Vtw and Vte due to handling the variation. In addition to the collapse of the Vt window value with the variation processing and program / erase cycles, some loss of charge along with time from the erased or written cell should also be accounted for. This is represented by the inner pair of dashed lines that reduce even the minimum Vt window value. At any given number of cycles, the minimum Vt window value is taken inside the dashed envelope. Beyond all of these, there are other effects that require the Vt window values to be made wide such as sense amplifier travel point fluctuations and fluctuations due to operation beyond the temperature range.

There are many ways to increase the Vt window value, but they all have their drawbacks. For example, the Vt window value can be made wider by using a larger programming voltage, Vpp. However, if Vpp is increased, then the tunnel oxide depends on the greater electric field stress in each program / erase cycle and the collapse of the period Vt window value becomes worse. The Vt window value can also be made wider by making the tunnel oxide thinner. However, making the tunnel oxide thinner will cause the charge stored in the floating gate to leak more over time after the tunnel oxide is stressed with a program / erase cycle. This effect is known as stress induced leakage current (SILC). The Vt window value can be wider by increasing the coupling ratio of the cell. The increase in the bonding ratio of the cell increases the silicon chip area consumed by the cell or reduces the interpoly dielectric thickness. It is not desirable to increase the silicon chip area for obvious reasons, and reducing the covalent dielectric may also make the cell more difficult to manufacture in high yield processes as well as reduce the cell's ability to retain charge.

Thus, it is desirable to optimize the programming window value of a memory cell in a p-channel split gate EEPROM without any disadvantages associated with the above mentioned solution.

According to one aspect of the present invention, a divided gate EEPROM memory cell is provided. This memory cell includes a memory transistor and a selection transistor that share a common gate. The memory cell further includes two independent and separate threshold voltage regulators inserted at different portions of the channel region of the substrate of the memory cell. One of the threshold voltage regulators is located in relation to the memory transistor to influence its threshold voltage. Another threshold voltage regulator is positioned relative to the selection transistor to influence its threshold voltage. In a preferred embodiment of the present invention, the threshold voltage regulating portion related to the memory transistor is formed of n-type impurities, preferably arsenic or trivalent phosphorus contents. In such an embodiment, the threshold voltage regulator associated with the select transistor consists of p-type impurities, preferably boron or BF ₂ .

In another aspect of the present invention, a method of combining split gate memory cells is provided. The method includes inserting a threshold voltage regulator associated with a memory transistor in a channel region of a substrate of a memory cell. The method further includes inserting a threshold voltage regulator associated with a select transistor in a different portion of the channel region of the cell substrate. In a preferred method, a threshold voltage control associated with a memory transistor is formed by inserting n-type impurities into the channel region of the substrate. In such a method, the threshold voltage adjustment associated with the selection transistor is formed by inserting a p-type impurity into the feather region of the substrate. During this step, the insertion of p-type impurities in the portion of the channel region associated with the memory transistor is provided by a floating gate that acts as a self-aligning mask. In one embodiment of the present invention, the step of inserting n-type impurities is performed before the floating gate is formed. In another embodiment, this step is performed after the floating gate is formed.

Independent and individual threshold voltage regulators widen the threshold voltage window values of the memory transistors and the selection transistors and thus extend the operating life of the memory cells.

Other objects and advantages of the present invention will become apparent from the following detailed description with reference to the accompanying drawings.

1 is a cross-sectional view of a memory cell in a conventional p-channel split gate EEPROM.

2 is a graph illustrating threshold voltages of memory cells in a programmed and erased state according to the number of program / erase cycles of a cell.

3 is a partial plan view of a memory cell array in a p-channel split gate EEPROM of the present invention;

4 is a cross-sectional view taken along the line A-B of FIG.

5 is a graph showing the write and erase threshold voltages Vt of the p-channel split gate EEPROM of the present invention according to the program voltage Vpp.

6-18 are process flow diagrams illustrating an example of a method of implanting separate threshold voltage controlled impurities for a selection transistor and a memory transistor of the present invention.

19-29 are process flow diagrams showing another example of a method for implanting separate threshold voltage controlled impurities for a select transistor and a memory transistor of the present invention.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. 3, a top left portion of a portion of the memory cell array 10 according to the present invention is shown. In the figure, cells of 8 columns (8 bit lines) and 8 rows (8 word lines) in width are shown. The bottom right of the memory cell shows the added columns and rows that form the rest of the cell array. In the upper left of the memory cell, there is a peripheral circuit that accesses the memory array and performs functions of other chips.

For simplicity of illustration, the present invention describes a single memory cell. 4 is a cross-sectional view of the A-B line in the upper left corner of the array 10 of FIG. 3, showing a single memory cell 11 according to the present invention. The memory cell 11 includes a memory transistor 12 and a selection transistor 14 formed on the p-type silicon substrate 16. This memory cell 11 is located in the formed n well formed on the substrate 16. The substrate 16 has a p-type diffusion layer that forms the source 18 and the drain 20. The metallic contact portion 24 is disposed over the p-type region 18, and the metal bitline drain contact portion 26 is disposed in the p-type region 20. The memory transistor 12 includes a floating gate 28 and a select gate 30, which are conductor layers, and the conductor layer of the select gate 30 is shared with the word line of the select transistor 14.

The memory cell 11 includes a separate injection of threshold voltage control impurities 34 and 36 for the memory transistor 12 and the selection transistor 14, respectively. The threshold voltage regulating impurity 34 is an n-type impurity using arsenic (As) or phosphorus (p), and the other threshold voltage regulating impurity 36 is a p-type impurity using boron (B) or BF. The n-type impurity has the effect of improving the threshold voltage window value (window value = VV-Vtw) generated from the merged cell structure. The impurity implanter varies the memory transistor 12 threshold voltage in the negative direction in the programmed and erased states. For example, arsenic (As) impurity implantation of about 1.0 X 10 ¹³ cm ^-2 only in the cell channel region causes the cell's program threshold voltage Vt to fluctuate to 0.0 V (moving 3V in the negative direction) and in the erased state. The threshold voltage Vt is changed to -8.0 V by the same amount. The threshold window values of the memory transistor 12 and the selection transistor 14 are from -0.8V to -8.0V. It is important that the threshold voltage of the selection transistor 14 does not move in the negative direction like the memory transistor 12. Because the total threshold window value changes negatively without expanding in width. Two independent threshold voltages suppress this problem.

5 is a graph of the threshold voltage Vte in the erased state and the threshold voltage Vtw in the programmed state according to the program voltage Vpp of the memory cell 11. This graph has a Vte-Vpp curve and a Vtw-Vpp curve. The values of Vte in the Vte-Vpp curve are those obtained when the program cell is first written when Vpp = 16V, and then erased by another Vpp value. As Vpp increases, Vte increases with a negative value. In fact, each time Vpp increases by 1V, Vte is biased by approximately 1V. The Vte value is measured in the following way. The overall threshold value in the combination of the selection transistor and the cell transistor in the erased state is determined by the cell transistor threshold. The polysilicon gate voltage (Vg) shared by the two transistors is in the range of 0V to negative values. The select transistor initially operates (eg at Vg = -1.3 V) but does not flow current Id because the cell transistor is not operated. As a result, since the two transistors coexist, Vg has a negative voltage range sufficient for the cell transistor to operate and current to flow, and the gate voltage (1) at the current Id value of 1 에서 in the erased state (Vg = Vte) Vg) is related to the threshold voltage in the erased state.

The values of Vtw in the Vtw-Vpp curve are the values obtained when first erased when Vpp = 16V, and then the cells are programmed by different Vpp values. Each time Vpp increases by 1V, Vtw increases by approximately 1V. When Vpp = 12V, the curve changes from Vtw = -1.0V to -1.5V. Even if Vpp increases above 12V, Vtw remains -1.0V to -1.5V. At this point, the selection transistor has a threshold voltage Vt that is more negative than that of the cell transistor. So in this situation it is the selection transistors that drive the two transistors.

In FIG. 5, the virtual Vt window value and the actual Vt window value are also displayed. The virtual Vt window value is a Vt window value obtained when the selection transistor has not limited the threshold of the program state. In the present invention, the inclined portion of the Vte-Vpp and Vtw-Vpp curves is the threshold voltage range controlled by the cell transistor, while the flat portion of the Vtw-Vpp curve is the threshold voltage range controlled by the selection transistor. In the manufacturing process of the present invention, the threshold voltage values of the two transistors are adjusted separately from each other, and the flat surface of the Vtw-Vpp curve is kept steady. On the other hand, two sloped curves are shifted downward. This is the main effect of widening the actual Vt window value for a given Vpp value.

Referring to the two manufacturing methods of the memory cell 11 of the present invention, FIGS. 6 to 18 show two photoresist masking steps, and FIGS. 19 to 29 show one photoresist masking step.

After performing other steps in the manufacturing process of the memory cell 11, n well formation, device isolation, and oxide growth do not form part of the present invention. This manufacturing process step is described in FIGS. 6 to 18. Initially, a sacrificial oxide film, such as a SiO ₂ layer, is formed over the n well 22 of the substrate 16 proximate the field SiO ₂ layer 102. SiO ₂ layer 100 is about 50-500 angstroms thick. SiO ₂ layer 100 is either a thermally grown layer (not shown) or a deposited layer. Next, as shown in FIG. 7, the photoresist layer 104 is patterned using a mask for exposing the n well onto the silicon substrate 16. Referring to FIG. 3, the photoresist layer 104 remains in peripheral circuits, but not in at least some memory cells 10.

Next, as shown in FIG. 8, the n-type impurity 106 is implanted into the surface of the n well 22 using an atom beam, which is a conventionally known ion implanter. The n-type impurities implanted at this stage have already been concentrated in n wells. Since the n-type impurity loses the electronics when it is combined with the lattice of the silicon substrate, it is ionized to "+" as shown in the drawing. Arsenic (As) or phosphorus (p) is mainly used as an n-type impurity, and the injection amount is preferably 5.0 × 10 ¹⁴ cm ⁻² . In the present invention, the implantation of n-type impurities is not important. In FIG. 9, the photoresist layer 104 is removed by dry plasma etching and wet chemical etching.

Next, in FIG. 10, the sacrificial layer SiO ₂ layer 100 is removed by wet chemical etching and other known equivalent methods.

The next step is to form the tunnel dielectric (the gate of the memory transistor) and the floating gate 28. First, in FIG. 11, a tunnel dielectric layer 108 having a thickness of 60-120 angstroms is formed in the channel region of the memory transistor 12 and the selection transistor 14. Next, in FIG. 12, the floating gate 28 is formed by the polysilicon layer 110 stacked in the thickness of 600-5000 angstroms (most optimally 1500 angstroms) on the tunnel dielectric 108. Next, the polysilicon layer ( 110 is an n-type or p-type impurity is added to form a conductor layer. Next, the dielectric layer 112 is formed of one or more layers on the polysilicon layer 110.

Next, a photoresist layer 114 is laminated to define the floating gate 28 by patterning with a mask. Dry plasma etch in FIG. 14 to leave at least a portion of the SiO ₂ layer above the channel band. Photoresist layer 114 protects the floating gate 28 area during etching. In FIG. 15, the photoresist layer 114 is removed during the dry plasma etching or the wet chemical etching process, leaving only the floating gate pattern 28.

Next, the threshold voltage regulation injection unit 36 of FIG. 4 is formed. Initially, the photoresist layer 116 is laminated to a peripheral circuit. 3 and 16, however, all memory arrays 10, including memory cells 11, are not masked by the photoresist layer 116 during this step. Next, the p-type impurity 118 is implanted into the n well. When the p-type impurity is combined with the lattice of the silicon substrate, the home appliance is obtained and ionized to "-" as shown in the drawing. As the p-type impurity, boron (B) or BF ₂ is mainly used, and the injection amount is preferably 5.0 × 10 ¹⁴ cm ⁻² . In addition, the energy required for ion implantation is necessary to penetrate the tunnel dielectric 108. The floating gate 110 prevents p-type impurities from being injected into the memory transistor portion of the channel. Therefore, it functions as a mask for separating the n-type impurity into the p-type impurity. The advantage of using a floating gate is to automatically align the injected material. Therefore, the implanted impurities of p-type and n-type are automatically aligned. Next, as shown in FIG. 18, the photoresist layer 116 is removed by dry plasma etching and wet chemical etching.

There is an alternative method of using one pot register rather than two photoresists in threshold voltage injection. This reduces the process cost. In this method, n-type impurities are not implanted into the channel region before the polysilicon layer to make the floating gate 28 is stacked and patterned. After the floating gate 28 is patterned, a new photoresist mask is applied to successfully implant two impurities. Impurities (34) are implanted into a memory cell or transistor by using n-type impurities, which are phosphorus (p) or arsenic (as), when there is enough energy to completely penetrate the polysilicon layer to make the tunnel oxide layer and the floating gate. This is accomplished. In this case, the n-type impurity is injected into the cell channel near the surface to shift the threshold voltage (Vt) of the cell, but penetrates deeply out of the polysilicon layer. The p-type impurities of boron (B) or BF ₂ have been implanted with the photoresist mask so far. This impurity is interrupted by the polysilicon layer because it is made at low energy. However, it is injected to the surface of the channel of the select transistor 14 to adjust the threshold voltage Vt. This technique is evaluated as a general technique, but it is not important that p-type impurities are implanted, for example, before n-type impurities. The advantage of this method is that the cost of using less one photoresist is reduced, and the manufacturing process at high temperature can be reduced, which enables more effective threshold voltage control. A further advantage is that deep n-type impurities implanted in the select transistor 14 channel band act as deep punch-through suppression impurities in select terminal 14. It will ideally shut off current if the cell is taken out of the process.

Other process steps according to the method of the present invention are described with reference to FIGS. 19 to 29. 19 shows that after the n well is formed, device isolation, a field oxide growth layer 200 and a sacrificial SiO ₂ layer 202 are formed. 20 shows the SiO ₂ layer 202 having a thickness of about 50-500 Angstrom removed by wet chemical etching. 21 shows that a tunnel dielectric film 204, about 60-120 angstroms thick, is formed over the channel bands of a memory transistor and a select transistor. Next, FIG. 22 deposits a polysilicon layer 206 having a thickness of 600-5000 angstroms. Later, the polysilicon layer 206 becomes a floating gate. Next, the polysilicon 206 is treated in the same manner as the polysilicon 110 described above. 22 forms dielectric layer 208 on one or more layers in the same manner as dielectric layer 112 described above on polysilicon layer 206.

Next, FIG. 23 shows forming the porter resist layer 210. The photoresist layer 210 is patterned with a mask to define the floating gate 28. 24 uses dry prisma etching to leave tunnel dielectric 204 partially at least in the channel band. 25 removes the photoresist layer 210 using dry plasma etching and wet chemical etching, leaving only the floating gate pattern 28.

Next, the threshold voltage adjusting units 34 and 38 are formed. Initially it begins by stacking the port resist layer 212 in the range of the peripheral circuit. 3 and 26, the memory array 10 including the memory cells 11 is not masked by the port resist layer in this process. FIG. 27 shows an n-type impurity such as phosphorus (p) or arsenic (As) when implanted when the impurity atoms have sufficient energy to penetrate the dielectric layer 208, the polysilicon layer 206, and the tunnel oxide layer 204. do. The outside of the cell channel band is covered with the dielectric layer 208 and the polysilicon layer 206, and n-type impurities penetrate deep into the silicon substrate. The outer side is the selection transistor channel 14 band. In this band, the n-type impurity is far from the surface and does not affect the selection transistor threshold voltage. As described above, since the n-type impurity loses the home appliance when combined with the lattice of the silicon substrate, it is ionized to "+" as indicated in the drawing. The injection amount is preferably 5.0 × 10 ¹⁴ cm ⁻² .

In the next step, the p-type impurity 216 is implanted when the impurity atoms have sufficient energy to penetrate the tunnel dielectric layer 204, but the dielectric layer 204, the polysilicon layer 206, and the region to define the memory transistor channel band. The energy is not large enough to penetrate the tunnel dielectric 204. 28, n-type impurities can penetrate the tunnel dielectric 204 outside of this region. In other words, this region defines the select transistor channel band. Since the p-type impurity is close to the surface in this region, the selection transistor 14 threshold voltage changes. In other words, as described above, when a p-type impurity is combined with a lattice of a silicon substrate, a home appliance is obtained and ionized to "-" as shown in the drawing. The p-type impurity mainly uses boron (B) or BF ₂ . The injection amount is preferably 5.0 × 10 ¹⁴ cm ⁻² . 29 shows that photoresist layer 212 has been removed by dry plasma etching and wet chemical etching.

As shown in FIG. 4, a common electrode gate or a selection gate and a selection gate of a memory transistor, a source and a drain of a memory cell, a metal contact portion, and the like are formed using a known technique, and the forming step of these elements is not important in the present invention. .

Although embodiments related to the manufacture of p-channel cells have been described, the present invention may be equally applied to n-channel cells. In this application the threshold voltage regulation implant impurities are reversed. In other words, as shown in FIG. 4, p-type impurities such as boron (B) and BF ₂ form a threshold voltage control unit of the memory transistor 12, and p-type impurities such as phosphorus (p) and arsenic (As) The threshold voltage regulation of the selection transistor 14 is formed. The present invention should be evaluated separately from other manufacturing processes. Therefore, other various modified methods should be considered within the scope of the present invention.

Claims (20)

A memory cell having a memory transistor and a selection transistor sharing a common gate, the memory cell comprising two independent and separate threshold voltage regulators injected into different channel region portions of the memory cell substrate, wherein one threshold voltage regulator And a threshold voltage adjusting part arranged with respect to the selection transistor to influence the threshold voltage of the selection transistor, wherein the other threshold voltage adjusting part is disposed with respect to the selection transistor to influence the threshold voltage of the selection transistor. The memory cell of claim 1, wherein the threshold voltage adjusting unit disposed with respect to the memory transistor is formed of n-type impurities. The memory cell of claim 2, wherein the n-type impurity is selected from the group consisting of arsenic and phosphorus. The memory cell of claim 1, wherein the threshold voltage adjusting unit disposed with respect to the selection transistor is formed of a p-type impurity. The memory cell of claim 4, wherein the p-type impurity is selected from the group consisting of boron and boron fluoride (BF ₂ ). Split-gate memory cells made of semiconductor devices are: a) a substrate having a channel region, b) a memory transistor having a floating gate; The channel region includes a portion adjacent to the floating gate and a portion extending outside the floating gate, c) a first threshold voltage regulator injected into a portion of the channel region adjacent to the floating gate; d) a selection transistor having a gate electrode shared with the memory transistor; e) a second threshold voltage adjusting part injected into a portion of the channel region extending outside the floating gate. 7. The divided gate memory cell of claim 6, wherein the first threshold voltage adjusting part is formed of an n-type impurity selected from the group consisting of arsenic and phosphorus. 7. The divided gate memory cell of claim 6, wherein the second threshold voltage adjusting part is formed of a p-type impurity selected from the group consisting of boron and boron fluoride (BF ₂ ). In the method of manufacturing a split gate memory cell, a) implanting a first threshold voltage regulating impurity into a channel region of a memory cell substrate; b) forming a floating gate over a portion of the channel region of the substrate, and c) injecting a second threshold voltage regulating impurity into a substrate channel region outside the portion of the channel region where the floating gate is warmed. 10. The method of claim 9, wherein injecting the first threshold voltage regulating impurity comprises forming an oxide film on the substrate and implanting an impurity through the oxide film. . The method of claim 10, wherein the implanting the impurity through the oxide film comprises implanting an n-type impurity selected from the group consisting of arsenic and phosphorus. The method of claim 9, wherein the forming of the floating gate in a portion of the channel region of the substrate comprises: a) depositing a layer of polysilicon material on the substrate, b) coating a protective photoresist layer over a portion of the polysilicon material layer, c) etching a portion of the polysilicon material layer not warmed with the protective photoresist layer, and d) removing the protective photoresist layer. 10. The method of claim 9, wherein injecting the second threshold voltage regulating impurity comprises injecting a p-type impurity into a portion of a channel region in which the floating gate is not heated. . 10. The method of claim 9, further comprising forming a select gate over the floating gate and a portion of a channel region outside the floating gate. 15. The method of claim 14, wherein forming the select gate comprises: a) depositing a layer of polysilicon material over the floating gate and the substrate, b) coating a protective photoresist layer over a portion of the polysilicon material layer, c) etching the portion of the polysilicon material layer not warmed with the protective photoresist layer, and d) removing the protective photoresist layer. 15. The method of claim 14, further comprising forming a dielectric layer between the floating gate and the select gate. 10. The method of claim 9, wherein the forming of the floating gate over a portion of the channel region of the substrate comprises: injecting a first threshold voltage regulating impurity into the channel region of the memory cell substrate; And injecting a second threshold voltage regulating impurity into the substrate channel region. 18. The method of claim 17, wherein injecting the first threshold voltage regulating impurity is sufficient to inject an impurity atom into the channel region of the substrate covered with the floating gate through the floating gate and in the substrate region outside the floating gate. And implanting an N-type impurity at an energy level sufficient to be deeply implanted into the floating gate outer substrate region to have a negligible effect on the threshold voltage. 18. The method of claim 17, wherein injecting the second threshold voltage regulating impurity is sufficient to allow impurity atoms to be implanted into the substrate channel region outside of the channel region portion covered with the floating gate and impurity atoms penetrate the floating gate. And implanting a p-type impurity at an energy level that is not so high that it can be implanted in a channel region covered with a floating gate. 10. The method of claim 9, wherein injecting the first threshold voltage regulating impurity comprises injecting the impurity at an implantation amount of 0 to 5.0 x 10 ¹⁴ cm ^-2 , and injecting the second threshold voltage regulating impurity. The method of manufacturing a divided gate memory cell comprising the step of injecting impurities in an injection amount of 0 to 5.0 x 10 ¹⁴ cm ^-2 .