KR20010068540A - The method of forming an contact pad in semiconductor memory devices - Google Patents

Abstract

PURPOSE: A method for forming a contact pad of a semiconductor memory device is provided to improve junction feature of a cell transistor by forming a contact pad as a multi-layered poly silicon layer and controlling density of a dopant. CONSTITUTION: The first conductive layer(314) and the second conductive layer(316) are smoothed through an etch-back or a CMP process so as for an upper part of an interlayer dielectric(310) to be exposed, thereby forming a contact pad(318). A gate pattern(306) is formed on a semiconductor substrate on which active regions are formed. A spacer dielectric layer is formed in a conformal manner on a front surface of the semiconductor substrate including the gate pattern. An interlayer dielectric(310) is formed on the spacer dielectric layer. The interlayer dielectric is patterned. The spacer dielectric layer exposed at this time is etched to form a gate spacer. At the same time, a contact pad hole is formed so as for at least one of the active regions to be exposed. A conductive layer is formed with a plurality of layers on the interlayer dielectric including the contact pad hole. A contact pad is formed on the interlayer dielectric.

Description

The contact pad formation method of a semiconductor memory device {THE METHOD OF FORMING AN CONTACT PAD IN SEMICONDUCTOR MEMORY DEVICES}

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, to a method of forming a contact pad of a semiconductor memory device.

As the semiconductor device is highly integrated, the size of the semiconductor elements constituting the semiconductor device gradually decreases. Accordingly, the manufacturing method of semiconductor devices including semiconductor elements is complicated and strictly controlled. In particular, in the method of manufacturing a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) device, as design rules are reduced, it is necessary to form a miniaturized semiconductor device on a limited-size cell, which makes the manufacturing method difficult. Is increased.

For example, in a manufacturing process of a semiconductor memory device, a storage node contact forming process between a source / drain region and a capacitor formed in an active region of a semiconductor substrate, or the source Bit line contact forming process between the / drain region and the bit line. In order to form the contacts, an interlayer insulating layer is etched to form a contact hole. In this case, when misalignment occurs, the gate electrode is damaged. Therefore, in order to solve the problem caused by misalignment, a contact pad is formed on the source / drain region of the semiconductor substrate, and a contact is formed on the contact pad. In this case, a gate spacer is formed on the sidewall of the gate electrode, and a method of forming a self-aligned contact (SAC), which is used as an etch stop layer when forming a contact, is widely used.

Hereinafter, a method for forming a contact pad of a semiconductor memory device according to the related art will be described in detail with reference to the accompanying drawings.

1A through 1E are cross-sectional views sequentially illustrating contact pad forming processes of a conventional semiconductor memory device.

Referring to FIG. 1A, an isolation region 102 is formed on a semiconductor substrate 100 to define an active region 104. The device isolation layer 102, that is, the field oxide layer may be formed by any one of a LOCOS (LOCal Oxidation Silicon) method or a shallow trench isolation (STI) method. Next, a gate oxide film (not shown) is formed on the semiconductor substrate 100 in a thin thickness, for example, in a thickness of 70 kPa to 80 kPa. Next, the polysilicon film, the silicide film, and the capping layer are sequentially stacked and patterned to form a gate pattern 106 including the gate electrode 106a and the capping layer 106b formed of the polysilicon film and the silicide film. ). Then, the source / drain regions 107 are formed in the semiconductor substrate 100 exposed to both sides of the gate pattern 106 through an ion implantation process. The ion implantation process is a series of processes for forming a desired dopant ions, manipulating the dopant ions to have energy, and injecting a certain amount of the dopant to a desired depth into the wafer surface to conduct a portion of the semiconductor wafer. At this time, the semiconductor substrate 100 under the gate pattern 106 between the source / drain regions 107 becomes a channel region, and the length of the channel region, that is, the distance between the source / drain regions 107 is formed as L. FIG. .

An etching process and an ion implantation process are performed to form the gate pattern 106 and the source / drain regions 107. At this time, the etching process uses a dry etching method, wherein the surface of the active region 104 of the semiconductor substrate exposed to the accelerated etchant is damaged by the impact caused by the etchant. In addition, during the ion implantation process, the surface of the active region of the semiconductor substrate is damaged by the implanted ions formed to have high energy (site I). Accordingly, the gratings of silicon constituting the semiconductor substrate are damaged on the surface and the inside of the active region of the semiconductor substrate, thereby causing defects. The defects include point defects, line defects, etc., and these defects have a lattice structure in which the source / drain regions are not dense.

Referring to FIG. 1B, a spacer insulating layer 108 for forming a spacer and protecting a gate pattern is conformally formed on a semiconductor substrate 100 including the gate pattern 106. Next, an interlayer insulating layer 110 is formed on the entire surface of the semiconductor substrate 100 including the spacer insulating layer 108. In this case, the interlayer insulating layer 110 is formed of an oxide film, for example, a fluidity film having good fluidity such as BPSG (BoroPhosphor Silicate Glass). The planarization process is performed.

Referring to FIG. 1C, the interlayer insulating layer 110 is patterned, and the spacer insulating layer 108 exposed at this time is etched to form a gate spacer 111, and the source / drain region 107 is formed. The contact pad hole 112 is formed to be exposed. In this case, the front etching is performed by a dry etching method.

1D and 1E, a conductive film 114 is stacked on the interlayer insulating layer 110 including the contact pad hole 112 to fill the contact pad hole 112. The conductive layer 114 is made of polysilicon doped with a high concentration, and planarizes the conductive layer 114 to form a contact pad 116. The planarization is accomplished through an etch-back or chemical mechanical polishing (CMP) method.

However, in the method of forming the contact pad as described above, the conductive film 114 constituting the contact pad 116 is made of highly doped polysilicon, and as described above, the silicon lattice of the semiconductor substrate is damaged. It is formed in contact with the defect generation site | part (I site | part of FIG. 1A) which generate | occur | produced. Therefore, the dopants heavily doped in polysilicon may damage the lattice and diffuse to the defect-producing sites, thereby degrading bonding properties. For example, the dopants diffused to the defect site shorten the channel region length of the cell transistor to L ′, resulting in leakage current due to the punch through phenomenon in which current flows before the threshold voltage. Done. Accordingly, the junction characteristics of the semiconductor DRAM device are degraded, and device operation defects such as causing a failure in the refresh operation of the semiconductor DRAM device occur.

SUMMARY OF THE INVENTION The present invention has been proposed to solve the problem of forming a contact pad of a semiconductor memory device according to the above-described prior art, wherein the contact pad is formed of a multi-layer polysilicon layer and the dopant concentration is adjusted to bond the cell transistors. An object of the present invention is to provide a method for forming a contact pad of a semiconductor memory device which can improve characteristics.

1A through 1E are cross-sectional views sequentially illustrating contact pad forming processes of a semiconductor memory device according to the related art.

2A through 2F are cross-sectional views sequentially illustrating contact pad forming processes of a semiconductor memory device according to example embodiments.

* Brief description of the main parts of the drawing

100, 300: semiconductor substrate 102, 302: device isolation film

104, 304: active region 106, 306: gate pattern

107, 307: source / drain regions 108, 308: spacer insulating film

110, 310: interlayer insulating film 111, 311: gate spacer

112 and 312: contact pad hole 114: contact pad conductive film

314: First conductive film 316: Second conductive film

The contact pad forming method of the semiconductor memory device according to the present invention for achieving the above object, first to form a gate pattern on a semiconductor substrate in which an active region is defined and to form a spacer insulating film on the entire surface of the semiconductor substrate including the gate pattern Form. Next, an interlayer insulating film is formed and patterned on the spacer insulating film to etch the spacer insulating film exposed at this time to form a gate spacer, and to form a contact pad hole so that at least one of the active regions is exposed. Next, a conductive film including at least two or more multilayers is formed on the interlayer insulating film including the contact pad hole and planarized to form a contact pad.

According to an embodiment of the present invention, a method of forming a conductive film may include: conformally forming a first conductive film on the interlayer insulating film including the contact pad hole; A second conductive layer is formed on the first conductive layer to fill the contact pad hole, wherein the first conductive layer and the second conductive layer are made of doped polysilicon, and the first conductive layer is lower than the second conductive layer. Forming into polysilicon having a low concentration of dopant concentration.

According to an exemplary embodiment of the present invention, the first conductive layer may be made of polysilicon undoped, and may be formed to have a thickness thinner than that of the second conductive layer, for example, 100 to 1,000 mm3. do.

(Example)

Hereinafter, a method of forming a contact pad of a semiconductor memory device according to an embodiment of the present invention will be described in detail.

2A through 2F are cross-sectional views sequentially illustrating contact pad forming processes of a semiconductor memory device according to example embodiments.

In FIG. 2A, the device isolation layer 302 is formed on the semiconductor substrate 300 to define the active region 304. The device isolation layer 302, that is, the field oxide layer, may be formed by any one of a LOCOS (LOCal Oxidation Silicon) method or a shallow trench isolation (STI) method. Next, a gate oxide film (not shown) is formed thin on the semiconductor substrate 300 to have a thickness of, for example, 70 kPa to 80 kPa. Next, a gate pattern 306 is formed by sequentially stacking and patterning a gate polysilicon, a silicide layer, and a capping layer on the semiconductor substrate 300 including the gate oxide layer. In this case, the gate pattern 306 includes a gate electrode 306a and a capping layer 306b including a polysilicon film and a silicide film. Next, a source / drain region 307 is formed on the active region 304 of the semiconductor substrate 100 exposed to both sides of the gate pattern 106 through an ion implantation process.

As described above, when the gate pattern forming process including dry etching and the ion implantation process in which the dopants having high energy are forcibly injected into the active region of the semiconductor substrate are damaged, the surface and the inside of the active region of the semiconductor substrate are damaged. Occurs. At this time, the lattice of silicon constituting the semiconductor substrate on and in the surface of the active region of the damaged semiconductor substrate is damaged and defects are generated. The defects include point defects, line defects, and the like, and the defects cause the silicon wafer in the active region of the semiconductor substrate, ie, the source / drain regions, to which ion implantation is performed, to have a dense lattice structure.

In FIG. 2B, a spacer insulating layer 308 for forming a spacer and protecting a gate pattern is conformally formed on a semiconductor substrate 300 including the gate pattern 306. Next, an interlayer insulating layer 310 is formed on the entire surface of the semiconductor substrate 300 including the spacer insulating layer 308. In this case, the interlayer insulating film 310 is formed of an oxide film, for example, a fluidity film having good fluidity such as BPSG (BoroPhosphor Silicate Glass), and the like. The interlayer insulating layer 310 is flowed through heat treatment and the CMP process is performed to planarize the interlayer insulating layer 310.

In FIG. 2C, the interlayer insulating layer 310 is patterned, and the spacer insulating layer 308 exposed at this time is etched to form a gate spacer 311 and the source / drain region 307 is exposed. The contact pad hole 312 is formed as much as possible.

2D and 2E, a first conductive layer 314 is conformally formed inside the contact pad hole 312 and on the interlayer insulating layer 310. The first conductive film 314 is made of low concentration polysilicon and is formed to a thickness of 100 kPa to 1,000 kPa. The first conductive layer 314 may be formed of polysilicon that does not contain a dopant. Next, a second conductive layer 316 is formed on the first conductive layer 314 to fill the contact pad hole 312. The second conductive layer 316 is made of polysilicon doped at a high concentration.

In FIG. 2F, the first conductive layer 314 and the second conductive layer 316 are planarized so as to expose an upper portion of the interlayer insulating layer 310 through an etch-back or CMP process. 318 is formed.

According to the present invention, the first conductive layer 314 is formed of low concentration doped polysilicon or undoped polysilicon. Accordingly, the first conductive layer 314 prevents the high concentration dopants in the second conductive layer 316 forming the majority of the contact pads from diffusing into the source / drain regions of the semiconductor substrate. Accordingly, the dopants inside the contact pads are prevented from diffusing into the source / drain regions through defects occurring in the source / drain regions of the semiconductor substrate, thereby maintaining a constant distance between the source / drain regions, that is, the channel length L. . In addition, the formation of leakage current and punch through phenomenon in the channel region can be prevented, so that the bonding characteristics, the refresh characteristics, and the resistance characteristics of the semiconductor DRAM device can be maintained stably.

According to the present invention, the conductive film forming the contact pad of the semiconductor memory device is multilayered, and the first conductive film in the contact hole is formed of polysilicon without low concentration or dopant doping, so that the source / drain region of the cell transistor and the contact pad are stabilized. The contact pad can be formed while maintaining the contact state. This prevents current leakage in the channel region of the cell transistor and maintains a stable junction state, thereby improving refresh characteristics of the semiconductor DRAM device and obtaining stable operation characteristics of the transistor.

Claims (3)

Forming a gate pattern on a semiconductor substrate in which an active region is defined; Conformally forming a spacer insulating film on an entire surface of the semiconductor substrate including the gate pattern; Forming an interlayer insulating film on the spacer insulating film; Patterning the interlayer insulating film, wherein the spacer insulating film is etched through the entire surface to form a gate spacer, and at least one contact pad hole is formed to expose at least one active region; And Forming a contact pad by forming and planarizing a conductive film formed of at least two layers on the interlayer insulating film including the contact pad hole, and forming a contact pad. The method of claim 1, Forming the conductive film, Conformally forming a first conductive film on the interlayer insulating film including the contact pad hole; And And forming a second conductive layer on the first conductive layer to fill the contact pad hole. Wherein the first conductive layer and the second conductive layer are made of doped polysilicon, and wherein the first conductive layer has a lower concentration of dopant than the second conductive layer. The method of claim 2, The first conductive layer is made of polysilicon without a dopant, and has a thickness of 100 to 1,000 Å.